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https://github.com/projectacrn/acrn-hypervisor.git
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f6bf0b809d
This patch implements risc-v specific timer codes. Basically, risc-v adapts to acrn timer framework with some specific behaviors. So far, it enables sstc support in h-mode. Tracked-On: #8792 Signed-off-by: Haicheng Li <haicheng.li@outlook.com> Co-developed-by: Yong Li <yong.li@intel.com> Signed-off-by: Yong Li <yong.li@intel.com> Co-developed-by: Yi Y Sun <yi.y.sun@intel.com> Signed-off-by: Yi Y Sun <yi.y.sun@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
56 lines
945 B
C
56 lines
945 B
C
/*
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* Copyright (C) 2023-2024 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#include <softirq.h>
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#include <timer.h>
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#include <asm/timer.h>
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#include <asm/sbi.h>
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#include <asm/qemu.h>
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#include <asm/cpu.h>
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#define HOST_CPUFREQ 10000000
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#define STOP_TIMER 0xFFFFFFFFFFFFFFFF
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void timer_irq_handler(void)
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{
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arch_set_timer_count(STOP_TIMER);
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fire_softirq(SOFTIRQ_TIMER);
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}
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void arch_init_timer(void)
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{
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return;
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}
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/* FIXME:
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* Such short arch_xxx function need be moved into header file with
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* static inline prefix.
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*/
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uint64_t arch_cpu_ticks(void)
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{
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uint64_t tick;
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asm volatile (
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"rdtime %0":"=r"(tick):: "memory");
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return tick;
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}
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uint32_t arch_cpu_tickrate(void)
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{
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return HOST_CPUFREQ / 1000;
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}
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void arch_set_timer_count(uint64_t timeout)
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{
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#ifdef CONFIG_SSTC
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cpu_csr_write(stimecmp, timeout);
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#else
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sbi_set_timer(timeout);
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#endif
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}
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