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7a3a539b17
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
153 lines
5.3 KiB
C
153 lines
5.3 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* cpuid.h
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*
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* Created on: Jan 4, 2018
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* Author: don
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*/
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#ifndef CPUID_H_
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#define CPUID_H_
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/* CPUID bit definitions */
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#define CPUID_ECX_SSE3 (1<<0)
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#define CPUID_ECX_PCLMUL (1<<1)
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#define CPUID_ECX_DTES64 (1<<2)
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#define CPUID_ECX_MONITOR (1<<3)
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#define CPUID_ECX_DS_CPL (1<<4)
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#define CPUID_ECX_VMX (1<<5)
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#define CPUID_ECX_SMX (1<<6)
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#define CPUID_ECX_EST (1<<7)
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#define CPUID_ECX_TM2 (1<<8)
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#define CPUID_ECX_SSSE3 (1<<9)
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#define CPUID_ECX_CID (1<<10)
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#define CPUID_ECX_FMA (1<<12)
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#define CPUID_ECX_CX16 (1<<13)
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#define CPUID_ECX_ETPRD (1<<14)
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#define CPUID_ECX_PDCM (1<<15)
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#define CPUID_ECX_DCA (1<<18)
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#define CPUID_ECX_SSE4_1 (1<<19)
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#define CPUID_ECX_SSE4_2 (1<<20)
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#define CPUID_ECX_x2APIC (1<<21)
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#define CPUID_ECX_MOVBE (1<<22)
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#define CPUID_ECX_POPCNT (1<<23)
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#define CPUID_ECX_AES (1<<25)
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#define CPUID_ECX_XSAVE (1<<26)
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#define CPUID_ECX_OSXSAVE (1<<27)
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#define CPUID_ECX_AVX (1<<28)
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#define CPUID_EDX_FPU (1<<0)
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#define CPUID_EDX_VME (1<<1)
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#define CPUID_EDX_DE (1<<2)
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#define CPUID_EDX_PSE (1<<3)
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#define CPUID_EDX_TSC (1<<4)
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#define CPUID_EDX_MSR (1<<5)
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#define CPUID_EDX_PAE (1<<6)
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#define CPUID_EDX_MCE (1<<7)
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#define CPUID_EDX_CX8 (1<<8)
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#define CPUID_EDX_APIC (1<<9)
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#define CPUID_EDX_SEP (1<<11)
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#define CPUID_EDX_MTRR (1<<12)
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#define CPUID_EDX_PGE (1<<13)
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#define CPUID_EDX_MCA (1<<14)
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#define CPUID_EDX_CMOV (1<<15)
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#define CPUID_EDX_PAT (1<<16)
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#define CPUID_EDX_PSE36 (1<<17)
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#define CPUID_EDX_PSN (1<<18)
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#define CPUID_EDX_CLF (1<<19)
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#define CPUID_EDX_DTES (1<<21)
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#define CPUID_EDX_ACPI (1<<22)
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#define CPUID_EDX_MMX (1<<23)
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#define CPUID_EDX_FXSR (1<<24)
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#define CPUID_EDX_SSE (1<<25)
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#define CPUID_EDX_SSE2 (1<<26)
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#define CPUID_EDX_SS (1<<27)
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#define CPUID_EDX_HTT (1<<28)
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#define CPUID_EDX_TM1 (1<<29)
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#define CPUID_EDX_IA64 (1<<30)
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#define CPUID_EDX_PBE (1<<31)
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/* CPUID.07H:EBX.TSC_ADJUST*/
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#define CPUID_EBX_TSC_ADJ (1<<1)
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/* CPUID.07H:EDX.IBRS_IBPB*/
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#define CPUID_EDX_IBRS_IBPB (1<<26)
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/* CPUID.07H:EDX.STIBP*/
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#define CPUID_EDX_STIBP (1<<27)
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/* CPUID.80000001H:EDX.Page1GB*/
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#define CPUID_EDX_PAGE1GB (1<<26)
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/* CPUID.07H:EBX.INVPCID*/
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#define CPUID_EBX_INVPCID (1<<10)
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/* CPUID.01H:ECX.PCID*/
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#define CPUID_ECX_PCID (1<<17)
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/* CPUID source operands */
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#define CPUID_VENDORSTRING 0
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#define CPUID_FEATURES 1
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#define CPUID_TLB 2
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#define CPUID_SERIALNUM 3
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#define CPUID_EXTEND_FEATURE 7
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#define CPUID_EXTEND_FUNCTION_1 0x80000001
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enum cpuid_cache_idx {
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CPUID_VENDORSTRING_CACHE_IDX = 0,
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CPUID_FEATURES_CACHE_IDX,
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CPUID_EXTEND_FEATURE_CACHE_IDX,
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CPUID_EXTEND_FEATURE_CACHE_MAX
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};
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struct cpuid_cache_entry {
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uint32_t a;
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uint32_t b;
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uint32_t c;
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uint32_t d;
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uint32_t inited;
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uint32_t reserved;
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};
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static inline void native_cpuid_count(uint32_t op, uint32_t count,
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uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *d)
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{
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/* Execute CPUID instruction and save results */
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asm volatile("cpuid":"=a"(*a), "=b"(*b),
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"=c"(*c), "=d"(*d)
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: "a"(op), "c" (count));
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}
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void cpuid_count(uint32_t op, uint32_t count,
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uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *d);
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#define cpuid(op, a, b, c, d) cpuid_count(op, 0, a, b, c, d)
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void emulate_cpuid(struct vcpu *vcpu, uint32_t src_op, uint32_t *eax_ptr,
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uint32_t *ebx_ptr, uint32_t *ecx_ptr, uint32_t *edx_ptr);
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#endif /* CPUID_H_ */
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