diff --git a/kernel/configs/arm64_kata_kvm_4.19.x b/kernel/configs/arm64_kata_kvm_4.14.x similarity index 86% rename from kernel/configs/arm64_kata_kvm_4.19.x rename to kernel/configs/arm64_kata_kvm_4.14.x index c0db14c6ef..c1f1e602d7 100644 --- a/kernel/configs/arm64_kata_kvm_4.19.x +++ b/kernel/configs/arm64_kata_kvm_4.14.x @@ -1,14 +1,41 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 4.19.8 Kernel Configuration +# Linux/arm64 4.14.72 Kernel Configuration # - -# -# Compiler: gcc (Ubuntu/Linaro 7.3.0-27ubuntu1~18.04) 7.3.0 -# -CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=70300 -CONFIG_CLANG_VERSION=0 +CONFIG_ARM64=y +CONFIG_64BIT=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_CONT_SHIFT=4 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_HAVE_GENERIC_GUP=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_SMP=y +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_EXTABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y @@ -17,10 +44,10 @@ CONFIG_THREAD_INFO_IN_TASK=y # General setup # CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" # CONFIG_COMPILE_TEST is not set CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set -CONFIG_BUILD_SALT="" CONFIG_DEFAULT_HOSTNAME="kata-container" CONFIG_SWAP=y CONFIG_SYSVIPC=y @@ -28,6 +55,7 @@ CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_FHANDLE=y # CONFIG_USELIB is not set # CONFIG_AUDIT is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y @@ -48,7 +76,6 @@ CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y @@ -65,9 +92,6 @@ CONFIG_NO_HZ_IDLE=y # CONFIG_NO_HZ_FULL is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set # # CPU/Task time and stats accounting @@ -82,7 +106,6 @@ CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_CPU_ISOLATION=y # # RCU Subsystem @@ -91,23 +114,23 @@ CONFIG_TREE_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y +# CONFIG_TASKS_RCU is not set CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_CONTEXT_TRACKING=y # CONFIG_CONTEXT_TRACKING_FORCE is not set +# CONFIG_BUILD_BIN2C is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=18 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_SWAP_ENABLED=y -CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y # CONFIG_DEBUG_BLK_CGROUP is not set CONFIG_CGROUP_WRITEBACK=y @@ -125,13 +148,13 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_SOCK_CGROUP_DATA=y +# CONFIG_CHECKPOINT_RESTORE is not set CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y CONFIG_NET_NS=y -# CONFIG_CHECKPOINT_RESTORE is not set CONFIG_SCHED_AUTOGROUP=y # CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set @@ -151,11 +174,14 @@ CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_BPF=y # CONFIG_EXPERT is not set CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set CONFIG_SYSFS_SYSCALL=y -CONFIG_FHANDLE=y +# CONFIG_SYSCTL_SYSCALL is not set CONFIG_POSIX_TIMERS=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y @@ -165,18 +191,16 @@ CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_ADVISE_SYSCALLS=y -CONFIG_MEMBARRIER=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_BASE_RELATIVE=y -# CONFIG_BPF_SYSCALL is not set # CONFIG_USERFAULTFD is not set -CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_RSEQ=y +CONFIG_PCI_QUIRKS=y +CONFIG_MEMBARRIER=y # CONFIG_EMBEDDED is not set CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set # # Kernel Performance Events And Counters @@ -188,411 +212,71 @@ CONFIG_SLAB=y # CONFIG_SLUB is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set # CONFIG_PROFILING is not set -CONFIG_ARM64=y -CONFIG_64BIT=y -CONFIG_MMU=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_CONT_SHIFT=4 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ZONE_DMA32=y -CONFIG_HAVE_GENERIC_GUP=y -CONFIG_SMP=y -CONFIG_KERNEL_MODE_NEON=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_PROC_KCORE_TEXT=y - -# -# Platform selection -# -# CONFIG_ARCH_ACTIONS is not set -# CONFIG_ARCH_SUNXI is not set -# CONFIG_ARCH_ALPINE is not set -# CONFIG_ARCH_BCM2835 is not set -# CONFIG_ARCH_BCM_IPROC is not set -# CONFIG_ARCH_BERLIN is not set -# CONFIG_ARCH_BRCMSTB is not set -# CONFIG_ARCH_EXYNOS is not set -# CONFIG_ARCH_K3 is not set -# CONFIG_ARCH_LAYERSCAPE is not set -# CONFIG_ARCH_LG1K is not set -# CONFIG_ARCH_HISI is not set -# CONFIG_ARCH_MEDIATEK is not set -# CONFIG_ARCH_MESON is not set -# CONFIG_ARCH_MVEBU is not set -# CONFIG_ARCH_QCOM is not set -# CONFIG_ARCH_REALTEK is not set -# CONFIG_ARCH_ROCKCHIP is not set -# CONFIG_ARCH_SEATTLE is not set -# CONFIG_ARCH_SYNQUACER is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_STRATIX10 is not set -# CONFIG_ARCH_TEGRA is not set -# CONFIG_ARCH_SPRD is not set -# CONFIG_ARCH_THUNDER is not set -# CONFIG_ARCH_THUNDER2 is not set -# CONFIG_ARCH_UNIPHIER is not set -# CONFIG_ARCH_VEXPRESS is not set -# CONFIG_ARCH_XGENE is not set -# CONFIG_ARCH_ZX is not set -# CONFIG_ARCH_ZYNQMP is not set - -# -# Bus support -# -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_SYSCALL=y -CONFIG_PCIEPORTBUS=y -CONFIG_HOTPLUG_PCI_PCIE=y -# CONFIG_PCIEAER is not set -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEBUG is not set -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -# CONFIG_PCIEASPM_PERFORMANCE is not set -CONFIG_PCIE_PME=y -# CONFIG_PCIE_PTM is not set -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_QUIRKS=y -CONFIG_PCI_REALLOC_ENABLE_AUTO=y -CONFIG_PCI_STUB=y -# CONFIG_PCI_PF_STUB is not set -CONFIG_PCI_ATS=y -CONFIG_PCI_ECAM=y -CONFIG_PCI_IOV=y -# CONFIG_PCI_PRI is not set -# CONFIG_PCI_PASID is not set -CONFIG_PCI_LABEL=y -CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_ACPI is not set -CONFIG_HOTPLUG_PCI_CPCI=y -CONFIG_HOTPLUG_PCI_SHPC=y - -# -# PCI controller drivers -# - -# -# Cadence PCIe controllers support -# -# CONFIG_PCIE_CADENCE_HOST is not set -# CONFIG_PCI_FTPCI100 is not set -CONFIG_PCI_HOST_COMMON=y -CONFIG_PCI_HOST_GENERIC=y -# CONFIG_PCIE_XILINX is not set -# CONFIG_PCI_XGENE is not set -# CONFIG_PCI_HOST_THUNDER_PEM is not set -# CONFIG_PCI_HOST_THUNDER_ECAM is not set - -# -# DesignWare PCI Core Support -# -# CONFIG_PCIE_DW_PLAT_HOST is not set -# CONFIG_PCI_HISI is not set -# CONFIG_PCIE_KIRIN is not set - -# -# PCI Endpoint -# -# CONFIG_PCI_ENDPOINT is not set - -# -# PCI switch controller drivers -# -# CONFIG_PCI_SW_SWITCHTEC is not set - -# -# Kernel Features -# - -# -# ARM errata workarounds via the alternatives framework -# -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_1024718=y -CONFIG_CAVIUM_ERRATUM_22375=y -CONFIG_CAVIUM_ERRATUM_23154=y -# CONFIG_CAVIUM_ERRATUM_27456 is not set -CONFIG_CAVIUM_ERRATUM_30115=y -CONFIG_QCOM_FALKOR_ERRATUM_1003=y -CONFIG_QCOM_FALKOR_ERRATUM_1009=y -CONFIG_QCOM_QDF2400_ERRATUM_0065=y -CONFIG_SOCIONEXT_SYNQUACER_PREITS=y -CONFIG_HISILICON_ERRATUM_161600802=y -CONFIG_QCOM_FALKOR_ERRATUM_E1041=y -CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_16K_PAGES is not set -# CONFIG_ARM64_64K_PAGES is not set -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARM64_VA_BITS_48 is not set -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PA_BITS=48 -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_SCHED_MC=y -CONFIG_SCHED_SMT=y -CONFIG_NR_CPUS=255 -CONFIG_HOTPLUG_CPU=y -# CONFIG_NUMA is not set -CONFIG_HOLES_IN_ZONE=y -# CONFIG_HZ_100 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_300 is not set -CONFIG_HZ_1000=y -CONFIG_HZ=1000 -CONFIG_SCHED_HRTICK=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HW_PERF_EVENTS=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_SECCOMP=y -CONFIG_PARAVIRT=y -# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set -# CONFIG_CRASH_DUMP is not set -# CONFIG_XEN is not set -CONFIG_FORCE_MAX_ZONEORDER=11 -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDEN_EL2_VECTORS=y -CONFIG_ARM64_SSBD=y -# CONFIG_ARM64_SW_TTBR0_PAN is not set - -# -# ARMv8.1 architectural features -# -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_PAN=y -# CONFIG_ARM64_LSE_ATOMICS is not set -CONFIG_ARM64_VHE=y - -# -# ARMv8.2 architectural features -# -CONFIG_ARM64_UAO=y -CONFIG_ARM64_PMEM=y -CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_SVE=y -CONFIG_ARM64_MODULE_PLTS=y -# CONFIG_RANDOMIZE_BASE is not set - -# -# Boot options -# -# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set -CONFIG_CMDLINE="" -# CONFIG_CMDLINE_FORCE is not set -CONFIG_EFI_STUB=y -CONFIG_EFI=y -# CONFIG_DMI is not set -# CONFIG_COMPAT is not set - -# -# Power management options -# -# CONFIG_SUSPEND is not set -# CONFIG_HIBERNATION is not set -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_CLK=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_CPU_PM=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y - -# -# CPU Power Management -# - -# -# CPU Idle -# -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y - -# -# ARM CPU Idle Drivers -# -# CONFIG_ARM_CPUIDLE is not set - -# -# CPU Frequency scaling -# -# CONFIG_CPU_FREQ is not set - -# -# Firmware Drivers -# -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_PSCI_CHECKER is not set -# CONFIG_ARM_SDE_INTERFACE is not set -# CONFIG_FW_CFG_SYSFS is not set -CONFIG_HAVE_ARM_SMCCC=y -# CONFIG_GOOGLE_FIRMWARE is not set - -# -# EFI (Extensible Firmware Interface) Support -# -# CONFIG_EFI_VARS is not set -CONFIG_EFI_ESRT=y -CONFIG_EFI_PARAMS_FROM_FDT=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_ARMSTUB=y -CONFIG_EFI_ARMSTUB_DTB_LOADER=y -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_TEST is not set -# CONFIG_RESET_ATTACK_MITIGATION is not set - -# -# Tegra firmware driver -# -CONFIG_ARCH_SUPPORTS_ACPI=y -CONFIG_ACPI=y -CONFIG_ACPI_GENERIC_GSI=y -CONFIG_ACPI_CCA_REQUIRED=y -# CONFIG_ACPI_DEBUGGER is not set -CONFIG_ACPI_SPCR_TABLE=y -# CONFIG_ACPI_EC_DEBUGFS is not set -CONFIG_ACPI_BUTTON=y -CONFIG_ACPI_FAN=y -# CONFIG_ACPI_DOCK is not set -CONFIG_ACPI_PROCESSOR_IDLE=y -CONFIG_ACPI_MCFG=y -CONFIG_ACPI_PROCESSOR=y -CONFIG_ACPI_HOTPLUG_CPU=y -CONFIG_ACPI_THERMAL=y -CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y -CONFIG_ACPI_TABLE_UPGRADE=y -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_CONTAINER=y -# CONFIG_ACPI_HED is not set -# CONFIG_ACPI_BGRT is not set -CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y -CONFIG_ACPI_NFIT=y -CONFIG_HAVE_ACPI_APEI=y -# CONFIG_ACPI_APEI is not set -# CONFIG_PMIC_OPREGION is not set -# CONFIG_ACPI_CONFIGFS is not set -CONFIG_ACPI_IORT=y -CONFIG_ACPI_GTDT=y -CONFIG_ACPI_PPTT=y -CONFIG_VIRTUALIZATION=y -# CONFIG_KVM is not set -# CONFIG_VHOST_NET is not set -# CONFIG_VHOST_VSOCK is not set -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set -CONFIG_ARM64_CRYPTO=y -# CONFIG_CRYPTO_SHA256_ARM64 is not set -# CONFIG_CRYPTO_SHA512_ARM64 is not set -# CONFIG_CRYPTO_SHA1_ARM64_CE is not set -# CONFIG_CRYPTO_SHA2_ARM64_CE is not set -# CONFIG_CRYPTO_SHA512_ARM64_CE is not set -# CONFIG_CRYPTO_SHA3_ARM64 is not set -# CONFIG_CRYPTO_SM3_ARM64_CE is not set -# CONFIG_CRYPTO_SM4_ARM64_CE is not set -# CONFIG_CRYPTO_GHASH_ARM64_CE is not set -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y -CONFIG_CRYPTO_CRC32_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -# CONFIG_CRYPTO_AES_ARM64_CE_CCM is not set -# CONFIG_CRYPTO_AES_ARM64_CE_BLK is not set -# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set -# CONFIG_CRYPTO_CHACHA20_NEON is not set -# CONFIG_CRYPTO_AES_ARM64_BS is not set - -# -# General architecture-dependent options -# # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_NMI=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_RCU_TABLE_FREE=y -CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CMPXCHG_DOUBLE=y CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP_FILTER=y -CONFIG_HAVE_STACKPROTECTOR=y -CONFIG_CC_HAS_STACKPROTECTOR_NONE=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_THIN_ARCHIVES=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_ARCH_MMAP_RND_BITS=18 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set CONFIG_CLONE_BACKWARDS=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y -CONFIG_REFCOUNT_FULL=y -CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +# CONFIG_REFCOUNT_FULL is not set # # GCOV-based kernel profiling # CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_PLUGIN_HOSTCC="" -CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y @@ -613,7 +297,6 @@ CONFIG_BLK_DEV_INTEGRITY=y # CONFIG_BLK_DEV_THROTTLING is not set # CONFIG_BLK_CMDLINE_PARSER is not set # CONFIG_BLK_WBT is not set -# CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_SED_OPAL is not set # @@ -655,83 +338,165 @@ CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_MQ_IOSCHED_DEADLINE=y CONFIG_MQ_IOSCHED_KYBER=y # CONFIG_IOSCHED_BFQ is not set -CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y -CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y -CONFIG_ARCH_INLINE_SPIN_LOCK=y -CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y -CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y -CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y -CONFIG_ARCH_INLINE_SPIN_UNLOCK=y -CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y -CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y -CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y -CONFIG_ARCH_INLINE_READ_LOCK=y -CONFIG_ARCH_INLINE_READ_LOCK_BH=y -CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y -CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y -CONFIG_ARCH_INLINE_READ_UNLOCK=y -CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y -CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y -CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y -CONFIG_ARCH_INLINE_WRITE_LOCK=y -CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y -CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y -CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y -CONFIG_ARCH_INLINE_WRITE_UNLOCK=y -CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y -CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y -CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y -CONFIG_INLINE_SPIN_TRYLOCK=y -CONFIG_INLINE_SPIN_TRYLOCK_BH=y -CONFIG_INLINE_SPIN_LOCK=y -CONFIG_INLINE_SPIN_LOCK_BH=y -CONFIG_INLINE_SPIN_LOCK_IRQ=y -CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y -CONFIG_INLINE_SPIN_UNLOCK_BH=y CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y -CONFIG_INLINE_READ_LOCK=y -CONFIG_INLINE_READ_LOCK_BH=y -CONFIG_INLINE_READ_LOCK_IRQ=y -CONFIG_INLINE_READ_LOCK_IRQSAVE=y CONFIG_INLINE_READ_UNLOCK=y -CONFIG_INLINE_READ_UNLOCK_BH=y CONFIG_INLINE_READ_UNLOCK_IRQ=y -CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y -CONFIG_INLINE_WRITE_LOCK=y -CONFIG_INLINE_WRITE_LOCK_BH=y -CONFIG_INLINE_WRITE_LOCK_IRQ=y -CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y CONFIG_INLINE_WRITE_UNLOCK=y -CONFIG_INLINE_WRITE_UNLOCK_BH=y CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y CONFIG_FREEZER=y # -# Executable file formats +# Platform selection # -CONFIG_BINFMT_ELF=y -CONFIG_ELFCORE=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_BINFMT_SCRIPT=y -CONFIG_BINFMT_MISC=y -CONFIG_COREDUMP=y +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BRCMSTB is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_LAYERSCAPE is not set +# CONFIG_ARCH_LG1K is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SEATTLE is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_THUNDER2 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VULCAN is not set +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQMP is not set # -# Memory Management options +# Bus support # +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEBUG is not set +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +# CONFIG_PCIE_DPC is not set +# CONFIG_PCIE_PTM is not set +CONFIG_PCI_BUS_ADDR_T_64BIT=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=y +CONFIG_PCI_ATS=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_IOV=y +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_SHPC=y + +# +# DesignWare PCI Core Support +# +# CONFIG_PCIE_DW_PLAT is not set +# CONFIG_PCI_HISI is not set +# CONFIG_PCIE_KIRIN is not set + +# +# PCI host controller drivers +# +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +# CONFIG_PCI_XGENE is not set +# CONFIG_PCI_HOST_THUNDER_PEM is not set +# CONFIG_PCI_HOST_THUNDER_ECAM is not set + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set + +# +# Kernel Features +# + +# +# ARM errata workarounds via the alternatives framework +# +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_CAVIUM_ERRATUM_22375=y +CONFIG_CAVIUM_ERRATUM_23154=y +# CONFIG_CAVIUM_ERRATUM_27456 is not set +CONFIG_CAVIUM_ERRATUM_30115=y +CONFIG_QCOM_FALKOR_ERRATUM_1003=y +CONFIG_QCOM_FALKOR_ERRATUM_1009=y +CONFIG_QCOM_QDF2400_ERRATUM_0065=y +CONFIG_QCOM_FALKOR_ERRATUM_E1041=y +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_16K_PAGES is not set +# CONFIG_ARM64_64K_PAGES is not set +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VA_BITS=39 +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_NR_CPUS=255 +CONFIG_HOTPLUG_CPU=y +# CONFIG_NUMA is not set +CONFIG_HOLES_IN_ZONE=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +CONFIG_HZ_1000=y +CONFIG_HZ=1000 +CONFIG_SCHED_HRTICK=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_FLATMEM_MANUAL is not set CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_HAVE_MEMORY_PRESENT=y @@ -740,15 +505,18 @@ CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y # CONFIG_SPARSEMEM_VMEMMAP is not set CONFIG_HAVE_MEMBLOCK=y CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MEMORY_BALLOON=y # CONFIG_COMPACTION is not set CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_BOUNCE=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y # CONFIG_MEMORY_FAILURE is not set # CONFIG_TRANSPARENT_HUGEPAGE is not set +# CONFIG_ARCH_WANTS_THP_SWAP is not set # CONFIG_CLEANCACHE is not set # CONFIG_FRONTSWAP is not set # CONFIG_CMA is not set @@ -756,11 +524,91 @@ CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y # CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y -# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set -CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_SECCOMP=y +CONFIG_PARAVIRT=y +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_XEN_DOM0=y +CONFIG_XEN=y +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_ARM64_SSBD=y +# CONFIG_ARM64_SW_TTBR0_PAN is not set + +# +# ARMv8.1 architectural features +# +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_PAN=y +# CONFIG_ARM64_LSE_ATOMICS is not set +CONFIG_ARM64_VHE=y + +# +# ARMv8.2 architectural features +# +CONFIG_ARM64_UAO=y +# CONFIG_ARM64_PMEM is not set +CONFIG_ARM64_MODULE_CMODEL_LARGE=y +# CONFIG_RANDOMIZE_BASE is not set + +# +# Boot options +# +CONFIG_CMDLINE="" +# CONFIG_CMDLINE_FORCE is not set +CONFIG_EFI_STUB=y +CONFIG_EFI=y +# CONFIG_DMI is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_SCRIPT=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=y +CONFIG_COREDUMP=y +# CONFIG_COMPAT is not set + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_HIBERNATION is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_CLK=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_CPU_PM=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# ARM CPU Idle Drivers +# +# CONFIG_ARM_CPUIDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set CONFIG_NET=y CONFIG_NET_INGRESS=y @@ -775,7 +623,6 @@ CONFIG_UNIX=y CONFIG_XFRM=y CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=y -# CONFIG_XFRM_INTERFACE is not set CONFIG_XFRM_SUB_POLICY=y CONFIG_XFRM_MIGRATE=y CONFIG_XFRM_STATISTICS=y @@ -789,12 +636,16 @@ CONFIG_IP_PNP_DHCP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_NET_IP_TUNNEL is not set # CONFIG_IP_MROUTE is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_NET_UDP_TUNNEL is not set # CONFIG_NET_FOU is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set @@ -828,6 +679,8 @@ CONFIG_IPV6=y # CONFIG_INET6_IPCOMP is not set # CONFIG_IPV6_MIP6 is not set # CONFIG_IPV6_ILA is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set CONFIG_INET6_XFRM_MODE_TRANSPORT=y CONFIG_INET6_XFRM_MODE_TUNNEL=y CONFIG_INET6_XFRM_MODE_BEET=y @@ -835,11 +688,14 @@ CONFIG_INET6_XFRM_MODE_BEET=y # CONFIG_IPV6_VTI is not set # CONFIG_IPV6_SIT is not set # CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set # CONFIG_IPV6_MULTIPLE_TABLES is not set # CONFIG_IPV6_MROUTE is not set # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set # CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set # CONFIG_NETWORK_PHY_TIMESTAMPING is not set CONFIG_NETFILTER=y CONFIG_NETFILTER_ADVANCED=y @@ -853,7 +709,6 @@ CONFIG_NETFILTER_NETLINK=y # CONFIG_NETFILTER_NETLINK_ACCT is not set # CONFIG_NETFILTER_NETLINK_QUEUE is not set # CONFIG_NETFILTER_NETLINK_LOG is not set -# CONFIG_NETFILTER_NETLINK_OSF is not set # CONFIG_NF_CONNTRACK is not set # CONFIG_NF_LOG_NETDEV is not set # CONFIG_NF_TABLES is not set @@ -918,7 +773,6 @@ CONFIG_NETFILTER_XT_MATCH_HL=y # CONFIG_NETFILTER_XT_MATCH_REALM is not set # CONFIG_NETFILTER_XT_MATCH_RECENT is not set # CONFIG_NETFILTER_XT_MATCH_SCTP is not set -# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set # CONFIG_NETFILTER_XT_MATCH_STRING is not set # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set @@ -947,8 +801,8 @@ CONFIG_IP_SET_MAX=256 # # IP: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV4 is not set # CONFIG_NF_SOCKET_IPV4 is not set -# CONFIG_NF_TPROXY_IPV4 is not set # CONFIG_NF_DUP_IPV4 is not set # CONFIG_NF_LOG_ARP is not set # CONFIG_NF_LOG_IPV4 is not set @@ -969,8 +823,8 @@ CONFIG_IP_NF_RAW=y # # IPv6: Netfilter Configuration # +# CONFIG_NF_DEFRAG_IPV6 is not set # CONFIG_NF_SOCKET_IPV6 is not set -# CONFIG_NF_TPROXY_IPV6 is not set # CONFIG_NF_DUP_IPV6 is not set CONFIG_NF_REJECT_IPV6=y # CONFIG_NF_LOG_IPV6 is not set @@ -984,14 +838,12 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=y CONFIG_IP6_NF_MATCH_MH=y CONFIG_IP6_NF_MATCH_RPFILTER=y CONFIG_IP6_NF_MATCH_RT=y -# CONFIG_IP6_NF_MATCH_SRH is not set CONFIG_IP6_NF_TARGET_HL=y CONFIG_IP6_NF_FILTER=y CONFIG_IP6_NF_TARGET_REJECT=y CONFIG_IP6_NF_MANGLE=y CONFIG_IP6_NF_RAW=y # CONFIG_BRIDGE_NF_EBTABLES is not set -# CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set @@ -1007,6 +859,7 @@ CONFIG_HAVE_NET_DSA=y # CONFIG_DECNET is not set CONFIG_LLC=y # CONFIG_LLC2 is not set +# CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set @@ -1028,19 +881,15 @@ CONFIG_NET_SCH_MULTIQ=y # CONFIG_NET_SCH_SFQ is not set # CONFIG_NET_SCH_TEQL is not set # CONFIG_NET_SCH_TBF is not set -# CONFIG_NET_SCH_CBS is not set -# CONFIG_NET_SCH_ETF is not set # CONFIG_NET_SCH_GRED is not set # CONFIG_NET_SCH_DSMARK is not set # CONFIG_NET_SCH_NETEM is not set # CONFIG_NET_SCH_DRR is not set # CONFIG_NET_SCH_MQPRIO is not set -# CONFIG_NET_SCH_SKBPRIO is not set # CONFIG_NET_SCH_CHOKE is not set # CONFIG_NET_SCH_QFQ is not set # CONFIG_NET_SCH_CODEL is not set CONFIG_NET_SCH_FQ_CODEL=y -# CONFIG_NET_SCH_CAKE is not set CONFIG_NET_SCH_FQ=y # CONFIG_NET_SCH_HHF is not set # CONFIG_NET_SCH_PIE is not set @@ -1071,15 +920,13 @@ CONFIG_NET_EMATCH_STACK=32 # CONFIG_NET_EMATCH_META is not set # CONFIG_NET_EMATCH_TEXT is not set # CONFIG_NET_EMATCH_IPSET is not set -# CONFIG_NET_EMATCH_IPT is not set # CONFIG_NET_CLS_ACT is not set CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set -# CONFIG_DNS_RESOLVER is not set +CONFIG_DNS_RESOLVER=m # CONFIG_BATMAN_ADV is not set # CONFIG_OPENVSWITCH is not set CONFIG_VSOCKETS=y -CONFIG_VSOCKETS_DIAG=y CONFIG_VIRTIO_VSOCKETS=y CONFIG_VIRTIO_VSOCKETS_COMMON=y # CONFIG_NETLINK_DIAG is not set @@ -1108,11 +955,13 @@ CONFIG_NET_FLOW_LIMIT=y # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set # CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set # CONFIG_WIRELESS is not set # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set CONFIG_NET_9P=y CONFIG_NET_9P_VIRTIO=y +# CONFIG_NET_9P_XEN is not set # CONFIG_NET_9P_DEBUG is not set # CONFIG_CAIF is not set # CONFIG_CEPH_LIB is not set @@ -1120,10 +969,10 @@ CONFIG_NET_9P_VIRTIO=y # CONFIG_PSAMPLE is not set # CONFIG_NET_IFE is not set # CONFIG_LWTUNNEL is not set +# CONFIG_DST_CACHE is not set CONFIG_GRO_CELLS=y # CONFIG_NET_DEVLINK is not set CONFIG_MAY_USE_DEVLINK=y -CONFIG_FAILOVER=y CONFIG_HAVE_EBPF_JIT=y # @@ -1139,52 +988,50 @@ CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y - -# -# Firmware loader -# CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set CONFIG_EXTRA_FIRMWARE="" -# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set CONFIG_ALLOW_DEV_COREDUMP=y # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set CONFIG_GENERIC_CPU_AUTOPROBE=y +# CONFIG_DMA_SHARED_BUFFER is not set CONFIG_GENERIC_ARCH_TOPOLOGY=y # # Bus devices # +# CONFIG_ARM_CCI400_PMU is not set +# CONFIG_ARM_CCI5xx_PMU is not set +# CONFIG_ARM_CCN is not set # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_SIMPLE_PM_BUS is not set # CONFIG_VEXPRESS_CONFIG is not set CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y -# CONFIG_GNSS is not set # CONFIG_MTD is not set CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_KOBJ=y CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y CONFIG_OF_IRQ=y CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y CONFIG_OF_RESERVED_MEM=y # CONFIG_OF_OVERLAY is not set # CONFIG_PARPORT is not set -CONFIG_PNP=y -CONFIG_PNP_DEBUG_MESSAGES=y - -# -# Protocols -# -CONFIG_PNPACPI=y CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_NULL_BLK is not set # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set @@ -1195,22 +1042,21 @@ CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_RAM_DAX=y # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +CONFIG_XEN_BLKDEV_FRONTEND=y CONFIG_VIRTIO_BLK=y # CONFIG_VIRTIO_BLK_SCSI is not set # CONFIG_BLK_DEV_RBD is not set # CONFIG_BLK_DEV_RSXX is not set - -# -# NVME Support -# # CONFIG_BLK_DEV_NVME is not set # CONFIG_NVME_FC is not set # # Misc devices # +# CONFIG_SENSORS_LIS3LV02D is not set # CONFIG_DUMMY_IRQ is not set # CONFIG_PHANTOM is not set # CONFIG_SGI_IOC4 is not set @@ -1232,11 +1078,7 @@ CONFIG_EEPROM_93CX6=y # # -# Altera FPGA firmware download module (requires I2C) -# - -# -# Intel MIC & related support +# Altera FPGA firmware download module # # @@ -1272,7 +1114,9 @@ CONFIG_EEPROM_93CX6=y # # CONFIG_GENWQE is not set # CONFIG_ECHO is not set -# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set +# CONFIG_CXL_LIB is not set # # SCSI device support @@ -1281,6 +1125,7 @@ CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y +# CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_MQ_DEFAULT=y CONFIG_SCSI_PROC_FS=y @@ -1335,8 +1180,10 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_SMARTPQI is not set # CONFIG_SCSI_UFSHCD is not set # CONFIG_SCSI_HPTIOP is not set +# CONFIG_XEN_SCSI_FRONTEND is not set # CONFIG_SCSI_SNIC is not set # CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set @@ -1367,12 +1214,10 @@ CONFIG_DM_BUFIO=y # CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set CONFIG_DM_BIO_PRISON=y CONFIG_DM_PERSISTENT_DATA=y -# CONFIG_DM_UNSTRIPED is not set # CONFIG_DM_CRYPT is not set CONFIG_DM_SNAPSHOT=y CONFIG_DM_THIN_PROVISIONING=y # CONFIG_DM_CACHE is not set -# CONFIG_DM_WRITECACHE is not set # CONFIG_DM_ERA is not set # CONFIG_DM_MIRROR is not set # CONFIG_DM_RAID is not set @@ -1401,10 +1246,11 @@ CONFIG_NET_CORE=y # CONFIG_NET_FC is not set # CONFIG_NET_TEAM is not set # CONFIG_MACVLAN is not set -# CONFIG_IPVLAN is not set # CONFIG_VXLAN is not set # CONFIG_MACSEC is not set # CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=y @@ -1422,8 +1268,8 @@ CONFIG_VIRTIO_NET=y # CONFIG_ETHERNET is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set -# CONFIG_NET_SB1000 is not set # CONFIG_MDIO_DEVICE is not set +# CONFIG_MDIO_BUS is not set # CONFIG_PHYLIB is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -1437,9 +1283,8 @@ CONFIG_VIRTIO_NET=y # Enable WiMAX (Networking options) to see the WiMAX drivers # # CONFIG_WAN is not set +CONFIG_XEN_NETDEV_FRONTEND=y # CONFIG_VMXNET3 is not set -# CONFIG_FUJITSU_ES is not set -CONFIG_NET_FAILOVER=y # CONFIG_ISDN is not set # CONFIG_NVM is not set @@ -1521,6 +1366,9 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # CONFIG_SERIAL_DEV_BUS is not set CONFIG_HVC_DRIVER=y +CONFIG_HVC_IRQ=y +CONFIG_HVC_XEN=y +CONFIG_HVC_XEN_FRONTEND=y # CONFIG_HVC_DCC is not set CONFIG_VIRTIO_CONSOLE=y # CONFIG_IPMI_HANDLER is not set @@ -1556,7 +1404,6 @@ CONFIG_HW_RANDOM_VIRTIO=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # -# CONFIG_PINCTRL is not set # CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_AVS is not set @@ -1574,28 +1421,13 @@ CONFIG_POWER_SUPPLY=y # CONFIG_BATTERY_BQ27XXX is not set # CONFIG_CHARGER_MAX8903 is not set # CONFIG_HWMON is not set -CONFIG_THERMAL=y -# CONFIG_THERMAL_STATISTICS is not set -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_OF=y -# CONFIG_THERMAL_WRITABLE_TRIPS is not set -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set -# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set -# CONFIG_THERMAL_GOV_FAIR_SHARE is not set -CONFIG_THERMAL_GOV_STEP_WISE=y -# CONFIG_THERMAL_GOV_BANG_BANG is not set -# CONFIG_THERMAL_GOV_USER_SPACE is not set -# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set -# CONFIG_THERMAL_EMULATION is not set -# CONFIG_QORIQ_THERMAL is not set - -# -# ACPI INT340X thermal drivers -# +# CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# # CONFIG_SSB is not set CONFIG_BCMA_POSSIBLE=y # CONFIG_BCMA is not set @@ -1603,10 +1435,10 @@ CONFIG_BCMA_POSSIBLE=y # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_ATMEL_FLEXCOM is not set # CONFIG_MFD_ATMEL_HLCDC is not set # CONFIG_MFD_CROS_EC is not set -# CONFIG_MFD_MADERA is not set # CONFIG_MFD_HI6421_PMIC is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_LPC_ICH is not set @@ -1615,10 +1447,12 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RTSX_PCI is not set # CONFIG_MFD_SM501 is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_SYSCON is not set # CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_TMIO is not set # CONFIG_MFD_VX855 is not set # CONFIG_REGULATOR is not set # CONFIG_RC_CORE is not set @@ -1630,21 +1464,18 @@ CONFIG_BCMA_POSSIBLE=y CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 # CONFIG_DRM is not set -# CONFIG_DRM_DP_CEC is not set # # ACP (Audio CoProcessor) Configuration # - -# -# AMD Library routines -# +# CONFIG_DRM_LIB_RANDOM is not set # # Frame buffer Devices # # CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_VGASTATE is not set # # Console display driver support @@ -1739,7 +1570,10 @@ CONFIG_RTC_DRV_PL031=y # CONFIG_UIO is not set CONFIG_VIRT_DRIVERS=y CONFIG_VIRTIO=y -CONFIG_VIRTIO_MENU=y + +# +# Virtio drivers +# CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_PCI_LEGACY=y CONFIG_VIRTIO_BALLOON=y @@ -1750,6 +1584,23 @@ CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y # # Microsoft Hyper-V guest support # +# CONFIG_HYPERV_TSCPAGE is not set + +# +# Xen driver support +# +# CONFIG_XEN_BALLOON is not set +# CONFIG_XEN_DEV_EVTCHN is not set +# CONFIG_XEN_BACKEND is not set +# CONFIG_XENFS is not set +# CONFIG_XEN_SYS_HYPERVISOR is not set +CONFIG_XEN_XENBUS_FRONTEND=y +# CONFIG_XEN_GNTDEV is not set +# CONFIG_XEN_GRANT_DEV_ALLOC is not set +CONFIG_SWIOTLB_XEN=y +CONFIG_XEN_PRIVCMD=m +CONFIG_XEN_EFI=y +CONFIG_XEN_AUTO_XLATE=y # CONFIG_STAGING is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set @@ -1764,13 +1615,15 @@ CONFIG_COMMON_CLK=y # CONFIG_CLK_HSDK is not set # CONFIG_CLK_QORIQ is not set # CONFIG_COMMON_CLK_XGENE is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set # CONFIG_HWSPINLOCK is not set # # Clock Source drivers # CONFIG_TIMER_OF=y -CONFIG_TIMER_ACPI=y CONFIG_TIMER_PROBE=y CONFIG_ARM_ARCH_TIMER=y # CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set @@ -1778,6 +1631,11 @@ CONFIG_ARM_ARCH_TIMER=y # CONFIG_HISILICON_ERRATUM_161010101 is not set # CONFIG_ARM64_ERRATUM_858921 is not set # CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set # CONFIG_MAILBOX is not set # CONFIG_IOMMU_SUPPORT is not set @@ -1789,8 +1647,6 @@ CONFIG_ARM_ARCH_TIMER=y # # Rpmsg drivers # -# CONFIG_RPMSG_VIRTIO is not set -# CONFIG_SOUNDWIRE is not set # # SOC (System On Chip) specific Drivers @@ -1805,10 +1661,6 @@ CONFIG_ARM_ARCH_TIMER=y # # CONFIG_SOC_BRCMSTB is not set -# -# NXP/Freescale QorIQ SoC drivers -# - # # i.MX SoC drivers # @@ -1816,12 +1668,8 @@ CONFIG_ARM_ARCH_TIMER=y # # Qualcomm SoC drivers # +# CONFIG_SUNXI_SRAM is not set # CONFIG_SOC_TI is not set - -# -# Xilinx SoC drivers -# -# CONFIG_XILINX_VCU is not set # CONFIG_PM_DEVFREQ is not set # CONFIG_EXTCON is not set # CONFIG_MEMORY is not set @@ -1829,17 +1677,12 @@ CONFIG_ARM_ARCH_TIMER=y # CONFIG_NTB is not set # CONFIG_VME_BUS is not set # CONFIG_PWM is not set - -# -# IRQ chip support -# CONFIG_IRQCHIP=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=1 CONFIG_ARM_GIC_V2M=y CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_PARTITION_PERCPU=y # CONFIG_IPACK_BUS is not set # CONFIG_RESET_CONTROLLER is not set @@ -1859,40 +1702,53 @@ CONFIG_PARTITION_PERCPU=y # # Performance monitor support # -# CONFIG_ARM_CCI_PMU is not set -# CONFIG_ARM_CCN is not set CONFIG_ARM_PMU=y -CONFIG_ARM_PMU_ACPI=y -# CONFIG_ARM_DSU_PMU is not set -# CONFIG_HISI_PMU is not set -# CONFIG_ARM_SPE_PMU is not set # CONFIG_RAS is not set # # Android # # CONFIG_ANDROID is not set -CONFIG_LIBNVDIMM=y -CONFIG_BLK_DEV_PMEM=y -CONFIG_ND_BLK=y -CONFIG_ND_CLAIM=y -CONFIG_ND_BTT=y -CONFIG_BTT=y -CONFIG_OF_PMEM=y -CONFIG_DAX_DRIVER=y +# CONFIG_LIBNVDIMM is not set CONFIG_DAX=y CONFIG_NVMEM=y - -# -# HW tracing support -# # CONFIG_STM is not set # CONFIG_INTEL_TH is not set # CONFIG_FPGA is not set + +# +# FSI support +# # CONFIG_FSI is not set # CONFIG_TEE is not set -# CONFIG_SIOX is not set -# CONFIG_SLIMBUS is not set + +# +# Firmware Drivers +# +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set +CONFIG_HAVE_ARM_SMCCC=y +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +# CONFIG_EFI_VARS is not set +CONFIG_EFI_ESRT=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_ARMSTUB=y +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_MESON_SM is not set + +# +# Tegra firmware driver +# +# CONFIG_ACPI is not set # # File systems @@ -1916,7 +1772,6 @@ CONFIG_XFS_FS=y # CONFIG_XFS_QUOTA is not set # CONFIG_XFS_POSIX_ACL is not set # CONFIG_XFS_RT is not set -# CONFIG_XFS_ONLINE_SCRUB is not set # CONFIG_XFS_WARN is not set # CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set @@ -1935,8 +1790,8 @@ CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_FANOTIFY=y # CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set CONFIG_AUTOFS4_FS=y -CONFIG_AUTOFS_FS=y # CONFIG_FUSE_FS is not set # CONFIG_OVERLAY_FS is not set @@ -1973,15 +1828,30 @@ CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y -CONFIG_MEMFD_CREATE=y # CONFIG_CONFIGFS_FS is not set # CONFIG_EFIVAR_FS is not set # CONFIG_MISC_FILESYSTEMS is not set CONFIG_NETWORK_FILESYSTEMS=y -# CONFIG_NFS_FS is not set +CONFIG_NFS_FS=m +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=m +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V4_1 is not set +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y # CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +# CONFIG_SUNRPC_DEBUG is not set # CONFIG_CEPH_FS is not set # CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_9P_FS=y @@ -2038,6 +1908,124 @@ CONFIG_NLS_ASCII=y # CONFIG_NLS_MAC_ROMANIAN is not set # CONFIG_NLS_MAC_TURKISH is not set # CONFIG_NLS_UTF8 is not set +CONFIG_VIRTUALIZATION=y +# CONFIG_KVM is not set +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_VSOCK is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +# CONFIG_PRINTK_TIME is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 + +# +# Compile-time checks and compiler options +# +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_ARCH_HAS_KCOV=y +# CONFIG_KCOV is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_SCHED_INFO=y +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_STACKTRACE is not set +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +CONFIG_HAVE_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_BUGVERBOSE=y + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set + +# +# Runtime Testing +# +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_SORT is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_MEMTEST is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ARM64_PTDUMP_CORE is not set +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +# CONFIG_DEBUG_WX is not set +# CONFIG_DEBUG_ALIGN_RODATA is not set +# CONFIG_ARM64_RELOC_TEST is not set +# CONFIG_CORESIGHT is not set # # Security options @@ -2069,6 +2057,7 @@ CONFIG_CRYPTO_HASH2=y # CONFIG_CRYPTO_DH is not set # CONFIG_CRYPTO_ECDH is not set # CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set # CONFIG_CRYPTO_USER is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set @@ -2084,11 +2073,6 @@ CONFIG_CRYPTO_HASH2=y # CONFIG_CRYPTO_CCM is not set # CONFIG_CRYPTO_GCM is not set # CONFIG_CRYPTO_CHACHA20POLY1305 is not set -# CONFIG_CRYPTO_AEGIS128 is not set -# CONFIG_CRYPTO_AEGIS128L is not set -# CONFIG_CRYPTO_AEGIS256 is not set -# CONFIG_CRYPTO_MORUS640 is not set -# CONFIG_CRYPTO_MORUS1280 is not set # CONFIG_CRYPTO_SEQIV is not set # CONFIG_CRYPTO_ECHAINIV is not set @@ -2096,7 +2080,6 @@ CONFIG_CRYPTO_HASH2=y # Block modes # # CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CFB is not set # CONFIG_CRYPTO_CTR is not set # CONFIG_CRYPTO_CTS is not set # CONFIG_CRYPTO_ECB is not set @@ -2132,7 +2115,6 @@ CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_SHA3 is not set -# CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set @@ -2154,7 +2136,6 @@ CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_SM4 is not set # CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set @@ -2166,7 +2147,6 @@ CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_842 is not set # CONFIG_CRYPTO_LZ4 is not set # CONFIG_CRYPTO_LZ4HC is not set -# CONFIG_CRYPTO_ZSTD is not set # # Random Number Generation @@ -2185,6 +2165,22 @@ CONFIG_CRYPTO_AES=y # Certificates for signature checking # # CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +CONFIG_ARM64_CRYPTO=y +# CONFIG_CRYPTO_SHA256_ARM64 is not set +# CONFIG_CRYPTO_SHA512_ARM64 is not set +# CONFIG_CRYPTO_SHA1_ARM64_CE is not set +# CONFIG_CRYPTO_SHA2_ARM64_CE is not set +# CONFIG_CRYPTO_GHASH_ARM64_CE is not set +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y +CONFIG_CRYPTO_CRC32_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +# CONFIG_CRYPTO_AES_ARM64_CE_CCM is not set +# CONFIG_CRYPTO_AES_ARM64_CE_BLK is not set +# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set +# CONFIG_CRYPTO_CHACHA20_NEON is not set +# CONFIG_CRYPTO_AES_ARM64_BS is not set +# CONFIG_BINARY_PRINTF is not set # # Library routines @@ -2196,9 +2192,8 @@ CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_HAS_FAST_MULTIPLIER=y -# CONFIG_INDIRECT_PIO is not set # CONFIG_CRC_CCITT is not set CONFIG_CRC16=y CONFIG_CRC_T10DIF=y @@ -2209,7 +2204,6 @@ CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set -# CONFIG_CRC64 is not set # CONFIG_CRC4 is not set # CONFIG_CRC7 is not set CONFIG_LIBCRC32C=y @@ -2218,18 +2212,15 @@ CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y # CONFIG_RANDOM32_SELFTEST is not set CONFIG_ZLIB_INFLATE=y # CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set CONFIG_DECOMPRESS_GZIP=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_DMA_DIRECT_OPS=y -CONFIG_SWIOTLB=y +# CONFIG_DMA_NOOP_OPS is not set +# CONFIG_DMA_VIRT_OPS is not set CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_NLATTR=y @@ -2237,124 +2228,10 @@ CONFIG_NLATTR=y # CONFIG_DDR is not set # CONFIG_IRQ_POLL is not set CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=m CONFIG_UCS2_STRING=y +# CONFIG_SG_SPLIT is not set CONFIG_SG_POOL=y CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_PMEM_API=y -CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set - -# -# Kernel hacking -# - -# -# printk and dmesg options -# -# CONFIG_PRINTK_TIME is not set -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 -CONFIG_CONSOLE_LOGLEVEL_QUIET=4 -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 - -# -# Compile-time checks and compiler options -# -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_FRAME_WARN=2048 -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_SECTION_MISMATCH is not set -CONFIG_SECTION_MISMATCH_WARN_ONLY=y -CONFIG_ARCH_WANT_FRAME_POINTERS=y -CONFIG_FRAME_POINTER=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_DEBUG_KERNEL is not set - -# -# Memory Debugging -# -# CONFIG_PAGE_EXTENSION is not set -# CONFIG_PAGE_POISONING is not set -# CONFIG_DEBUG_RODATA_TEST is not set -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_HAVE_ARCH_KASAN=y -# CONFIG_KASAN is not set -CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set - -# -# Debug Lockups and Hangs -# -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -CONFIG_SCHED_INFO=y -# CONFIG_DEBUG_TIMEKEEPING is not set - -# -# Lock Debugging (spinlocks, mutexes, etc...) -# -CONFIG_LOCK_DEBUGGING_SUPPORT=y -# CONFIG_WW_MUTEX_SELFTEST is not set -# CONFIG_STACKTRACE is not set -# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set -CONFIG_HAVE_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_BUGVERBOSE=y - -# -# RCU Debugging -# -CONFIG_RCU_CPU_STALL_TIMEOUT=60 -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_DMA_API_DEBUG is not set -CONFIG_RUNTIME_TESTING_MENU=y -# CONFIG_TEST_LIST_SORT is not set -# CONFIG_TEST_SORT is not set -# CONFIG_ATOMIC64_SELFTEST is not set -# CONFIG_TEST_HEXDUMP is not set -# CONFIG_TEST_STRING_HELPERS is not set -# CONFIG_TEST_KSTRTOX is not set -# CONFIG_TEST_PRINTF is not set -# CONFIG_TEST_BITMAP is not set -# CONFIG_TEST_BITFIELD is not set -# CONFIG_TEST_UUID is not set -# CONFIG_TEST_OVERFLOW is not set -# CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set -# CONFIG_TEST_IDA is not set -# CONFIG_TEST_LKM is not set -# CONFIG_TEST_USER_COPY is not set -# CONFIG_TEST_BPF is not set -# CONFIG_FIND_BIT_BENCHMARK is not set -# CONFIG_TEST_FIRMWARE is not set -# CONFIG_TEST_SYSCTL is not set -# CONFIG_TEST_UDELAY is not set -# CONFIG_TEST_STATIC_KEYS is not set -# CONFIG_TEST_KMOD is not set -# CONFIG_MEMTEST is not set -# CONFIG_BUG_ON_DATA_CORRUPTION is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y -# CONFIG_UBSAN is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y -# CONFIG_STRICT_DEVMEM is not set -# CONFIG_PID_IN_CONTEXTIDR is not set -# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set -# CONFIG_DEBUG_WX is not set -# CONFIG_DEBUG_ALIGN_RODATA is not set -# CONFIG_ARM64_RELOC_TEST is not set -# CONFIG_CORESIGHT is not set diff --git a/kernel/patches/0003-backport-Arm64-KVM-Dynamic-IPA-and-52bit-IPA-support.patch b/kernel/patches/0003-backport-Arm64-KVM-Dynamic-IPA-and-52bit-IPA-support.patch deleted file mode 100644 index a360e2fd96..0000000000 --- a/kernel/patches/0003-backport-Arm64-KVM-Dynamic-IPA-and-52bit-IPA-support.patch +++ /dev/null @@ -1,1973 +0,0 @@ -From 74e66a2f5f15dcde9c0f510e709113fa1f69c5db Mon Sep 17 00:00:00 2001 -From: Wei Chen -Date: Wed, 5 Dec 2018 08:21:10 +0000 -Subject: [PATCH] backport Arm64 KVM Dynamic IPA and 52bit IPA support to - 4.19.6 - -This patch is based on Suzuki K Poulose's -[v6,00/18] kvm: arm64: Dynamic IPA and 52bit IPA -https://patchwork.kernel.org/cover/10616271/ - -Signed-off-by: Wei Chen ---- - arch/arm/include/asm/kvm_arm.h | 4 +- - arch/arm/include/asm/kvm_host.h | 13 +- - arch/arm/include/asm/kvm_mmu.h | 20 +- - arch/arm/include/asm/stage2_pgtable.h | 54 ++-- - arch/arm64/include/asm/cpufeature.h | 22 +- - arch/arm64/include/asm/kvm_arm.h | 156 +++++++++--- - arch/arm64/include/asm/kvm_asm.h | 3 +- - arch/arm64/include/asm/kvm_host.h | 16 +- - arch/arm64/include/asm/kvm_hyp.h | 10 + - arch/arm64/include/asm/kvm_mmu.h | 47 +++- - arch/arm64/include/asm/stage2_pgtable-nopmd.h | 42 ---- - arch/arm64/include/asm/stage2_pgtable-nopud.h | 39 --- - arch/arm64/include/asm/stage2_pgtable.h | 236 +++++++++++++----- - arch/arm64/kvm/guest.c | 6 +- - arch/arm64/kvm/hyp-init.S | 3 + - arch/arm64/kvm/hyp/Makefile | 1 - - arch/arm64/kvm/hyp/s2-setup.c | 90 ------- - arch/arm64/kvm/hyp/switch.c | 4 +- - arch/arm64/kvm/hyp/tlb.c | 4 +- - arch/arm64/kvm/reset.c | 108 +++++++- - include/linux/irqchip/arm-gic-v3.h | 3 + - include/uapi/linux/kvm.h | 15 ++ - virt/kvm/arm/arm.c | 26 +- - virt/kvm/arm/mmu.c | 120 ++++----- - virt/kvm/arm/vgic/vgic-its.c | 36 +-- - virt/kvm/arm/vgic/vgic-mmio-v3.c | 2 - - 26 files changed, 652 insertions(+), 428 deletions(-) - delete mode 100644 arch/arm64/include/asm/stage2_pgtable-nopmd.h - delete mode 100644 arch/arm64/include/asm/stage2_pgtable-nopud.h - delete mode 100644 arch/arm64/kvm/hyp/s2-setup.c - -diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h -index 3ab8b3781bfe..b95f8d0d9f17 100644 ---- a/arch/arm/include/asm/kvm_arm.h -+++ b/arch/arm/include/asm/kvm_arm.h -@@ -133,8 +133,7 @@ - * space. - */ - #define KVM_PHYS_SHIFT (40) --#define KVM_PHYS_SIZE (_AC(1, ULL) << KVM_PHYS_SHIFT) --#define KVM_PHYS_MASK (KVM_PHYS_SIZE - _AC(1, ULL)) -+ - #define PTRS_PER_S2_PGD (_AC(1, ULL) << (KVM_PHYS_SHIFT - 30)) - - /* Virtualization Translation Control Register (VTCR) bits */ -@@ -161,6 +160,7 @@ - #else - #define VTTBR_X (5 - KVM_T0SZ) - #endif -+#define VTTBR_CNP_BIT _AC(1, UL) - #define VTTBR_BADDR_MASK (((_AC(1, ULL) << (40 - VTTBR_X)) - 1) << VTTBR_X) - #define VTTBR_VMID_SHIFT _AC(48, ULL) - #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) -diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h -index 3ad482d2f1eb..5ca5d9af0c26 100644 ---- a/arch/arm/include/asm/kvm_host.h -+++ b/arch/arm/include/asm/kvm_host.h -@@ -273,7 +273,7 @@ static inline void __cpu_init_stage2(void) - kvm_call_hyp(__init_stage2_translation); - } - --static inline int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext) -+static inline int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext) - { - return 0; - } -@@ -354,4 +354,15 @@ static inline void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu) {} - struct kvm *kvm_arch_alloc_vm(void); - void kvm_arch_free_vm(struct kvm *kvm); - -+static inline int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type) -+{ -+ /* -+ * On 32bit ARM, VMs get a static 40bit IPA stage2 setup, -+ * so any non-zero value used as type is illegal. -+ */ -+ if (type) -+ return -EINVAL; -+ return 0; -+} -+ - #endif /* __ARM_KVM_HOST_H__ */ -diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h -index 265ea9cf7df7..1098ffc3d54b 100644 ---- a/arch/arm/include/asm/kvm_mmu.h -+++ b/arch/arm/include/asm/kvm_mmu.h -@@ -35,16 +35,12 @@ - addr; \ - }) - --/* -- * KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation levels. -- */ --#define KVM_MMU_CACHE_MIN_PAGES 2 -- - #ifndef __ASSEMBLY__ - - #include - #include - #include -+#include - #include - #include - #include -@@ -52,6 +48,13 @@ - /* Ensure compatibility with arm64 */ - #define VA_BITS 32 - -+#define kvm_phys_shift(kvm) KVM_PHYS_SHIFT -+#define kvm_phys_size(kvm) (1ULL << kvm_phys_shift(kvm)) -+#define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - 1ULL) -+#define kvm_vttbr_baddr_mask(kvm) VTTBR_BADDR_MASK -+ -+#define stage2_pgd_size(kvm) (PTRS_PER_S2_PGD * sizeof(pgd_t)) -+ - int create_hyp_mappings(void *from, void *to, pgprot_t prot); - int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size, - void __iomem **kaddr, -@@ -355,6 +358,13 @@ static inline int hyp_map_aux_data(void) - - #define kvm_phys_to_vttbr(addr) (addr) - -+static inline void kvm_set_ipa_limit(void) {} -+ -+static inline bool kvm_cpu_has_cnp(void) -+{ -+ return false; -+} -+ - #endif /* !__ASSEMBLY__ */ - - #endif /* __ARM_KVM_MMU_H__ */ -diff --git a/arch/arm/include/asm/stage2_pgtable.h b/arch/arm/include/asm/stage2_pgtable.h -index 460d616bb2d6..f6a7ea805232 100644 ---- a/arch/arm/include/asm/stage2_pgtable.h -+++ b/arch/arm/include/asm/stage2_pgtable.h -@@ -19,43 +19,53 @@ - #ifndef __ARM_S2_PGTABLE_H_ - #define __ARM_S2_PGTABLE_H_ - --#define stage2_pgd_none(pgd) pgd_none(pgd) --#define stage2_pgd_clear(pgd) pgd_clear(pgd) --#define stage2_pgd_present(pgd) pgd_present(pgd) --#define stage2_pgd_populate(pgd, pud) pgd_populate(NULL, pgd, pud) --#define stage2_pud_offset(pgd, address) pud_offset(pgd, address) --#define stage2_pud_free(pud) pud_free(NULL, pud) -- --#define stage2_pud_none(pud) pud_none(pud) --#define stage2_pud_clear(pud) pud_clear(pud) --#define stage2_pud_present(pud) pud_present(pud) --#define stage2_pud_populate(pud, pmd) pud_populate(NULL, pud, pmd) --#define stage2_pmd_offset(pud, address) pmd_offset(pud, address) --#define stage2_pmd_free(pmd) pmd_free(NULL, pmd) -- --#define stage2_pud_huge(pud) pud_huge(pud) -+/* -+ * kvm_mmu_cache_min_pages() is the number of pages required -+ * to install a stage-2 translation. We pre-allocate the entry -+ * level table at VM creation. Since we have a 3 level page-table, -+ * we need only two pages to add a new mapping. -+ */ -+#define kvm_mmu_cache_min_pages(kvm) 2 -+ -+#define stage2_pgd_none(kvm, pgd) pgd_none(pgd) -+#define stage2_pgd_clear(kvm, pgd) pgd_clear(pgd) -+#define stage2_pgd_present(kvm, pgd) pgd_present(pgd) -+#define stage2_pgd_populate(kvm, pgd, pud) pgd_populate(NULL, pgd, pud) -+#define stage2_pud_offset(kvm, pgd, address) pud_offset(pgd, address) -+#define stage2_pud_free(kvm, pud) pud_free(NULL, pud) -+ -+#define stage2_pud_none(kvm, pud) pud_none(pud) -+#define stage2_pud_clear(kvm, pud) pud_clear(pud) -+#define stage2_pud_present(kvm, pud) pud_present(pud) -+#define stage2_pud_populate(kvm, pud, pmd) pud_populate(NULL, pud, pmd) -+#define stage2_pmd_offset(kvm, pud, address) pmd_offset(pud, address) -+#define stage2_pmd_free(kvm, pmd) pmd_free(NULL, pmd) -+ -+#define stage2_pud_huge(kvm, pud) pud_huge(pud) - - /* Open coded p*d_addr_end that can deal with 64bit addresses */ --static inline phys_addr_t stage2_pgd_addr_end(phys_addr_t addr, phys_addr_t end) -+static inline phys_addr_t -+stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) - { - phys_addr_t boundary = (addr + PGDIR_SIZE) & PGDIR_MASK; - - return (boundary - 1 < end - 1) ? boundary : end; - } - --#define stage2_pud_addr_end(addr, end) (end) -+#define stage2_pud_addr_end(kvm, addr, end) (end) - --static inline phys_addr_t stage2_pmd_addr_end(phys_addr_t addr, phys_addr_t end) -+static inline phys_addr_t -+stage2_pmd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) - { - phys_addr_t boundary = (addr + PMD_SIZE) & PMD_MASK; - - return (boundary - 1 < end - 1) ? boundary : end; - } - --#define stage2_pgd_index(addr) pgd_index(addr) -+#define stage2_pgd_index(kvm, addr) pgd_index(addr) - --#define stage2_pte_table_empty(ptep) kvm_page_empty(ptep) --#define stage2_pmd_table_empty(pmdp) kvm_page_empty(pmdp) --#define stage2_pud_table_empty(pudp) false -+#define stage2_pte_table_empty(kvm, ptep) kvm_page_empty(ptep) -+#define stage2_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp) -+#define stage2_pud_table_empty(kvm, pudp) false - - #endif /* __ARM_S2_PGTABLE_H_ */ -diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h -index 1717ba1db35d..9bc6b940141b 100644 ---- a/arch/arm64/include/asm/cpufeature.h -+++ b/arch/arm64/include/asm/cpufeature.h -@@ -262,7 +262,7 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; - /* - * CPU feature detected at boot time based on system-wide value of a - * feature. It is safe for a late CPU to have this feature even though -- * the system hasn't enabled it, although the featuer will not be used -+ * the system hasn't enabled it, although the feature will not be used - * by Linux in this case. If the system has enabled this feature already, - * then every late CPU must have it. - */ -@@ -530,6 +530,26 @@ void arm64_set_ssbd_mitigation(bool state); - static inline void arm64_set_ssbd_mitigation(bool state) {} - #endif - -+static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange) -+{ -+ switch (parange) { -+ case 0: return 32; -+ case 1: return 36; -+ case 2: return 40; -+ case 3: return 42; -+ case 4: return 44; -+ case 5: return 48; -+ case 6: return 52; -+ /* -+ * A future PE could use a value unknown to the kernel. -+ * However, by the "D10.1.4 Principles of the ID scheme -+ * for fields in ID registers", ARM DDI 0487C.a, any new -+ * value is guaranteed to be higher than what we know already. -+ * As a safe limit, we return the limit supported by the kernel. -+ */ -+ default: return CONFIG_ARM64_PA_BITS; -+ } -+} - #endif /* __ASSEMBLY__ */ - - #endif -diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h -index aa45df752a16..6f602af5263c 100644 ---- a/arch/arm64/include/asm/kvm_arm.h -+++ b/arch/arm64/include/asm/kvm_arm.h -@@ -107,6 +107,7 @@ - #define VTCR_EL2_RES1 (1 << 31) - #define VTCR_EL2_HD (1 << 22) - #define VTCR_EL2_HA (1 << 21) -+#define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT - #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK - #define VTCR_EL2_TG0_MASK TCR_TG0_MASK - #define VTCR_EL2_TG0_4K TCR_TG0_4K -@@ -120,62 +121,150 @@ - #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA - #define VTCR_EL2_SL0_SHIFT 6 - #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT) --#define VTCR_EL2_SL0_LVL1 (1 << VTCR_EL2_SL0_SHIFT) - #define VTCR_EL2_T0SZ_MASK 0x3f --#define VTCR_EL2_T0SZ_40B 24 - #define VTCR_EL2_VS_SHIFT 19 - #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) - #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) - -+#define VTCR_EL2_T0SZ(x) TCR_T0SZ(x) -+ - /* - * We configure the Stage-2 page tables to always restrict the IPA space to be - * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are - * not known to exist and will break with this configuration. - * -- * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time -- * (see hyp-init.S). -+ * The VTCR_EL2 is configured per VM and is initialised in kvm_arm_setup_stage2(). - * - * Note that when using 4K pages, we concatenate two first level page tables - * together. With 16K pages, we concatenate 16 first level page tables. - * -- * The magic numbers used for VTTBR_X in this patch can be found in Tables -- * D4-23 and D4-25 in ARM DDI 0487A.b. - */ - --#define VTCR_EL2_T0SZ_IPA VTCR_EL2_T0SZ_40B - #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ - VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1) - --#ifdef CONFIG_ARM64_64K_PAGES - /* -- * Stage2 translation configuration: -- * 64kB pages (TG0 = 1) -- * 2 level page tables (SL = 1) -+ * VTCR_EL2:SL0 indicates the entry level for Stage2 translation. -+ * Interestingly, it depends on the page size. -+ * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a -+ * -+ * ----------------------------------------- -+ * | Entry level | 4K | 16K/64K | -+ * ------------------------------------------ -+ * | Level: 0 | 2 | - | -+ * ------------------------------------------ -+ * | Level: 1 | 1 | 2 | -+ * ------------------------------------------ -+ * | Level: 2 | 0 | 1 | -+ * ------------------------------------------ -+ * | Level: 3 | - | 0 | -+ * ------------------------------------------ -+ * -+ * The table roughly translates to : -+ * -+ * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level -+ * -+ * Where TGRAN_SL0_BASE is a magic number depending on the page size: -+ * TGRAN_SL0_BASE(4K) = 2 -+ * TGRAN_SL0_BASE(16K) = 3 -+ * TGRAN_SL0_BASE(64K) = 3 -+ * provided we take care of ruling out the unsupported cases and -+ * Entry_Level = 4 - Number_of_levels. -+ * - */ --#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1) --#define VTTBR_X_TGRAN_MAGIC 38 -+#ifdef CONFIG_ARM64_64K_PAGES -+ -+#define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K -+#define VTCR_EL2_TGRAN_SL0_BASE 3UL -+ - #elif defined(CONFIG_ARM64_16K_PAGES) --/* -- * Stage2 translation configuration: -- * 16kB pages (TG0 = 2) -- * 2 level page tables (SL = 1) -- */ --#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1) --#define VTTBR_X_TGRAN_MAGIC 42 -+ -+#define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K -+#define VTCR_EL2_TGRAN_SL0_BASE 3UL -+ - #else /* 4K */ --/* -- * Stage2 translation configuration: -- * 4kB pages (TG0 = 0) -- * 3 level page tables (SL = 1) -- */ --#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1) --#define VTTBR_X_TGRAN_MAGIC 37 -+ -+#define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K -+#define VTCR_EL2_TGRAN_SL0_BASE 2UL -+ - #endif - --#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS) --#define VTTBR_X (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA) -+#define VTCR_EL2_LVLS_TO_SL0(levels) \ -+ ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT) -+#define VTCR_EL2_SL0_TO_LVLS(sl0) \ -+ ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE) -+#define VTCR_EL2_LVLS(vtcr) \ -+ VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT) - --#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X) -+#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN) -+#define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK)) -+ -+/* -+ * ARM VMSAv8-64 defines an algorithm for finding the translation table -+ * descriptors in section D4.2.8 in ARM DDI 0487C.a. -+ * -+ * The algorithm defines the expectations on the translation table -+ * addresses for each level, based on PAGE_SIZE, entry level -+ * and the translation table size (T0SZ). The variable "x" in the -+ * algorithm determines the alignment of a table base address at a given -+ * level and thus determines the alignment of VTTBR:BADDR for stage2 -+ * page table entry level. -+ * Since the number of bits resolved at the entry level could vary -+ * depending on the T0SZ, the value of "x" is defined based on a -+ * Magic constant for a given PAGE_SIZE and Entry Level. The -+ * intermediate levels must be always aligned to the PAGE_SIZE (i.e, -+ * x = PAGE_SHIFT). -+ * -+ * The value of "x" for entry level is calculated as : -+ * x = Magic_N - T0SZ -+ * -+ * where Magic_N is an integer depending on the page size and the entry -+ * level of the page table as below: -+ * -+ * -------------------------------------------- -+ * | Entry level | 4K 16K 64K | -+ * -------------------------------------------- -+ * | Level: 0 (4 levels) | 28 | - | - | -+ * -------------------------------------------- -+ * | Level: 1 (3 levels) | 37 | 31 | 25 | -+ * -------------------------------------------- -+ * | Level: 2 (2 levels) | 46 | 42 | 38 | -+ * -------------------------------------------- -+ * | Level: 3 (1 level) | - | 53 | 51 | -+ * -------------------------------------------- -+ * -+ * We have a magic formula for the Magic_N below: -+ * -+ * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels) -+ * -+ * where Number_of_levels = (4 - Level). We are only interested in the -+ * value for Entry_Level for the stage2 page table. -+ * -+ * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows: -+ * -+ * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT) -+ * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels) -+ * -+ * Here is one way to explain the Magic Formula: -+ * -+ * x = log2(Size_of_Entry_Level_Table) -+ * -+ * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another -+ * PAGE_SHIFT bits in the PTE, we have : -+ * -+ * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT) -+ * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3 -+ * where n = number of levels, and since each pointer is 8bytes, we have: -+ * -+ * x = Bits_Entry_Level + 3 -+ * = IPA_SHIFT - (PAGE_SHIFT - 3) * n -+ * -+ * The only constraint here is that, we have to find the number of page table -+ * levels for a given IPA size (which we do, see stage2_pt_levels()) -+ */ -+#define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3))) -+ -+#define VTTBR_CNP_BIT (UL(1)) - #define VTTBR_VMID_SHIFT (UL(48)) - #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) - -@@ -223,6 +312,13 @@ - - /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ - #define HPFAR_MASK (~UL(0xf)) -+/* -+ * We have -+ * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12] -+ * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12] -+ */ -+#define PAR_TO_HPFAR(par) \ -+ (((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8) - - #define kvm_arm_exception_type \ - {0, "IRQ" }, \ -diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h -index 102b5a5c47b6..aea01a09eb94 100644 ---- a/arch/arm64/include/asm/kvm_asm.h -+++ b/arch/arm64/include/asm/kvm_asm.h -@@ -30,6 +30,7 @@ - #define ARM_EXCEPTION_IRQ 0 - #define ARM_EXCEPTION_EL1_SERROR 1 - #define ARM_EXCEPTION_TRAP 2 -+#define ARM_EXCEPTION_IL 3 - /* The hyp-stub will return this for any kvm_call_hyp() call */ - #define ARM_EXCEPTION_HYP_GONE HVC_STUB_ERR - -@@ -72,8 +73,6 @@ extern void __vgic_v3_init_lrs(void); - - extern u32 __kvm_get_mdcr_el2(void); - --extern u32 __init_stage2_translation(void); -- - /* Home-grown __this_cpu_{ptr,read} variants that always work at HYP */ - #define __hyp_this_cpu_ptr(sym) \ - ({ \ -diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h -index 3d6d7336f871..60770b197a43 100644 ---- a/arch/arm64/include/asm/kvm_host.h -+++ b/arch/arm64/include/asm/kvm_host.h -@@ -53,7 +53,7 @@ DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); - - int __attribute_const__ kvm_target_cpu(void); - int kvm_reset_vcpu(struct kvm_vcpu *vcpu); --int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext); -+int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext); - void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start); - - struct kvm_arch { -@@ -61,11 +61,13 @@ struct kvm_arch { - u64 vmid_gen; - u32 vmid; - -- /* 1-level 2nd stage table, protected by kvm->mmu_lock */ -+ /* stage2 entry level table */ - pgd_t *pgd; - - /* VTTBR value associated with above pgd and vmid */ - u64 vttbr; -+ /* VTCR_EL2 value for this VM */ -+ u64 vtcr; - - /* The last vcpu id that ran on each physical CPU */ - int __percpu *last_vcpu_ran; -@@ -440,13 +442,7 @@ int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, - int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, - struct kvm_device_attr *attr); - --static inline void __cpu_init_stage2(void) --{ -- u32 parange = kvm_call_hyp(__init_stage2_translation); -- -- WARN_ONCE(parange < 40, -- "PARange is %d bits, unsupported configuration!", parange); --} -+static inline void __cpu_init_stage2(void) {} - - /* Guest/host FPSIMD coordination helpers */ - int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); -@@ -509,6 +505,8 @@ static inline int kvm_arm_have_ssbd(void) - void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu); - void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu); - -+void kvm_set_ipa_limit(void); -+ - #define __KVM_HAVE_ARCH_VM_ALLOC - struct kvm *kvm_arch_alloc_vm(void); - void kvm_arch_free_vm(struct kvm *kvm); -diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h -index 384c34397619..23aca66767f9 100644 ---- a/arch/arm64/include/asm/kvm_hyp.h -+++ b/arch/arm64/include/asm/kvm_hyp.h -@@ -155,5 +155,15 @@ void deactivate_traps_vhe_put(void); - u64 __guest_enter(struct kvm_vcpu *vcpu, struct kvm_cpu_context *host_ctxt); - void __noreturn __hyp_do_panic(unsigned long, ...); - -+/* -+ * Must be called from hyp code running at EL2 with an updated VTTBR -+ * and interrupts disabled. -+ */ -+static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm) -+{ -+ write_sysreg(kvm->arch.vtcr, vtcr_el2); -+ write_sysreg(kvm->arch.vttbr, vttbr_el2); -+} -+ - #endif /* __ARM64_KVM_HYP_H__ */ - -diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h -index d6fff7de5539..658657367f2f 100644 ---- a/arch/arm64/include/asm/kvm_mmu.h -+++ b/arch/arm64/include/asm/kvm_mmu.h -@@ -141,8 +141,16 @@ static inline unsigned long __kern_hyp_va(unsigned long v) - * We currently only support a 40bit IPA. - */ - #define KVM_PHYS_SHIFT (40) --#define KVM_PHYS_SIZE (1UL << KVM_PHYS_SHIFT) --#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1UL) -+ -+#define kvm_phys_shift(kvm) VTCR_EL2_IPA(kvm->arch.vtcr) -+#define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm)) -+#define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL)) -+ -+static inline bool kvm_page_empty(void *ptr) -+{ -+ struct page *ptr_page = virt_to_page(ptr); -+ return page_count(ptr_page) == 1; -+} - - #include - -@@ -238,12 +246,6 @@ static inline bool kvm_s2pmd_exec(pmd_t *pmdp) - return !(READ_ONCE(pmd_val(*pmdp)) & PMD_S2_XN); - } - --static inline bool kvm_page_empty(void *ptr) --{ -- struct page *ptr_page = virt_to_page(ptr); -- return page_count(ptr_page) == 1; --} -- - #define hyp_pte_table_empty(ptep) kvm_page_empty(ptep) - - #ifdef __PAGETABLE_PMD_FOLDED -@@ -517,5 +519,34 @@ static inline int hyp_map_aux_data(void) - - #define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr) - -+/* -+ * Get the magic number 'x' for VTTBR:BADDR of this KVM instance. -+ * With v8.2 LVA extensions, 'x' should be a minimum of 6 with -+ * 52bit IPS. -+ */ -+static inline int arm64_vttbr_x(u32 ipa_shift, u32 levels) -+{ -+ int x = ARM64_VTTBR_X(ipa_shift, levels); -+ -+ return (IS_ENABLED(CONFIG_ARM64_PA_BITS_52) && x < 6) ? 6 : x; -+} -+ -+static inline u64 vttbr_baddr_mask(u32 ipa_shift, u32 levels) -+{ -+ unsigned int x = arm64_vttbr_x(ipa_shift, levels); -+ -+ return GENMASK_ULL(PHYS_MASK_SHIFT - 1, x); -+} -+ -+static inline u64 kvm_vttbr_baddr_mask(struct kvm *kvm) -+{ -+ return vttbr_baddr_mask(kvm_phys_shift(kvm), kvm_stage2_levels(kvm)); -+} -+ -+static inline bool kvm_cpu_has_cnp(void) -+{ -+ return system_supports_cnp(); -+} -+ - #endif /* __ASSEMBLY__ */ - #endif /* __ARM64_KVM_MMU_H__ */ -diff --git a/arch/arm64/include/asm/stage2_pgtable-nopmd.h b/arch/arm64/include/asm/stage2_pgtable-nopmd.h -deleted file mode 100644 -index 2656a0fd05a6..000000000000 ---- a/arch/arm64/include/asm/stage2_pgtable-nopmd.h -+++ /dev/null -@@ -1,42 +0,0 @@ --/* -- * Copyright (C) 2016 - ARM Ltd -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License version 2 as -- * published by the Free Software Foundation. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program. If not, see . -- */ -- --#ifndef __ARM64_S2_PGTABLE_NOPMD_H_ --#define __ARM64_S2_PGTABLE_NOPMD_H_ -- --#include -- --#define __S2_PGTABLE_PMD_FOLDED -- --#define S2_PMD_SHIFT S2_PUD_SHIFT --#define S2_PTRS_PER_PMD 1 --#define S2_PMD_SIZE (1UL << S2_PMD_SHIFT) --#define S2_PMD_MASK (~(S2_PMD_SIZE-1)) -- --#define stage2_pud_none(pud) (0) --#define stage2_pud_present(pud) (1) --#define stage2_pud_clear(pud) do { } while (0) --#define stage2_pud_populate(pud, pmd) do { } while (0) --#define stage2_pmd_offset(pud, address) ((pmd_t *)(pud)) -- --#define stage2_pmd_free(pmd) do { } while (0) -- --#define stage2_pmd_addr_end(addr, end) (end) -- --#define stage2_pud_huge(pud) (0) --#define stage2_pmd_table_empty(pmdp) (0) -- --#endif -diff --git a/arch/arm64/include/asm/stage2_pgtable-nopud.h b/arch/arm64/include/asm/stage2_pgtable-nopud.h -deleted file mode 100644 -index 5ee87b54ebf3..000000000000 ---- a/arch/arm64/include/asm/stage2_pgtable-nopud.h -+++ /dev/null -@@ -1,39 +0,0 @@ --/* -- * Copyright (C) 2016 - ARM Ltd -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License version 2 as -- * published by the Free Software Foundation. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program. If not, see . -- */ -- --#ifndef __ARM64_S2_PGTABLE_NOPUD_H_ --#define __ARM64_S2_PGTABLE_NOPUD_H_ -- --#define __S2_PGTABLE_PUD_FOLDED -- --#define S2_PUD_SHIFT S2_PGDIR_SHIFT --#define S2_PTRS_PER_PUD 1 --#define S2_PUD_SIZE (_AC(1, UL) << S2_PUD_SHIFT) --#define S2_PUD_MASK (~(S2_PUD_SIZE-1)) -- --#define stage2_pgd_none(pgd) (0) --#define stage2_pgd_present(pgd) (1) --#define stage2_pgd_clear(pgd) do { } while (0) --#define stage2_pgd_populate(pgd, pud) do { } while (0) -- --#define stage2_pud_offset(pgd, address) ((pud_t *)(pgd)) -- --#define stage2_pud_free(x) do { } while (0) -- --#define stage2_pud_addr_end(addr, end) (end) --#define stage2_pud_table_empty(pmdp) (0) -- --#endif -diff --git a/arch/arm64/include/asm/stage2_pgtable.h b/arch/arm64/include/asm/stage2_pgtable.h -index 8b68099348e5..d352f6df8d2c 100644 ---- a/arch/arm64/include/asm/stage2_pgtable.h -+++ b/arch/arm64/include/asm/stage2_pgtable.h -@@ -19,8 +19,16 @@ - #ifndef __ARM64_S2_PGTABLE_H_ - #define __ARM64_S2_PGTABLE_H_ - -+#include - #include - -+/* -+ * PGDIR_SHIFT determines the size a top-level page table entry can map -+ * and depends on the number of levels in the page table. Compute the -+ * PGDIR_SHIFT for a given number of levels. -+ */ -+#define pt_levels_pgdir_shift(lvls) ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - (lvls)) -+ - /* - * The hardware supports concatenation of up to 16 tables at stage2 entry level - * and we use the feature whenever possible. -@@ -29,112 +37,208 @@ - * On arm64, the smallest PAGE_SIZE supported is 4k, which means - * (PAGE_SHIFT - 3) > 4 holds for all page sizes. - * This implies, the total number of page table levels at stage2 expected -- * by the hardware is actually the number of levels required for (KVM_PHYS_SHIFT - 4) -+ * by the hardware is actually the number of levels required for (IPA_SHIFT - 4) - * in normal translations(e.g, stage1), since we cannot have another level in -- * the range (KVM_PHYS_SHIFT, KVM_PHYS_SHIFT - 4). -+ * the range (IPA_SHIFT, IPA_SHIFT - 4). - */ --#define STAGE2_PGTABLE_LEVELS ARM64_HW_PGTABLE_LEVELS(KVM_PHYS_SHIFT - 4) -+#define stage2_pgtable_levels(ipa) ARM64_HW_PGTABLE_LEVELS((ipa) - 4) -+#define kvm_stage2_levels(kvm) VTCR_EL2_LVLS(kvm->arch.vtcr) - --/* -- * With all the supported VA_BITs and 40bit guest IPA, the following condition -- * is always true: -- * -- * STAGE2_PGTABLE_LEVELS <= CONFIG_PGTABLE_LEVELS -- * -- * We base our stage-2 page table walker helpers on this assumption and -- * fall back to using the host version of the helper wherever possible. -- * i.e, if a particular level is not folded (e.g, PUD) at stage2, we fall back -- * to using the host version, since it is guaranteed it is not folded at host. -- * -- * If the condition breaks in the future, we can rearrange the host level -- * definitions and reuse them for stage2. Till then... -- */ --#if STAGE2_PGTABLE_LEVELS > CONFIG_PGTABLE_LEVELS --#error "Unsupported combination of guest IPA and host VA_BITS." --#endif -- --/* S2_PGDIR_SHIFT is the size mapped by top-level stage2 entry */ --#define S2_PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - STAGE2_PGTABLE_LEVELS) --#define S2_PGDIR_SIZE (_AC(1, UL) << S2_PGDIR_SHIFT) --#define S2_PGDIR_MASK (~(S2_PGDIR_SIZE - 1)) -+/* stage2_pgdir_shift() is the size mapped by top-level stage2 entry for the VM */ -+#define stage2_pgdir_shift(kvm) pt_levels_pgdir_shift(kvm_stage2_levels(kvm)) -+#define stage2_pgdir_size(kvm) (1ULL << stage2_pgdir_shift(kvm)) -+#define stage2_pgdir_mask(kvm) ~(stage2_pgdir_size(kvm) - 1) - - /* - * The number of PTRS across all concatenated stage2 tables given by the - * number of bits resolved at the initial level. -+ * If we force more levels than necessary, we may have (stage2_pgdir_shift > IPA), -+ * in which case, stage2_pgd_ptrs will have one entry. - */ --#define PTRS_PER_S2_PGD (1 << (KVM_PHYS_SHIFT - S2_PGDIR_SHIFT)) -+#define pgd_ptrs_shift(ipa, pgdir_shift) \ -+ ((ipa) > (pgdir_shift) ? ((ipa) - (pgdir_shift)) : 0) -+#define __s2_pgd_ptrs(ipa, lvls) \ -+ (1 << (pgd_ptrs_shift((ipa), pt_levels_pgdir_shift(lvls)))) -+#define __s2_pgd_size(ipa, lvls) (__s2_pgd_ptrs((ipa), (lvls)) * sizeof(pgd_t)) -+ -+#define stage2_pgd_ptrs(kvm) __s2_pgd_ptrs(kvm_phys_shift(kvm), kvm_stage2_levels(kvm)) -+#define stage2_pgd_size(kvm) __s2_pgd_size(kvm_phys_shift(kvm), kvm_stage2_levels(kvm)) - - /* -- * KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation -- * levels in addition to the PGD. -+ * kvm_mmmu_cache_min_pages() is the number of pages required to install -+ * a stage-2 translation. We pre-allocate the entry level page table at -+ * the VM creation. - */ --#define KVM_MMU_CACHE_MIN_PAGES (STAGE2_PGTABLE_LEVELS - 1) -+#define kvm_mmu_cache_min_pages(kvm) (kvm_stage2_levels(kvm) - 1) - -- --#if STAGE2_PGTABLE_LEVELS > 3 -+/* Stage2 PUD definitions when the level is present */ -+static inline bool kvm_stage2_has_pud(struct kvm *kvm) -+{ -+ return (CONFIG_PGTABLE_LEVELS > 3) && (kvm_stage2_levels(kvm) > 3); -+} - - #define S2_PUD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(1) --#define S2_PUD_SIZE (_AC(1, UL) << S2_PUD_SHIFT) -+#define S2_PUD_SIZE (1UL << S2_PUD_SHIFT) - #define S2_PUD_MASK (~(S2_PUD_SIZE - 1)) - --#define stage2_pgd_none(pgd) pgd_none(pgd) --#define stage2_pgd_clear(pgd) pgd_clear(pgd) --#define stage2_pgd_present(pgd) pgd_present(pgd) --#define stage2_pgd_populate(pgd, pud) pgd_populate(NULL, pgd, pud) --#define stage2_pud_offset(pgd, address) pud_offset(pgd, address) --#define stage2_pud_free(pud) pud_free(NULL, pud) -+static inline bool stage2_pgd_none(struct kvm *kvm, pgd_t pgd) -+{ -+ if (kvm_stage2_has_pud(kvm)) -+ return pgd_none(pgd); -+ else -+ return 0; -+} - --#define stage2_pud_table_empty(pudp) kvm_page_empty(pudp) -+static inline void stage2_pgd_clear(struct kvm *kvm, pgd_t *pgdp) -+{ -+ if (kvm_stage2_has_pud(kvm)) -+ pgd_clear(pgdp); -+} - --static inline phys_addr_t stage2_pud_addr_end(phys_addr_t addr, phys_addr_t end) -+static inline bool stage2_pgd_present(struct kvm *kvm, pgd_t pgd) - { -- phys_addr_t boundary = (addr + S2_PUD_SIZE) & S2_PUD_MASK; -+ if (kvm_stage2_has_pud(kvm)) -+ return pgd_present(pgd); -+ else -+ return 1; -+} - -- return (boundary - 1 < end - 1) ? boundary : end; -+static inline void stage2_pgd_populate(struct kvm *kvm, pgd_t *pgd, pud_t *pud) -+{ -+ if (kvm_stage2_has_pud(kvm)) -+ pgd_populate(NULL, pgd, pud); -+} -+ -+static inline pud_t *stage2_pud_offset(struct kvm *kvm, -+ pgd_t *pgd, unsigned long address) -+{ -+ if (kvm_stage2_has_pud(kvm)) -+ return pud_offset(pgd, address); -+ else -+ return (pud_t *)pgd; - } - --#endif /* STAGE2_PGTABLE_LEVELS > 3 */ -+static inline void stage2_pud_free(struct kvm *kvm, pud_t *pud) -+{ -+ if (kvm_stage2_has_pud(kvm)) -+ pud_free(NULL, pud); -+} - -+static inline bool stage2_pud_table_empty(struct kvm *kvm, pud_t *pudp) -+{ -+ if (kvm_stage2_has_pud(kvm)) -+ return kvm_page_empty(pudp); -+ else -+ return false; -+} - --#if STAGE2_PGTABLE_LEVELS > 2 -+static inline phys_addr_t -+stage2_pud_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) -+{ -+ if (kvm_stage2_has_pud(kvm)) { -+ phys_addr_t boundary = (addr + S2_PUD_SIZE) & S2_PUD_MASK; -+ -+ return (boundary - 1 < end - 1) ? boundary : end; -+ } else { -+ return end; -+ } -+} -+ -+/* Stage2 PMD definitions when the level is present */ -+static inline bool kvm_stage2_has_pmd(struct kvm *kvm) -+{ -+ return (CONFIG_PGTABLE_LEVELS > 2) && (kvm_stage2_levels(kvm) > 2); -+} - - #define S2_PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2) --#define S2_PMD_SIZE (_AC(1, UL) << S2_PMD_SHIFT) -+#define S2_PMD_SIZE (1UL << S2_PMD_SHIFT) - #define S2_PMD_MASK (~(S2_PMD_SIZE - 1)) - --#define stage2_pud_none(pud) pud_none(pud) --#define stage2_pud_clear(pud) pud_clear(pud) --#define stage2_pud_present(pud) pud_present(pud) --#define stage2_pud_populate(pud, pmd) pud_populate(NULL, pud, pmd) --#define stage2_pmd_offset(pud, address) pmd_offset(pud, address) --#define stage2_pmd_free(pmd) pmd_free(NULL, pmd) -+static inline bool stage2_pud_none(struct kvm *kvm, pud_t pud) -+{ -+ if (kvm_stage2_has_pmd(kvm)) -+ return pud_none(pud); -+ else -+ return 0; -+} -+ -+static inline void stage2_pud_clear(struct kvm *kvm, pud_t *pud) -+{ -+ if (kvm_stage2_has_pmd(kvm)) -+ pud_clear(pud); -+} - --#define stage2_pud_huge(pud) pud_huge(pud) --#define stage2_pmd_table_empty(pmdp) kvm_page_empty(pmdp) -+static inline bool stage2_pud_present(struct kvm *kvm, pud_t pud) -+{ -+ if (kvm_stage2_has_pmd(kvm)) -+ return pud_present(pud); -+ else -+ return 1; -+} - --static inline phys_addr_t stage2_pmd_addr_end(phys_addr_t addr, phys_addr_t end) -+static inline void stage2_pud_populate(struct kvm *kvm, pud_t *pud, pmd_t *pmd) - { -- phys_addr_t boundary = (addr + S2_PMD_SIZE) & S2_PMD_MASK; -+ if (kvm_stage2_has_pmd(kvm)) -+ pud_populate(NULL, pud, pmd); -+} - -- return (boundary - 1 < end - 1) ? boundary : end; -+static inline pmd_t *stage2_pmd_offset(struct kvm *kvm, -+ pud_t *pud, unsigned long address) -+{ -+ if (kvm_stage2_has_pmd(kvm)) -+ return pmd_offset(pud, address); -+ else -+ return (pmd_t *)pud; - } - --#endif /* STAGE2_PGTABLE_LEVELS > 2 */ -+static inline void stage2_pmd_free(struct kvm *kvm, pmd_t *pmd) -+{ -+ if (kvm_stage2_has_pmd(kvm)) -+ pmd_free(NULL, pmd); -+} -+ -+static inline bool stage2_pud_huge(struct kvm *kvm, pud_t pud) -+{ -+ if (kvm_stage2_has_pmd(kvm)) -+ return pud_huge(pud); -+ else -+ return 0; -+} -+ -+static inline bool stage2_pmd_table_empty(struct kvm *kvm, pmd_t *pmdp) -+{ -+ if (kvm_stage2_has_pmd(kvm)) -+ return kvm_page_empty(pmdp); -+ else -+ return 0; -+} - --#define stage2_pte_table_empty(ptep) kvm_page_empty(ptep) -+static inline phys_addr_t -+stage2_pmd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) -+{ -+ if (kvm_stage2_has_pmd(kvm)) { -+ phys_addr_t boundary = (addr + S2_PMD_SIZE) & S2_PMD_MASK; - --#if STAGE2_PGTABLE_LEVELS == 2 --#include --#elif STAGE2_PGTABLE_LEVELS == 3 --#include --#endif -+ return (boundary - 1 < end - 1) ? boundary : end; -+ } else { -+ return end; -+ } -+} - -+static inline bool stage2_pte_table_empty(struct kvm *kvm, pte_t *ptep) -+{ -+ return kvm_page_empty(ptep); -+} - --#define stage2_pgd_index(addr) (((addr) >> S2_PGDIR_SHIFT) & (PTRS_PER_S2_PGD - 1)) -+static inline unsigned long stage2_pgd_index(struct kvm *kvm, phys_addr_t addr) -+{ -+ return (((addr) >> stage2_pgdir_shift(kvm)) & (stage2_pgd_ptrs(kvm) - 1)); -+} - --static inline phys_addr_t stage2_pgd_addr_end(phys_addr_t addr, phys_addr_t end) -+static inline phys_addr_t -+stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) - { -- phys_addr_t boundary = (addr + S2_PGDIR_SIZE) & S2_PGDIR_MASK; -+ phys_addr_t boundary = (addr + stage2_pgdir_size(kvm)) & stage2_pgdir_mask(kvm); - - return (boundary - 1 < end - 1) ? boundary : end; - } -diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c -index a6c9fbaeaefc..dd436a50fce7 100644 ---- a/arch/arm64/kvm/guest.c -+++ b/arch/arm64/kvm/guest.c -@@ -391,15 +391,15 @@ int __attribute_const__ kvm_target_cpu(void) - return KVM_ARM_TARGET_CORTEX_A53; - case ARM_CPU_PART_CORTEX_A57: - return KVM_ARM_TARGET_CORTEX_A57; -- }; -+ } - break; - case ARM_CPU_IMP_APM: - switch (part_number) { - case APM_CPU_PART_POTENZA: - return KVM_ARM_TARGET_XGENE_POTENZA; -- }; -+ } - break; -- }; -+ } - - /* Return a default generic target */ - return KVM_ARM_TARGET_GENERIC_V8; -diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S -index ea9225160786..4576b86a5579 100644 ---- a/arch/arm64/kvm/hyp-init.S -+++ b/arch/arm64/kvm/hyp-init.S -@@ -65,6 +65,9 @@ __do_hyp_init: - b.lo __kvm_handle_stub_hvc - - phys_to_ttbr x4, x0 -+alternative_if ARM64_HAS_CNP -+ orr x4, x4, #TTBR_CNP_BIT -+alternative_else_nop_endif - msr ttbr0_el2, x4 - - mrs x4, tcr_el1 -diff --git a/arch/arm64/kvm/hyp/Makefile b/arch/arm64/kvm/hyp/Makefile -index 2fabc2dc1966..82d1904328ad 100644 ---- a/arch/arm64/kvm/hyp/Makefile -+++ b/arch/arm64/kvm/hyp/Makefile -@@ -19,7 +19,6 @@ obj-$(CONFIG_KVM_ARM_HOST) += switch.o - obj-$(CONFIG_KVM_ARM_HOST) += fpsimd.o - obj-$(CONFIG_KVM_ARM_HOST) += tlb.o - obj-$(CONFIG_KVM_ARM_HOST) += hyp-entry.o --obj-$(CONFIG_KVM_ARM_HOST) += s2-setup.o - - # KVM code is run at a different exception code with a different map, so - # compiler instrumentation that inserts callbacks or checks into the code may -diff --git a/arch/arm64/kvm/hyp/s2-setup.c b/arch/arm64/kvm/hyp/s2-setup.c -deleted file mode 100644 -index 603e1ee83e89..000000000000 ---- a/arch/arm64/kvm/hyp/s2-setup.c -+++ /dev/null -@@ -1,90 +0,0 @@ --/* -- * Copyright (C) 2016 - ARM Ltd -- * Author: Marc Zyngier -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License version 2 as -- * published by the Free Software Foundation. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program. If not, see . -- */ -- --#include --#include --#include --#include -- --u32 __hyp_text __init_stage2_translation(void) --{ -- u64 val = VTCR_EL2_FLAGS; -- u64 parange; -- u64 tmp; -- -- /* -- * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS -- * bits in VTCR_EL2. Amusingly, the PARange is 4 bits, while -- * PS is only 3. Fortunately, bit 19 is RES0 in VTCR_EL2... -- */ -- parange = read_sysreg(id_aa64mmfr0_el1) & 7; -- if (parange > ID_AA64MMFR0_PARANGE_MAX) -- parange = ID_AA64MMFR0_PARANGE_MAX; -- val |= parange << 16; -- -- /* Compute the actual PARange... */ -- switch (parange) { -- case 0: -- parange = 32; -- break; -- case 1: -- parange = 36; -- break; -- case 2: -- parange = 40; -- break; -- case 3: -- parange = 42; -- break; -- case 4: -- parange = 44; -- break; -- case 5: -- default: -- parange = 48; -- break; -- } -- -- /* -- * ... and clamp it to 40 bits, unless we have some braindead -- * HW that implements less than that. In all cases, we'll -- * return that value for the rest of the kernel to decide what -- * to do. -- */ -- val |= 64 - (parange > 40 ? 40 : parange); -- -- /* -- * Check the availability of Hardware Access Flag / Dirty Bit -- * Management in ID_AA64MMFR1_EL1 and enable the feature in VTCR_EL2. -- */ -- tmp = (read_sysreg(id_aa64mmfr1_el1) >> ID_AA64MMFR1_HADBS_SHIFT) & 0xf; -- if (tmp) -- val |= VTCR_EL2_HA; -- -- /* -- * Read the VMIDBits bits from ID_AA64MMFR1_EL1 and set the VS -- * bit in VTCR_EL2. -- */ -- tmp = (read_sysreg(id_aa64mmfr1_el1) >> ID_AA64MMFR1_VMIDBITS_SHIFT) & 0xf; -- val |= (tmp == ID_AA64MMFR1_VMIDBITS_16) ? -- VTCR_EL2_VS_16BIT : -- VTCR_EL2_VS_8BIT; -- -- write_sysreg(val, vtcr_el2); -- -- return parange; --} -diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c -index ca46153d7915..7cc175c88a37 100644 ---- a/arch/arm64/kvm/hyp/switch.c -+++ b/arch/arm64/kvm/hyp/switch.c -@@ -198,7 +198,7 @@ void deactivate_traps_vhe_put(void) - - static void __hyp_text __activate_vm(struct kvm *kvm) - { -- write_sysreg(kvm->arch.vttbr, vttbr_el2); -+ __load_guest_stage2(kvm); - } - - static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu) -@@ -263,7 +263,7 @@ static bool __hyp_text __translate_far_to_hpfar(u64 far, u64 *hpfar) - return false; /* Translation failed, back to guest */ - - /* Convert PAR to HPFAR format */ -- *hpfar = ((tmp >> 12) & ((1UL << 36) - 1)) << 4; -+ *hpfar = PAR_TO_HPFAR(tmp); - return true; - } - -diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c -index 131c7772703c..4dbd9c69a96d 100644 ---- a/arch/arm64/kvm/hyp/tlb.c -+++ b/arch/arm64/kvm/hyp/tlb.c -@@ -30,7 +30,7 @@ static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm) - * bits. Changing E2H is impossible (goodbye TTBR1_EL2), so - * let's flip TGE before executing the TLB operation. - */ -- write_sysreg(kvm->arch.vttbr, vttbr_el2); -+ __load_guest_stage2(kvm); - val = read_sysreg(hcr_el2); - val &= ~HCR_TGE; - write_sysreg(val, hcr_el2); -@@ -39,7 +39,7 @@ static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm) - - static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm) - { -- write_sysreg(kvm->arch.vttbr, vttbr_el2); -+ __load_guest_stage2(kvm); - isb(); - } - -diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c -index e37c78bbe1ca..b72a3dd56204 100644 ---- a/arch/arm64/kvm/reset.c -+++ b/arch/arm64/kvm/reset.c -@@ -26,6 +26,7 @@ - - #include - -+#include - #include - #include - #include -@@ -33,6 +34,9 @@ - #include - #include - -+/* Maximum phys_shift supported for any VM on this host */ -+static u32 kvm_ipa_limit; -+ - /* - * ARMv8 Reset Values - */ -@@ -55,12 +59,12 @@ static bool cpu_has_32bit_el1(void) - } - - /** -- * kvm_arch_dev_ioctl_check_extension -+ * kvm_arch_vm_ioctl_check_extension - * - * We currently assume that the number of HW registers is uniform - * across all CPUs (see cpuinfo_sanity_check). - */ --int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext) -+int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext) - { - int r; - -@@ -82,9 +86,11 @@ int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext) - break; - case KVM_CAP_SET_GUEST_DEBUG: - case KVM_CAP_VCPU_ATTRIBUTES: -- case KVM_CAP_VCPU_EVENTS: - r = 1; - break; -+ case KVM_CAP_ARM_VM_IPA_SIZE: -+ r = kvm_ipa_limit; -+ break; - default: - r = 0; - } -@@ -133,3 +139,99 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) - /* Reset timer */ - return kvm_timer_vcpu_reset(vcpu); - } -+ -+void kvm_set_ipa_limit(void) -+{ -+ unsigned int ipa_max, pa_max, va_max, parange; -+ -+ parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 0x7; -+ pa_max = id_aa64mmfr0_parange_to_phys_shift(parange); -+ -+ /* Clamp the IPA limit to the PA size supported by the kernel */ -+ ipa_max = (pa_max > PHYS_MASK_SHIFT) ? PHYS_MASK_SHIFT : pa_max; -+ /* -+ * Since our stage2 table is dependent on the stage1 page table code, -+ * we must always honor the following condition: -+ * -+ * Number of levels in Stage1 >= Number of levels in Stage2. -+ * -+ * So clamp the ipa limit further down to limit the number of levels. -+ * Since we can concatenate upto 16 tables at entry level, we could -+ * go upto 4bits above the maximum VA addressible with the current -+ * number of levels. -+ */ -+ va_max = PGDIR_SHIFT + PAGE_SHIFT - 3; -+ va_max += 4; -+ -+ if (va_max < ipa_max) -+ ipa_max = va_max; -+ -+ /* -+ * If the final limit is lower than the real physical address -+ * limit of the CPUs, report the reason. -+ */ -+ if (ipa_max < pa_max) -+ pr_info("kvm: Limiting the IPA size due to kernel %s Address limit\n", -+ (va_max < pa_max) ? "Virtual" : "Physical"); -+ -+ WARN(ipa_max < KVM_PHYS_SHIFT, -+ "KVM IPA limit (%d bit) is smaller than default size\n", ipa_max); -+ kvm_ipa_limit = ipa_max; -+ kvm_info("IPA Size Limit: %dbits\n", kvm_ipa_limit); -+} -+ -+/* -+ * Configure the VTCR_EL2 for this VM. The VTCR value is common -+ * across all the physical CPUs on the system. We use system wide -+ * sanitised values to fill in different fields, except for Hardware -+ * Management of Access Flags. HA Flag is set unconditionally on -+ * all CPUs, as it is safe to run with or without the feature and -+ * the bit is RES0 on CPUs that don't support it. -+ */ -+int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type) -+{ -+ u64 vtcr = VTCR_EL2_FLAGS; -+ u32 parange, phys_shift; -+ u8 lvls; -+ -+ if (type & ~KVM_VM_TYPE_ARM_IPA_SIZE_MASK) -+ return -EINVAL; -+ -+ phys_shift = KVM_VM_TYPE_ARM_IPA_SIZE(type); -+ if (phys_shift) { -+ if (phys_shift > kvm_ipa_limit || -+ phys_shift < 32) -+ return -EINVAL; -+ } else { -+ phys_shift = KVM_PHYS_SHIFT; -+ } -+ -+ parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 7; -+ if (parange > ID_AA64MMFR0_PARANGE_MAX) -+ parange = ID_AA64MMFR0_PARANGE_MAX; -+ vtcr |= parange << VTCR_EL2_PS_SHIFT; -+ -+ vtcr |= VTCR_EL2_T0SZ(phys_shift); -+ /* -+ * Use a minimum 2 level page table to prevent splitting -+ * host PMD huge pages at stage2. -+ */ -+ lvls = stage2_pgtable_levels(phys_shift); -+ if (lvls < 2) -+ lvls = 2; -+ vtcr |= VTCR_EL2_LVLS_TO_SL0(lvls); -+ -+ /* -+ * Enable the Hardware Access Flag management, unconditionally -+ * on all CPUs. The features is RES0 on CPUs without the support -+ * and must be ignored by the CPUs. -+ */ -+ vtcr |= VTCR_EL2_HA; -+ -+ /* Set the vmid bits */ -+ vtcr |= (kvm_get_vmid_bits() == 16) ? -+ VTCR_EL2_VS_16BIT : -+ VTCR_EL2_VS_8BIT; -+ kvm->arch.vtcr = vtcr; -+ return 0; -+} -diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h -index 8bdbb5f29494..424ee18695ce 100644 ---- a/include/linux/irqchip/arm-gic-v3.h -+++ b/include/linux/irqchip/arm-gic-v3.h -@@ -388,6 +388,9 @@ - #define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48) - #define GITS_BASER_PHYS_52_to_48(phys) \ - (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12) -+#define GITS_BASER_ADDR_48_to_52(baser) \ -+ (((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48) -+ - #define GITS_BASER_SHAREABILITY_SHIFT (10) - #define GITS_BASER_InnerShareable \ - GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) -diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h -index 251be353f950..c6a2f49b2d2e 100644 ---- a/include/uapi/linux/kvm.h -+++ b/include/uapi/linux/kvm.h -@@ -750,6 +750,15 @@ struct kvm_ppc_resize_hpt { - - #define KVM_S390_SIE_PAGE_OFFSET 1 - -+/* -+ * On arm64, machine type can be used to request the physical -+ * address size for the VM. Bits[7-0] are reserved for the guest -+ * PA size shift (i.e, log2(PA_Size)). For backward compatibility, -+ * value 0 implies the default IPA size, 40bits. -+ */ -+#define KVM_VM_TYPE_ARM_IPA_SIZE_MASK 0xffULL -+#define KVM_VM_TYPE_ARM_IPA_SIZE(x) \ -+ ((x) & KVM_VM_TYPE_ARM_IPA_SIZE_MASK) - /* - * ioctls for /dev/kvm fds: - */ -@@ -953,6 +962,12 @@ struct kvm_ppc_resize_hpt { - #define KVM_CAP_NESTED_STATE 157 - #define KVM_CAP_ARM_INJECT_SERROR_ESR 158 - #define KVM_CAP_MSR_PLATFORM_INFO 159 -+#define KVM_CAP_PPC_NESTED_HV 160 -+#define KVM_CAP_HYPERV_SEND_IPI 161 -+#define KVM_CAP_COALESCED_PIO 162 -+#define KVM_CAP_HYPERV_ENLIGHTENED_VMCS 163 -+#define KVM_CAP_EXCEPTION_PAYLOAD 164 -+#define KVM_CAP_ARM_VM_IPA_SIZE 165 - - #ifdef KVM_CAP_IRQ_ROUTING - -diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c -index 8fb31a7cc22c..23774970c9df 100644 ---- a/virt/kvm/arm/arm.c -+++ b/virt/kvm/arm/arm.c -@@ -120,8 +120,9 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) - { - int ret, cpu; - -- if (type) -- return -EINVAL; -+ ret = kvm_arm_setup_stage2(kvm, type); -+ if (ret) -+ return ret; - - kvm->arch.last_vcpu_ran = alloc_percpu(typeof(*kvm->arch.last_vcpu_ran)); - if (!kvm->arch.last_vcpu_ran) -@@ -212,6 +213,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) - case KVM_CAP_READONLY_MEM: - case KVM_CAP_MP_STATE: - case KVM_CAP_IMMEDIATE_EXIT: -+ case KVM_CAP_VCPU_EVENTS: - r = 1; - break; - case KVM_CAP_ARM_SET_DEVICE_ADDR: -@@ -240,7 +242,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) - r = 1; - break; - default: -- r = kvm_arch_dev_ioctl_check_extension(kvm, ext); -+ r = kvm_arch_vm_ioctl_check_extension(kvm, ext); - break; - } - return r; -@@ -496,7 +498,7 @@ static bool need_new_vmid_gen(struct kvm *kvm) - static void update_vttbr(struct kvm *kvm) - { - phys_addr_t pgd_phys; -- u64 vmid; -+ u64 vmid, cnp = kvm_cpu_has_cnp() ? VTTBR_CNP_BIT : 0; - bool new_gen; - - read_lock(&kvm_vmid_lock); -@@ -544,9 +546,9 @@ static void update_vttbr(struct kvm *kvm) - - /* update vttbr to be used with the new vmid */ - pgd_phys = virt_to_phys(kvm->arch.pgd); -- BUG_ON(pgd_phys & ~VTTBR_BADDR_MASK); -+ BUG_ON(pgd_phys & ~kvm_vttbr_baddr_mask(kvm)); - vmid = ((u64)(kvm->arch.vmid) << VTTBR_VMID_SHIFT) & VTTBR_VMID_MASK(kvm_vmid_bits); -- kvm->arch.vttbr = kvm_phys_to_vttbr(pgd_phys) | vmid; -+ kvm->arch.vttbr = kvm_phys_to_vttbr(pgd_phys) | vmid | cnp; - - write_unlock(&kvm_vmid_lock); - } -@@ -1307,16 +1309,10 @@ static void cpu_hyp_reinit(void) - { - cpu_hyp_reset(); - -- if (is_kernel_in_hyp_mode()) { -- /* -- * __cpu_init_stage2() is safe to call even if the PM -- * event was cancelled before the CPU was reset. -- */ -- __cpu_init_stage2(); -+ if (is_kernel_in_hyp_mode()) - kvm_timer_init_vhe(); -- } else { -+ else - cpu_init_hyp_mode(NULL); -- } - - kvm_arm_init_debug(); - -@@ -1412,6 +1408,8 @@ static int init_common_resources(void) - kvm_vmid_bits = kvm_get_vmid_bits(); - kvm_info("%d-bit VMID\n", kvm_vmid_bits); - -+ kvm_set_ipa_limit(); -+ - return 0; - } - -diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c -index 2f405b0be25c..c23a1b323aad 100644 ---- a/virt/kvm/arm/mmu.c -+++ b/virt/kvm/arm/mmu.c -@@ -45,7 +45,6 @@ static phys_addr_t hyp_idmap_vector; - - static unsigned long io_map_base; - --#define S2_PGD_SIZE (PTRS_PER_S2_PGD * sizeof(pgd_t)) - #define hyp_pgd_order get_order(PTRS_PER_PGD * sizeof(pgd_t)) - - #define KVM_S2PTE_FLAG_IS_IOMAP (1UL << 0) -@@ -150,20 +149,20 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) - - static void clear_stage2_pgd_entry(struct kvm *kvm, pgd_t *pgd, phys_addr_t addr) - { -- pud_t *pud_table __maybe_unused = stage2_pud_offset(pgd, 0UL); -- stage2_pgd_clear(pgd); -+ pud_t *pud_table __maybe_unused = stage2_pud_offset(kvm, pgd, 0UL); -+ stage2_pgd_clear(kvm, pgd); - kvm_tlb_flush_vmid_ipa(kvm, addr); -- stage2_pud_free(pud_table); -+ stage2_pud_free(kvm, pud_table); - put_page(virt_to_page(pgd)); - } - - static void clear_stage2_pud_entry(struct kvm *kvm, pud_t *pud, phys_addr_t addr) - { -- pmd_t *pmd_table __maybe_unused = stage2_pmd_offset(pud, 0); -- VM_BUG_ON(stage2_pud_huge(*pud)); -- stage2_pud_clear(pud); -+ pmd_t *pmd_table __maybe_unused = stage2_pmd_offset(kvm, pud, 0); -+ VM_BUG_ON(stage2_pud_huge(kvm, *pud)); -+ stage2_pud_clear(kvm, pud); - kvm_tlb_flush_vmid_ipa(kvm, addr); -- stage2_pmd_free(pmd_table); -+ stage2_pmd_free(kvm, pmd_table); - put_page(virt_to_page(pud)); - } - -@@ -252,7 +251,7 @@ static void unmap_stage2_ptes(struct kvm *kvm, pmd_t *pmd, - } - } while (pte++, addr += PAGE_SIZE, addr != end); - -- if (stage2_pte_table_empty(start_pte)) -+ if (stage2_pte_table_empty(kvm, start_pte)) - clear_stage2_pmd_entry(kvm, pmd, start_addr); - } - -@@ -262,9 +261,9 @@ static void unmap_stage2_pmds(struct kvm *kvm, pud_t *pud, - phys_addr_t next, start_addr = addr; - pmd_t *pmd, *start_pmd; - -- start_pmd = pmd = stage2_pmd_offset(pud, addr); -+ start_pmd = pmd = stage2_pmd_offset(kvm, pud, addr); - do { -- next = stage2_pmd_addr_end(addr, end); -+ next = stage2_pmd_addr_end(kvm, addr, end); - if (!pmd_none(*pmd)) { - if (pmd_thp_or_huge(*pmd)) { - pmd_t old_pmd = *pmd; -@@ -281,7 +280,7 @@ static void unmap_stage2_pmds(struct kvm *kvm, pud_t *pud, - } - } while (pmd++, addr = next, addr != end); - -- if (stage2_pmd_table_empty(start_pmd)) -+ if (stage2_pmd_table_empty(kvm, start_pmd)) - clear_stage2_pud_entry(kvm, pud, start_addr); - } - -@@ -291,14 +290,14 @@ static void unmap_stage2_puds(struct kvm *kvm, pgd_t *pgd, - phys_addr_t next, start_addr = addr; - pud_t *pud, *start_pud; - -- start_pud = pud = stage2_pud_offset(pgd, addr); -+ start_pud = pud = stage2_pud_offset(kvm, pgd, addr); - do { -- next = stage2_pud_addr_end(addr, end); -- if (!stage2_pud_none(*pud)) { -- if (stage2_pud_huge(*pud)) { -+ next = stage2_pud_addr_end(kvm, addr, end); -+ if (!stage2_pud_none(kvm, *pud)) { -+ if (stage2_pud_huge(kvm, *pud)) { - pud_t old_pud = *pud; - -- stage2_pud_clear(pud); -+ stage2_pud_clear(kvm, pud); - kvm_tlb_flush_vmid_ipa(kvm, addr); - kvm_flush_dcache_pud(old_pud); - put_page(virt_to_page(pud)); -@@ -308,7 +307,7 @@ static void unmap_stage2_puds(struct kvm *kvm, pgd_t *pgd, - } - } while (pud++, addr = next, addr != end); - -- if (stage2_pud_table_empty(start_pud)) -+ if (stage2_pud_table_empty(kvm, start_pud)) - clear_stage2_pgd_entry(kvm, pgd, start_addr); - } - -@@ -332,7 +331,7 @@ static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size) - assert_spin_locked(&kvm->mmu_lock); - WARN_ON(size & ~PAGE_MASK); - -- pgd = kvm->arch.pgd + stage2_pgd_index(addr); -+ pgd = kvm->arch.pgd + stage2_pgd_index(kvm, addr); - do { - /* - * Make sure the page table is still active, as another thread -@@ -341,8 +340,8 @@ static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size) - */ - if (!READ_ONCE(kvm->arch.pgd)) - break; -- next = stage2_pgd_addr_end(addr, end); -- if (!stage2_pgd_none(*pgd)) -+ next = stage2_pgd_addr_end(kvm, addr, end); -+ if (!stage2_pgd_none(kvm, *pgd)) - unmap_stage2_puds(kvm, pgd, addr, next); - /* - * If the range is too large, release the kvm->mmu_lock -@@ -371,9 +370,9 @@ static void stage2_flush_pmds(struct kvm *kvm, pud_t *pud, - pmd_t *pmd; - phys_addr_t next; - -- pmd = stage2_pmd_offset(pud, addr); -+ pmd = stage2_pmd_offset(kvm, pud, addr); - do { -- next = stage2_pmd_addr_end(addr, end); -+ next = stage2_pmd_addr_end(kvm, addr, end); - if (!pmd_none(*pmd)) { - if (pmd_thp_or_huge(*pmd)) - kvm_flush_dcache_pmd(*pmd); -@@ -389,11 +388,11 @@ static void stage2_flush_puds(struct kvm *kvm, pgd_t *pgd, - pud_t *pud; - phys_addr_t next; - -- pud = stage2_pud_offset(pgd, addr); -+ pud = stage2_pud_offset(kvm, pgd, addr); - do { -- next = stage2_pud_addr_end(addr, end); -- if (!stage2_pud_none(*pud)) { -- if (stage2_pud_huge(*pud)) -+ next = stage2_pud_addr_end(kvm, addr, end); -+ if (!stage2_pud_none(kvm, *pud)) { -+ if (stage2_pud_huge(kvm, *pud)) - kvm_flush_dcache_pud(*pud); - else - stage2_flush_pmds(kvm, pud, addr, next); -@@ -409,10 +408,11 @@ static void stage2_flush_memslot(struct kvm *kvm, - phys_addr_t next; - pgd_t *pgd; - -- pgd = kvm->arch.pgd + stage2_pgd_index(addr); -+ pgd = kvm->arch.pgd + stage2_pgd_index(kvm, addr); - do { -- next = stage2_pgd_addr_end(addr, end); -- stage2_flush_puds(kvm, pgd, addr, next); -+ next = stage2_pgd_addr_end(kvm, addr, end); -+ if (!stage2_pgd_none(kvm, *pgd)) -+ stage2_flush_puds(kvm, pgd, addr, next); - } while (pgd++, addr = next, addr != end); - } - -@@ -897,7 +897,7 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm) - } - - /* Allocate the HW PGD, making sure that each page gets its own refcount */ -- pgd = alloc_pages_exact(S2_PGD_SIZE, GFP_KERNEL | __GFP_ZERO); -+ pgd = alloc_pages_exact(stage2_pgd_size(kvm), GFP_KERNEL | __GFP_ZERO); - if (!pgd) - return -ENOMEM; - -@@ -986,7 +986,7 @@ void kvm_free_stage2_pgd(struct kvm *kvm) - - spin_lock(&kvm->mmu_lock); - if (kvm->arch.pgd) { -- unmap_stage2_range(kvm, 0, KVM_PHYS_SIZE); -+ unmap_stage2_range(kvm, 0, kvm_phys_size(kvm)); - pgd = READ_ONCE(kvm->arch.pgd); - kvm->arch.pgd = NULL; - } -@@ -994,7 +994,7 @@ void kvm_free_stage2_pgd(struct kvm *kvm) - - /* Free the HW pgd, one page at a time */ - if (pgd) -- free_pages_exact(pgd, S2_PGD_SIZE); -+ free_pages_exact(pgd, stage2_pgd_size(kvm)); - } - - static pud_t *stage2_get_pud(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, -@@ -1003,16 +1003,16 @@ static pud_t *stage2_get_pud(struct kvm *kvm, struct kvm_mmu_memory_cache *cache - pgd_t *pgd; - pud_t *pud; - -- pgd = kvm->arch.pgd + stage2_pgd_index(addr); -- if (WARN_ON(stage2_pgd_none(*pgd))) { -+ pgd = kvm->arch.pgd + stage2_pgd_index(kvm, addr); -+ if (stage2_pgd_none(kvm, *pgd)) { - if (!cache) - return NULL; - pud = mmu_memory_cache_alloc(cache); -- stage2_pgd_populate(pgd, pud); -+ stage2_pgd_populate(kvm, pgd, pud); - get_page(virt_to_page(pgd)); - } - -- return stage2_pud_offset(pgd, addr); -+ return stage2_pud_offset(kvm, pgd, addr); - } - - static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache *cache, -@@ -1025,15 +1025,15 @@ static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache *cache - if (!pud) - return NULL; - -- if (stage2_pud_none(*pud)) { -+ if (stage2_pud_none(kvm, *pud)) { - if (!cache) - return NULL; - pmd = mmu_memory_cache_alloc(cache); -- stage2_pud_populate(pud, pmd); -+ stage2_pud_populate(kvm, pud, pmd); - get_page(virt_to_page(pud)); - } - -- return stage2_pmd_offset(pud, addr); -+ return stage2_pmd_offset(kvm, pud, addr); - } - - static int stage2_set_pmd_huge(struct kvm *kvm, struct kvm_mmu_memory_cache -@@ -1207,8 +1207,9 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, - if (writable) - pte = kvm_s2pte_mkwrite(pte); - -- ret = mmu_topup_memory_cache(&cache, KVM_MMU_CACHE_MIN_PAGES, -- KVM_NR_MEM_OBJS); -+ ret = mmu_topup_memory_cache(&cache, -+ kvm_mmu_cache_min_pages(kvm), -+ KVM_NR_MEM_OBJS); - if (ret) - goto out; - spin_lock(&kvm->mmu_lock); -@@ -1302,19 +1303,21 @@ static void stage2_wp_ptes(pmd_t *pmd, phys_addr_t addr, phys_addr_t end) - - /** - * stage2_wp_pmds - write protect PUD range -+ * kvm: kvm instance for the VM - * @pud: pointer to pud entry - * @addr: range start address - * @end: range end address - */ --static void stage2_wp_pmds(pud_t *pud, phys_addr_t addr, phys_addr_t end) -+static void stage2_wp_pmds(struct kvm *kvm, pud_t *pud, -+ phys_addr_t addr, phys_addr_t end) - { - pmd_t *pmd; - phys_addr_t next; - -- pmd = stage2_pmd_offset(pud, addr); -+ pmd = stage2_pmd_offset(kvm, pud, addr); - - do { -- next = stage2_pmd_addr_end(addr, end); -+ next = stage2_pmd_addr_end(kvm, addr, end); - if (!pmd_none(*pmd)) { - if (pmd_thp_or_huge(*pmd)) { - if (!kvm_s2pmd_readonly(pmd)) -@@ -1334,18 +1337,19 @@ static void stage2_wp_pmds(pud_t *pud, phys_addr_t addr, phys_addr_t end) - * - * Process PUD entries, for a huge PUD we cause a panic. - */ --static void stage2_wp_puds(pgd_t *pgd, phys_addr_t addr, phys_addr_t end) -+static void stage2_wp_puds(struct kvm *kvm, pgd_t *pgd, -+ phys_addr_t addr, phys_addr_t end) - { - pud_t *pud; - phys_addr_t next; - -- pud = stage2_pud_offset(pgd, addr); -+ pud = stage2_pud_offset(kvm, pgd, addr); - do { -- next = stage2_pud_addr_end(addr, end); -- if (!stage2_pud_none(*pud)) { -+ next = stage2_pud_addr_end(kvm, addr, end); -+ if (!stage2_pud_none(kvm, *pud)) { - /* TODO:PUD not supported, revisit later if supported */ -- BUG_ON(stage2_pud_huge(*pud)); -- stage2_wp_pmds(pud, addr, next); -+ BUG_ON(stage2_pud_huge(kvm, *pud)); -+ stage2_wp_pmds(kvm, pud, addr, next); - } - } while (pud++, addr = next, addr != end); - } -@@ -1361,7 +1365,7 @@ static void stage2_wp_range(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) - pgd_t *pgd; - phys_addr_t next; - -- pgd = kvm->arch.pgd + stage2_pgd_index(addr); -+ pgd = kvm->arch.pgd + stage2_pgd_index(kvm, addr); - do { - /* - * Release kvm_mmu_lock periodically if the memory region is -@@ -1375,9 +1379,9 @@ static void stage2_wp_range(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) - cond_resched_lock(&kvm->mmu_lock); - if (!READ_ONCE(kvm->arch.pgd)) - break; -- next = stage2_pgd_addr_end(addr, end); -- if (stage2_pgd_present(*pgd)) -- stage2_wp_puds(pgd, addr, next); -+ next = stage2_pgd_addr_end(kvm, addr, end); -+ if (stage2_pgd_present(kvm, *pgd)) -+ stage2_wp_puds(kvm, pgd, addr, next); - } while (pgd++, addr = next, addr != end); - } - -@@ -1526,7 +1530,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, - up_read(¤t->mm->mmap_sem); - - /* We need minimum second+third level pages */ -- ret = mmu_topup_memory_cache(memcache, KVM_MMU_CACHE_MIN_PAGES, -+ ret = mmu_topup_memory_cache(memcache, kvm_mmu_cache_min_pages(kvm), - KVM_NR_MEM_OBJS); - if (ret) - return ret; -@@ -1769,7 +1773,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run) - } - - /* Userspace should not be able to register out-of-bounds IPAs */ -- VM_BUG_ON(fault_ipa >= KVM_PHYS_SIZE); -+ VM_BUG_ON(fault_ipa >= kvm_phys_size(vcpu->kvm)); - - if (fault_status == FSC_ACCESS) { - handle_access_fault(vcpu, fault_ipa); -@@ -2068,7 +2072,7 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, - * space addressable by the KVM guest IPA space. - */ - if (memslot->base_gfn + memslot->npages >= -- (KVM_PHYS_SIZE >> PAGE_SHIFT)) -+ (kvm_phys_size(kvm) >> PAGE_SHIFT)) - return -EFAULT; - - down_read(¤t->mm->mmap_sem); -diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c -index 12502251727e..eb2a390a6c86 100644 ---- a/virt/kvm/arm/vgic/vgic-its.c -+++ b/virt/kvm/arm/vgic/vgic-its.c -@@ -241,13 +241,6 @@ static struct its_ite *find_ite(struct vgic_its *its, u32 device_id, - list_for_each_entry(dev, &(its)->device_list, dev_list) \ - list_for_each_entry(ite, &(dev)->itt_head, ite_list) - --/* -- * We only implement 48 bits of PA at the moment, although the ITS -- * supports more. Let's be restrictive here. -- */ --#define BASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 16)) --#define CBASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 12)) -- - #define GIC_LPI_OFFSET 8192 - - #define VITS_TYPER_IDBITS 16 -@@ -759,6 +752,7 @@ static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id, - { - int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K; - u64 indirect_ptr, type = GITS_BASER_TYPE(baser); -+ phys_addr_t base = GITS_BASER_ADDR_48_to_52(baser); - int esz = GITS_BASER_ENTRY_SIZE(baser); - int index; - gfn_t gfn; -@@ -783,7 +777,7 @@ static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id, - if (id >= (l1_tbl_size / esz)) - return false; - -- addr = BASER_ADDRESS(baser) + id * esz; -+ addr = base + id * esz; - gfn = addr >> PAGE_SHIFT; - - if (eaddr) -@@ -798,7 +792,7 @@ static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id, - - /* Each 1st level entry is represented by a 64-bit value. */ - if (kvm_read_guest_lock(its->dev->kvm, -- BASER_ADDRESS(baser) + index * sizeof(indirect_ptr), -+ base + index * sizeof(indirect_ptr), - &indirect_ptr, sizeof(indirect_ptr))) - return false; - -@@ -808,11 +802,7 @@ static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id, - if (!(indirect_ptr & BIT_ULL(63))) - return false; - -- /* -- * Mask the guest physical address and calculate the frame number. -- * Any address beyond our supported 48 bits of PA will be caught -- * by the actual check in the final step. -- */ -+ /* Mask the guest physical address and calculate the frame number. */ - indirect_ptr &= GENMASK_ULL(51, 16); - - /* Find the address of the actual entry */ -@@ -1304,9 +1294,6 @@ static u64 vgic_sanitise_its_baser(u64 reg) - GITS_BASER_OUTER_CACHEABILITY_SHIFT, - vgic_sanitise_outer_cacheability); - -- /* Bits 15:12 contain bits 51:48 of the PA, which we don't support. */ -- reg &= ~GENMASK_ULL(15, 12); -- - /* We support only one (ITS) page size: 64K */ - reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K; - -@@ -1325,11 +1312,8 @@ static u64 vgic_sanitise_its_cbaser(u64 reg) - GITS_CBASER_OUTER_CACHEABILITY_SHIFT, - vgic_sanitise_outer_cacheability); - -- /* -- * Sanitise the physical address to be 64k aligned. -- * Also limit the physical addresses to 48 bits. -- */ -- reg &= ~(GENMASK_ULL(51, 48) | GENMASK_ULL(15, 12)); -+ /* Sanitise the physical address to be 64k aligned. */ -+ reg &= ~GENMASK_ULL(15, 12); - - return reg; - } -@@ -1375,7 +1359,7 @@ static void vgic_its_process_commands(struct kvm *kvm, struct vgic_its *its) - if (!its->enabled) - return; - -- cbaser = CBASER_ADDRESS(its->cbaser); -+ cbaser = GITS_CBASER_ADDRESS(its->cbaser); - - while (its->cwriter != its->creadr) { - int ret = kvm_read_guest_lock(kvm, cbaser + its->creadr, -@@ -2233,7 +2217,7 @@ static int vgic_its_restore_device_tables(struct vgic_its *its) - if (!(baser & GITS_BASER_VALID)) - return 0; - -- l1_gpa = BASER_ADDRESS(baser); -+ l1_gpa = GITS_BASER_ADDR_48_to_52(baser); - - if (baser & GITS_BASER_INDIRECT) { - l1_esz = GITS_LVL1_ENTRY_SIZE; -@@ -2305,7 +2289,7 @@ static int vgic_its_save_collection_table(struct vgic_its *its) - { - const struct vgic_its_abi *abi = vgic_its_get_abi(its); - u64 baser = its->baser_coll_table; -- gpa_t gpa = BASER_ADDRESS(baser); -+ gpa_t gpa = GITS_BASER_ADDR_48_to_52(baser); - struct its_collection *collection; - u64 val; - size_t max_size, filled = 0; -@@ -2354,7 +2338,7 @@ static int vgic_its_restore_collection_table(struct vgic_its *its) - if (!(baser & GITS_BASER_VALID)) - return 0; - -- gpa = BASER_ADDRESS(baser); -+ gpa = GITS_BASER_ADDR_48_to_52(baser); - - max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K; - -diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c -index a2a175b08b17..b3d1f0985117 100644 ---- a/virt/kvm/arm/vgic/vgic-mmio-v3.c -+++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c -@@ -364,7 +364,6 @@ static u64 vgic_sanitise_pendbaser(u64 reg) - vgic_sanitise_outer_cacheability); - - reg &= ~PENDBASER_RES0_MASK; -- reg &= ~GENMASK_ULL(51, 48); - - return reg; - } -@@ -382,7 +381,6 @@ static u64 vgic_sanitise_propbaser(u64 reg) - vgic_sanitise_outer_cacheability); - - reg &= ~PROPBASER_RES0_MASK; -- reg &= ~GENMASK_ULL(51, 48); - return reg; - } - --- -2.17.1 -