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Dragonballl: introduce MTRR regs support

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MTRR, or Memory-Type Range Registers are a group of x86 MSRs providing a way to control access
 and cache ability of physical memory regions.
During our test in runtime-rs + Dragonball, we found out that this register support is a must
for passthrough GPU running CUDA application, GPU needs that information to properly use GPU memory.

fixes: #9310
Signed-off-by: Chao Wu <chaowu@linux.alibaba.com>
This commit is contained in:
Chao Wu 2024-03-17 22:04:09 +08:00
parent daab76de36
commit 5a4b858ece
1 changed files with 10 additions and 0 deletions
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10
src/dragonball/src/dbs_arch/src/x86_64/regs.rs
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@ -31,6 +31,11 @@ pub const X86_CR0_PG: u64 = 0x8000_0000;
/// Physical Address Extension bit in CR4. /// Physical Address Extension bit in CR4.
pub const X86_CR4_PAE: u64 = 0x20; pub const X86_CR4_PAE: u64 = 0x20;
// MTRR constants.
const MTRR_ENABLED: u64 = 0x0800; // IA32_MTRR_DEF_TYPE MSR: E (MTRRs enabled) flag, bit 11
const MTRR_FIXED_RANGE_ENABLE: u64 = 0x0400;
const MTRR_MEM_TYPE_WB: u64 = 0x6;
/// Errors thrown while setting up x86_64 registers. /// Errors thrown while setting up x86_64 registers.
#[derive(Debug)] #[derive(Debug)]
pub enum Error { pub enum Error {
@ -215,6 +220,11 @@ fn create_msr_entries() -> Vec<kvm_msr_entry> {
data: 0x0, data: 0x0,
..Default::default() ..Default::default()
}); });
entries.push(kvm_msr_entry {
index: msr::MSR_MTRRdefType,
data: MTRR_ENABLED | MTRR_FIXED_RANGE_ENABLE | MTRR_MEM_TYPE_WB,
..Default::default()
});
// x86_64 specific msrs, we only run on x86_64 not x86. // x86_64 specific msrs, we only run on x86_64 not x86.
entries.push(kvm_msr_entry { entries.push(kvm_msr_entry {
index: msr::MSR_STAR, index: msr::MSR_STAR,