sel4-sys: add arch_generic support

Adds an architecture-independent api for sel4-sys interfaces similar
to what libsel4 does. For example, instead of seL4_RISCV_Page_Map use
seL4_Page_Map. This is mostly aliases for common types & system calls but
also features like the Grant right implying NoExecute for seL4_Page_Map.

While here fix crate paths to sel4-sys; everything external to
kata-os-common is intended to use kata-os-common::sel4-sys.

Change-Id: I6faa07d41ffd2fbb4182bf2fa7c05a768e4368f3
GitOrigin-RevId: f51e5186b61eab541e9fb4d2d4175adcc3ca8cee
This commit is contained in:
Sam Leffler 2022-05-20 18:22:12 +00:00
parent 3f19e4b805
commit 3bd8389a4c
28 changed files with 194 additions and 182 deletions

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@ -13,13 +13,12 @@ use kata_os_common::sel4_sys;
use sel4_sys::seL4_CapRights;
use sel4_sys::seL4_CPtr;
use sel4_sys::seL4_Default_VMAttributes;
use sel4_sys::seL4_PageBits;
use sel4_sys::seL4_Page_Map;
use sel4_sys::seL4_Page_Unmap;
use sel4_sys::seL4_WordBits;
use sel4_sys::seL4_RISCV_Page_Map as seL4_Page_Map;
use sel4_sys::seL4_RISCV_Page_Unmap as seL4_Page_Unmap;
use sel4_sys::seL4_RISCV_VMAttributes::Default_VMAttributes as seL4_Default_VMAttributes;
use kata_io as io;
#[derive(Debug)]

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@ -11,13 +11,11 @@ use log::{error, trace};
use sel4_sys::seL4_CapRights;
use sel4_sys::seL4_CPtr;
use sel4_sys::seL4_Default_VMAttributes;
use sel4_sys::seL4_Error;
use sel4_sys::seL4_PageBits;
// TODO(sleffler): belongs in sel4_sys
use sel4_sys::seL4_RISCV_Page_Map as seL4_Page_Map;
use sel4_sys::seL4_RISCV_Page_Unmap as seL4_Page_Unmap;
use sel4_sys::seL4_RISCV_VMAttributes::Default_VMAttributes as seL4_Default_VMAttributes;
use sel4_sys::seL4_Page_Map;
use sel4_sys::seL4_Page_Unmap;
use kata_io as io;
use io::Read;

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@ -27,7 +27,6 @@ kata-memory-interface = { path = "../../MemoryManager/kata-memory-interface" }
kata-os-common = { path = "../../kata-os-common" }
kata-security-interface = { path = "../../SecurityCoordinator/kata-security-interface" }
log = "0.4"
sel4-sys = { path = "../../kata-os-common/src/sel4-sys" }
smallstr = "0.2"
spin = "0.9"
static_assertions = "1.1"

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@ -6,54 +6,22 @@
use static_assertions::assert_cfg;
assert_cfg!(any(target_arch = "riscv32", target_arch = "riscv64"));
use sel4_sys::seL4_CapRights;
use sel4_sys::seL4_CPtr;
use super::sel4_sys;
use sel4_sys::seL4_PageBits;
use sel4_sys::seL4_PageDirIndexBits;
use sel4_sys::seL4_PageTableIndexBits;
use sel4_sys::seL4_Result;
use sel4_sys::seL4_RISCV_Page_Map;
use sel4_sys::seL4_RISCV_VMAttributes;
use sel4_sys::seL4_Word;
pub const PAGE_SIZE: usize = 4096; // Base/small page size
pub const STACK_ALIGNMENT_BYTES: usize = 16;
pub const REG_ARGS: seL4_Word = 4; // Number of regs for passing thread args
// Architecture-independent aliases to enable arch-independent rootserver code
// TODO(sleffler): maybe move to sel4_sys?
pub use sel4_sys::seL4_RISCV_4K_Page as seL4_SmallPageObject;
pub use sel4_sys::seL4_RISCV_PageTableObject as seL4_PageTableObject;
pub use sel4_sys::seL4_PageTableIndexBits as seL4_PageDirIndexBits;
pub use sel4_sys::seL4_RISCV_ASIDControl_MakePool as seL4_ASIDControl_MakePool;
pub use sel4_sys::seL4_RISCV_ASIDPool_Assign as seL4_ASIDPool_Assign;
pub use sel4_sys::seL4_RISCV_PageTable_Map as seL4_PageTable_Map;
pub use sel4_sys::seL4_RISCV_Page_GetAddress as seL4_Page_GetAddress;
pub use sel4_sys::seL4_RISCV_Page_Unmap as seL4_Page_Unmap;
pub use sel4_sys::seL4_RISCV_VMAttributes as seL4_VMAttributes;
pub use sel4_sys::seL4_RISCV_VMAttributes::Default_VMAttributes as seL4_Default_VMAttributes;
pub unsafe fn seL4_Page_Map(
sel4_page: seL4_CPtr,
sel4_pd: seL4_CPtr,
vaddr: seL4_Word,
rights: seL4_CapRights,
vm_attribs: seL4_VMAttributes,
) -> seL4_Result {
if rights.get_capAllowGrant() != 0 {
// NB: executable
seL4_RISCV_Page_Map(sel4_page, sel4_pd, vaddr, rights, vm_attribs)
} else {
seL4_RISCV_Page_Map(sel4_page, sel4_pd, vaddr, rights,
seL4_RISCV_VMAttributes::ExecuteNever)
}
}
fn MASK(pow2_bits: usize) -> usize { (1 << pow2_bits) - 1 }
// NB: used to setup copy_addr_pt
pub fn PD_SLOT(vaddr: usize) -> usize {
(vaddr >> (seL4_PageTableIndexBits + seL4_PageBits)) & MASK(seL4_PageDirIndexBits)
}
// NB: used for tcb_args::maybe_spill_tcb_args
// NB: used by tcb_args::maybe_spill_tcb_args
pub fn PT_SLOT(vaddr: usize) -> usize { (vaddr >> seL4_PageBits) & MASK(seL4_PageTableIndexBits) }

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@ -6,15 +6,19 @@ use static_assertions::assert_cfg;
assert_cfg!(target_arch = "riscv32");
use kata_memory_interface::ObjDesc;
use super::sel4_sys;
mod riscv;
pub use riscv::*;
use sel4_sys::seL4_CapRights;
use sel4_sys::seL4_PageTable_Map;
use sel4_sys::seL4_Page_Map;
use sel4_sys::seL4_Result;
use sel4_sys::seL4_RISCV_4K_Page;
use sel4_sys::seL4_RISCV_PageTableObject;
use sel4_sys::seL4_UserContext;
use sel4_sys::seL4_VMAttributes;
use sel4_sys::seL4_Word;
pub fn get_user_context(pc: seL4_Word, sp: seL4_Word, argv: &[seL4_Word])
@ -64,7 +68,7 @@ pub fn map_page(
vm_attribs: seL4_VMAttributes,
) -> seL4_Result {
assert_eq!(frame.type_, seL4_RISCV_4K_Page);
// XXX cannot distinguish between PD & PT
// NB: cannot distinguish between PD & PT
assert_eq!(pd.type_, seL4_RISCV_PageTableObject);
unsafe {
seL4_Page_Map(frame.cptr, pd.cptr, vaddr, rights, vm_attribs)

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@ -1,5 +1,7 @@
// MCS Kernel Support.
use super::sel4_sys;
use sel4_sys::seL4_CNode;
use sel4_sys::seL4_CPtr;
use sel4_sys::seL4_Result;

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@ -1,5 +1,7 @@
// No MCS Kernel Support.
use super::sel4_sys;
use sel4_sys::seL4_CNode;
use sel4_sys::seL4_CPtr;
use sel4_sys::seL4_Error;

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@ -1,6 +1,8 @@
// No SMP support.
// TODO(sleffler): maybe merge into arch code
use super::sel4_sys;
use sel4_sys::seL4_Result;
use sel4_sys::seL4_Word;

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@ -3,6 +3,7 @@
use crate::arch::REG_ARGS;
use crate::sel4bundle::seL4Bundle;
use super::sel4_sys;
use sel4_sys::seL4_Error;
use sel4_sys::seL4_Word;

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@ -1,6 +1,8 @@
// SMP support.
// TODO(sleffler): maybe merge into arch code
use super::sel4_sys;
use sel4_sys::seL4_Result;
use sel4_sys::seL4_TCB_SetAffinity;
use sel4_sys::seL4_Word;

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@ -7,6 +7,7 @@ use core::ptr;
use crate::sel4bundle::arch;
use crate::sel4bundle::CopyRegion;
use crate::sel4bundle::seL4BundleImpl;
use super::sel4_sys;
use arch::PAGE_SIZE;
use arch::REG_ARGS;

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@ -17,6 +17,7 @@ use kata_memory_interface::kata_object_free_in_cnode;
use kata_memory_interface::ObjDesc;
use kata_memory_interface::ObjDescBundle;
use kata_os_common::cspace_slot::CSpaceSlot;
use kata_os_common::sel4_sys;
use kata_proc_interface::Bundle;
use kata_proc_interface::BundleImage;
use kata_proc_interface::BundleImplInterface;
@ -26,16 +27,22 @@ use log::{debug, error, info, trace};
use kata_io as io;
use io::Read;
use sel4_sys::seL4_ASIDPool_Assign;
use sel4_sys::seL4_CapRights;
use sel4_sys::seL4_CNode_Move;
use sel4_sys::seL4_CPtr;
use sel4_sys::seL4_Default_VMAttributes;
use sel4_sys::seL4_DomainSet_Set;
use sel4_sys::seL4_EndpointObject;
use sel4_sys::seL4_Error;
use sel4_sys::seL4_MinSchedContextBits;
use sel4_sys::seL4_Page_Map;
use sel4_sys::seL4_PageTableObject;
use sel4_sys::seL4_Page_Unmap;
use sel4_sys::seL4_ReplyObject;
use sel4_sys::seL4_Result;
use sel4_sys::seL4_SchedContextObject;
use sel4_sys::seL4_SmallPageObject;
use sel4_sys::seL4_TCBObject;
use sel4_sys::seL4_TCB_Resume;
use sel4_sys::seL4_TCB_Suspend;
@ -71,12 +78,6 @@ use SELF_TCB_PROCESS_MANAGER_PROC_CTRL_0000 as SELF_TCB;
mod arch;
use arch::PAGE_SIZE;
use arch::seL4_ASIDPool_Assign;
use arch::seL4_Default_VMAttributes;
use arch::seL4_Page_Map;
use arch::seL4_Page_Unmap;
use arch::seL4_PageTableObject;
use arch::seL4_SmallPageObject;
// MCS feature support
#[cfg_attr(feature = "CONFIG_KERNEL_MCS", path = "feature/mcs.rs")]
@ -411,7 +412,7 @@ impl seL4BundleImpl {
// vaddr of the next frame to be mapped. Assumes the image fits into
// a single PT level and that the PT has been setup.
fn load_application(&self) -> Result<usize, seL4_Error> {
let vm_attribs = arch::seL4_Default_VMAttributes;
let vm_attribs = seL4_Default_VMAttributes;
// NB: assumes pd and pt are setup (not sure we can check)
let pd = &self.dynamic_objs.objs[PD_SLOT];
@ -497,7 +498,7 @@ impl seL4BundleImpl {
// NB: grant =>'s X on ARM+RISCV
/*grant_reply=*/ 0, /*grant=*/ 0, /*read=*/ 1, /*write=*/ 1,
);
let vm_attribs = arch::seL4_Default_VMAttributes;
let vm_attribs = seL4_Default_VMAttributes;
let pd = &self.dynamic_objs.objs[PD_SLOT];
let pt = &self.dynamic_objs.objs[PT_SLOT];

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@ -40,6 +40,6 @@ capdl = { path = "../capdl" }
cpio = { git = "https://github.com/rcore-os/cpio" }
cstr_core = "0.2.3"
log = "0.4"
sel4-sys = { path = "../sel4-sys" }
sel4-sys = { path = "../sel4-sys", features = ["arch_generic"] }
smallvec = "1.2"
static_assertions = "1.1"

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@ -37,16 +37,6 @@ pub const CDL_PT_LEVEL_1_IndexBits: usize = seL4_PUDIndexBits;
pub const CDL_PT_LEVEL_2_IndexBits: usize = seL4_PageDirIndexBits;
pub const CDL_PT_LEVEL_3_IndexBits: usize = seL4_PageTableIndexBits;
// Architecture-independent aliases to enable arch-independent rootserver code
pub use sel4_sys::seL4_ARM_ASIDControl_MakePool as seL4_ASIDControl_MakePool;
pub use sel4_sys::seL4_ARM_ASIDPool_Assign as seL4_ASIDPool_Assign;
pub use sel4_sys::seL4_ARM_PageTable_Map as seL4_PageTable_Map;
pub use sel4_sys::seL4_ARM_Page_GetAddress as seL4_Page_GetAddress;
pub use sel4_sys::seL4_ARM_Page_Map as seL4_Page_Map;
pub use sel4_sys::seL4_ARM_Page_Unmap as seL4_Page_Unmap;
pub use sel4_sys::seL4_ARM_VMAttributes as seL4_VMAttributes;
pub use sel4_sys::seL4_ARM_VMAttributes::Default_VMAttributes as seL4_Default_VMAttributes;
fn MASK(pow2_bits: usize) -> usize { (1 << pow2_bits) - 1 }
pub fn PD_SLOT(vaddr: usize) -> usize {

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@ -36,16 +36,7 @@ pub const REG_ARGS: seL4_Word = 4; // Number of regs for passing thread args
pub const CDL_PT_LEVEL_3_IndexBits: usize = seL4_PageTableIndexBits;
// Architecture-independent aliases to enable arch-independent rootserver code
pub use sel4_sys::seL4_ARM_ASIDControl_MakePool as seL4_ASIDControl_MakePool;
pub use sel4_sys::seL4_ARM_ASIDPool_Assign as seL4_ASIDPool_Assign;
pub use sel4_sys::seL4_ARM_PageTable_Map as seL4_PageTable_Map;
pub use sel4_sys::seL4_ARM_Page_GetAddress as seL4_Page_GetAddress;
// NB: seL4_Page_Map has a wrapper (see below)
pub use sel4_sys::seL4_ARM_Page_Unmap as seL4_Page_Unmap;
pub use sel4_sys::seL4_ARM_VMAttributes as seL4_VMAttributes;
pub use sel4_sys::seL4_ARM_VMAttributes::Default_VMAttributes as seL4_Default_VMAttributes;
// NB: this overrides what sel4_sys provides
pub fn seL4_Page_Map(
sel4_page: seL4_ARM_Page,
sel4_pd: seL4_ARM_PageTable,

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@ -9,53 +9,22 @@ assert_cfg!(any(target_arch = "riscv32", target_arch = "riscv64"));
use capdl::CDL_ObjectType::*;
use capdl::*;
use sel4_sys::seL4_CapRights;
use sel4_sys::seL4_CPtr;
use sel4_sys::seL4_PageBits;
use sel4_sys::seL4_PageDirIndexBits;
use sel4_sys::seL4_PageTableIndexBits;
use sel4_sys::seL4_Result;
use sel4_sys::seL4_RISCV_Page_Map;
use sel4_sys::seL4_RISCV_VMAttributes;
use sel4_sys::seL4_Word;
pub const PAGE_SIZE: usize = 4096; // Base page size
pub const STACK_ALIGNMENT_BYTES: usize = 16;
pub const REG_ARGS: seL4_Word = 4; // Number of regs for passing thread args
// Architecture-independent aliases to enable arch-independent rootserver code
// TODO(sleffler): maybe move to sel4_sys?
pub use sel4_sys::seL4_PageTableIndexBits as seL4_PageDirIndexBits;
pub use sel4_sys::seL4_RISCV_ASIDControl_MakePool as seL4_ASIDControl_MakePool;
pub use sel4_sys::seL4_RISCV_ASIDPool_Assign as seL4_ASIDPool_Assign;
pub use sel4_sys::seL4_RISCV_PageTable_Map as seL4_PageTable_Map;
pub use sel4_sys::seL4_RISCV_Page_GetAddress as seL4_Page_GetAddress;
pub use sel4_sys::seL4_RISCV_Page_Unmap as seL4_Page_Unmap;
pub use sel4_sys::seL4_RISCV_VMAttributes as seL4_VMAttributes;
pub use sel4_sys::seL4_RISCV_VMAttributes::Default_VMAttributes as seL4_Default_VMAttributes;
pub unsafe fn seL4_Page_Map(
sel4_page: seL4_CPtr,
sel4_pd: seL4_CPtr,
vaddr: seL4_Word,
rights: seL4_CapRights,
vm_attribs: seL4_VMAttributes,
) -> seL4_Result {
if rights.get_capAllowGrant() != 0 {
// NB: executable
seL4_RISCV_Page_Map(sel4_page, sel4_pd, vaddr, rights, vm_attribs)
} else {
seL4_RISCV_Page_Map(sel4_page, sel4_pd, vaddr, rights,
seL4_RISCV_VMAttributes::ExecuteNever)
}
}
fn MASK(pow2_bits: usize) -> usize { (1 << pow2_bits) - 1 }
// NB: used to setup copy_addr_pt
pub fn PD_SLOT(vaddr: usize) -> usize {
(vaddr >> (seL4_PageTableIndexBits + seL4_PageBits)) & MASK(seL4_PageDirIndexBits)
}
// NB: used for tcb_args::maybe_spill_tcb_args
// NB: used by tcb_args::maybe_spill_tcb_args
pub fn PT_SLOT(vaddr: usize) -> usize { (vaddr >> seL4_PageBits) & MASK(seL4_PageTableIndexBits) }
// Identifies IRQ objects that potentially need special processing.

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@ -9,6 +9,7 @@ use capdl::*;
use log::{debug, info, trace};
use smallvec::SmallVec;
use sel4_sys::seL4_ASIDControl_MakePool;
use sel4_sys::seL4_BootInfo;
use sel4_sys::seL4_CapASIDControl;
use sel4_sys::seL4_CapInitThreadCNode;
@ -21,6 +22,7 @@ use sel4_sys::seL4_Error;
use sel4_sys::seL4_ObjectType::*;
use sel4_sys::seL4_ObjectType;
use sel4_sys::seL4_PageBits;
use sel4_sys::seL4_Page_GetAddress;
use sel4_sys::seL4_Result;
use sel4_sys::seL4_UntypedDesc;
use sel4_sys::seL4_Untyped_Retype;
@ -29,8 +31,6 @@ use sel4_sys::seL4_WordBits;
use crate::arch::kobject_get_type;
use crate::arch::requires_creation;
use crate::arch::seL4_ASIDControl_MakePool;
use crate::arch::seL4_Page_GetAddress;
use static_assertions::assert_cfg;
assert_cfg!(not(feature = "CONFIG_CAPDL_LOADER_STATIC_ALLOC"));

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@ -2,9 +2,6 @@
// The first REG_ARGS arguments are passed to threads using registers;
// any more arguments are written to the stack.
use crate::arch::seL4_Default_VMAttributes;
use crate::arch::seL4_Page_Map;
use crate::arch::seL4_Page_Unmap;
use crate::arch::PAGE_SIZE;
use crate::arch::PT_SLOT;
use crate::arch::REG_ARGS;
@ -16,10 +13,13 @@ use capdl::*;
use core::mem::size_of;
use core::ptr;
use sel4_sys::seL4_CPtr;
use sel4_sys::seL4_CapInitThreadVSpace;
use sel4_sys::seL4_CapRights;
use sel4_sys::seL4_CPtr;
use sel4_sys::seL4_Default_VMAttributes;
use sel4_sys::seL4_Error;
use sel4_sys::seL4_Page_Map;
use sel4_sys::seL4_Page_Unmap;
use sel4_sys::seL4_Word;
use static_assertions::assert_cfg;

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@ -20,39 +20,10 @@ use core::ptr;
use cpio::CpioNewcReader;
use cstr_core::CStr;
use log::{debug, error, trace};
use sel4_sys::*;
use smallvec::SmallVec;
use static_assertions::*;
use sel4_sys::seL4_ASIDPoolBits;
use sel4_sys::seL4_BootInfo;
use sel4_sys::seL4_BootInfoHeader;
use sel4_sys::SEL4_BOOTINFO_HEADER_NUM;
use sel4_sys::seL4_CapASIDControl;
use sel4_sys::seL4_CapDomain;
use sel4_sys::seL4_CapInitThreadASIDPool;
use sel4_sys::seL4_CapInitThreadCNode;
use sel4_sys::seL4_CapInitThreadVSpace;
use sel4_sys::seL4_CapIRQControl;
use sel4_sys::seL4_CapRights;
use sel4_sys::seL4_CNode_Copy;
use sel4_sys::seL4_CNode_Mint;
use sel4_sys::seL4_CNode_Move;
use sel4_sys::seL4_CNode_Mutate;
use sel4_sys::seL4_CPtr;
use sel4_sys::seL4_DomainSet_Set;
use sel4_sys::seL4_Error::*;
use sel4_sys::seL4_Error;
use sel4_sys::seL4_IRQHandler_SetNotification;
use sel4_sys::seL4_ObjectType::*;
use sel4_sys::seL4_ObjectType;
use sel4_sys::seL4_Result;
use sel4_sys::seL4_TCB_Resume;
use sel4_sys::seL4_TCB_WriteRegisters;
use sel4_sys::seL4_Untyped_Retype;
use sel4_sys::seL4_UserContext;
use sel4_sys::seL4_Word;
use sel4_sys::seL4_WordBits;
// Setup arch- & feature-specific support. Note these must be named
// explicitly below; e.g. loader_alloc::check_untypeds.
@ -70,15 +41,6 @@ mod arch;
use arch::is_irq;
use arch::PAGE_SIZE; // Base page size, typically 4KB
// XXX should come from sel4_sys
use arch::seL4_ASIDPool_Assign;
use arch::seL4_Default_VMAttributes;
use arch::seL4_PageTable_Map;
use arch::seL4_Page_GetAddress;
use arch::seL4_Page_Map;
use arch::seL4_Page_Unmap;
use arch::seL4_VMAttributes;
// Allocation-specific support
#[cfg_attr(
feature = "CONFIG_CAPDL_LOADER_STATIC_ALLOC",
@ -876,7 +838,6 @@ impl<'a> KataOsModel<'a> {
#[cfg(feature = "CONFIG_DEBUG_BUILD")]
// Name the thread after its TCB name if possible.
if let Ok(cstr) = cstr_core::CString::new(cdl_tcb.name()) {
use sel4_sys::seL4_DebugNameThread;
unsafe { seL4_DebugNameThread(sel4_tcb, cstr.to_bytes_with_nul()) };
}
Ok(())

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@ -40,7 +40,8 @@ SEL4_OUT_DIR = "${ROOTDIR}out/kata/kernel"
# Other syscalls api's are generated only when the associated config
# knobs are set but do not affect the syscall ABI (e.g. CONFIG_PRINTING).
[features]
default = []
default = ["arch_generic"]
arch_generic = []
CONFIG_KERNEL_MCS = []
CONFIG_PRINTING = []
CONFIG_DEBUG_BUILD = []

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@ -57,11 +57,14 @@ pub const seL4_Frame_Args: usize = 4;
pub const seL4_Frame_MRs: usize = 7;
pub const seL4_Frame_HasNPC: usize = 0;
pub type seL4_ARM_Page = seL4_CPtr;
pub type seL4_ARM_PageTable = seL4_CPtr;
pub type seL4_ARM_PageDirectory = seL4_CPtr;
pub type seL4_ARM_ASIDControl = seL4_CPtr;
pub type seL4_ARM_ASIDPool = seL4_CPtr;
pub type seL4_ARM_PageDirectory = seL4_CPtr;
pub type seL4_ARM_Page = seL4_CPtr;
pub type seL4_ARM_PageTable = seL4_CPtr;
#[cfg(feature = "arch_generic")]
include!("arm_generic.rs");
error_types!(u32);
@ -92,11 +95,18 @@ pub struct seL4_UserContext {
#[repr(u32)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum seL4_ARM_VMAttributes {
Default = 0,
PageCacheable = 1,
ParityEnabled = 2,
ExecuteNever = 4,
}
pub const Default_VMAttributes: usize = 0;
impl From<u32> for seL4_ARM_VMAttributes {
fn from(val: u32) -> seL4_RISCV_VMAttributes {
unsafe { ::core::mem::transmute(val & 7) }
}
}
pub const seL4_ARM_Default_VMAttributes: seL4_ARM_VMAttributes =
seL4_ARM_VMAttributes::Default;
#[repr(C)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]

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@ -31,13 +31,16 @@ pub const seL4_Frame_Args: usize = 4;
pub const seL4_Frame_MRs: usize = 7;
pub const seL4_Frame_HasNPC: usize = 0;
pub type seL4_ARM_VSpace = seL4_CPtr;
pub type seL4_ARM_PageUpperDirectory = seL4_CPtr;
pub type seL4_ARM_Page = seL4_CPtr;
pub type seL4_ARM_PageTable = seL4_CPtr;
pub type seL4_ARM_PageDirectory = seL4_CPtr;
pub type seL4_ARM_ASIDControl = seL4_CPtr;
pub type seL4_ARM_ASIDPool = seL4_CPtr;
pub type seL4_ARM_PageDirectory = seL4_CPtr;
pub type seL4_ARM_Page = seL4_CPtr;
pub type seL4_ARM_PageTable = seL4_CPtr;
pub type seL4_ARM_PageUpperDirectory = seL4_CPtr;
pub type seL4_ARM_VSpace = seL4_CPtr;
#[cfg(feature = "arch_generic")]
include!("arm_generic.rs");
error_types!(u64);
@ -85,11 +88,18 @@ pub struct seL4_UserContext {
#[repr(u32)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum seL4_ARM_VMAttributes {
Default = 0,
PageCacheable = 1,
ParityEnabled = 2,
ExecuteNever = 4,
}
pub const Default_VMAttributes: usize = 0;
impl From<u32> for seL4_ARM_VMAttributes {
fn from(val: u32) -> seL4_RISCV_VMAttributes {
unsafe { ::core::mem::transmute(val & 7) }
}
}
pub const seL4_ARM_Default_VMAttributes: seL4_ARM_VMAttributes =
seL4_ARM_VMAttributes::Default;
#[repr(C)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]

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@ -0,0 +1,21 @@
// Arch-independent aliases.
pub type seL4_ASIDControl = seL4_ARM_ASIDControl;
pub type seL4_ASIDPool = seL4_ARM_ASIDPool;
pub type seL4_PageDirectory = seL4_ARM_PageDirectory;
pub type seL4_Page = seL4_ARM_Page;
pub type seL4_PageTable = seL4_ARM_PageTable;
pub type seL4_VMAttributes = seL4_ARM_VMAttributes;
pub use seL4_ObjectType::seL4_ARM_LargePageObject as seL4_LargePageObject;
pub use seL4_ObjectType::seL4_ARM_PageDirectoryObject as seL4_PageDirectoryObject;
pub use seL4_ObjectType::seL4_ARM_PageTableObject as seL4_PageTableObject;
pub use seL4_ObjectType::seL4_ARM_SmallPageObject as seL4_SmallPageObject;
pub use seL4_ARM_Default_VMAttributes as seL4_Default_VMAttributes;
pub use seL4_ARM_ASIDControl_MakePool as seL4_ASIDControl_MakePool;
pub use seL4_ARM_ASIDPool_Assign as seL4_ASIDPool_Assign;
pub use seL4_ARM_PageTable_Map as seL4_PageTable_Map;
pub use seL4_ARM_Page_GetAddress as seL4_Page_GetAddress;
pub use seL4_ARM_Page_Map as seL4_Page_Map;
pub use seL4_ARM_Page_Unmap as seL4_Page_Unmap;

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@ -18,6 +18,7 @@ pub const seL4_ReplyBits: usize = 4;
pub const seL4_EndpointBits: usize = 4;
pub const seL4_PageTableEntryBits: usize = 2;
pub const seL4_PageTableIndexBits: usize = 10;
pub const seL4_PageDirIndexBits: usize = seL4_PageTableIndexBits;
pub const seL4_LargePageBits: usize = 22;
pub const seL4_PageTableBits: usize = 12;
pub const seL4_VSpaceBits: usize = seL4_PageTableBits;
@ -38,6 +39,9 @@ pub type seL4_RISCV_PageTable = seL4_CPtr;
pub type seL4_RISCV_ASIDControl = seL4_CPtr;
pub type seL4_RISCV_ASIDPool = seL4_CPtr;
#[cfg(feature = "arch_generic")]
include!("riscv_generic.rs");
error_types!(u32);
#[repr(C)]
@ -83,14 +87,16 @@ pub struct seL4_UserContext {
#[repr(u32)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum seL4_RISCV_VMAttributes {
Default = 0,
ExecuteNever = 0x1,
Default_VMAttributes = 0,
}
impl From<u32> for seL4_RISCV_VMAttributes {
fn from(val: u32) -> seL4_RISCV_VMAttributes {
unsafe { ::core::mem::transmute(val & 1) }
}
}
pub const seL4_RISCV_Default_VMAttributes: seL4_RISCV_VMAttributes =
seL4_RISCV_VMAttributes::Default;
#[repr(C)]
#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]

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@ -0,0 +1,37 @@
// Arch-independent aliases.
pub type seL4_ASIDControl = seL4_RISCV_ASIDControl;
pub type seL4_ASIDPool = seL4_RISCV_ASIDPool;
pub type seL4_PageDirectory = seL4_RISCV_PageTable;
pub type seL4_Page = seL4_RISCV_Page;
pub type seL4_PageTable = seL4_RISCV_PageTable;
pub type seL4_VMAttributes = seL4_RISCV_VMAttributes;
pub use seL4_ObjectType::seL4_RISCV_Mega_Page as seL4_LargePageObject;
pub use seL4_ObjectType::seL4_RISCV_PageTableObject as seL4_PageDirectoryObject;
pub use seL4_ObjectType::seL4_RISCV_PageTableObject as seL4_PageTableObject;
pub use seL4_ObjectType::seL4_RISCV_4K_Page as seL4_SmallPageObject;
pub use seL4_RISCV_Default_VMAttributes as seL4_Default_VMAttributes;
pub use seL4_RISCV_ASIDControl_MakePool as seL4_ASIDControl_MakePool;
pub use seL4_RISCV_ASIDPool_Assign as seL4_ASIDPool_Assign;
pub use seL4_RISCV_PageTable_Map as seL4_PageTable_Map;
pub use seL4_RISCV_Page_GetAddress as seL4_Page_GetAddress;
// NB: seL4_Page_Map impl found below
pub use seL4_RISCV_Page_Unmap as seL4_Page_Unmap;
pub unsafe fn seL4_Page_Map(
sel4_page: seL4_CPtr,
sel4_pd: seL4_CPtr,
vaddr: seL4_Word,
rights: seL4_CapRights,
vm_attribs: seL4_VMAttributes,
) -> seL4_Result {
if rights.get_capAllowGrant() != 0 {
// NB: executable
seL4_RISCV_Page_Map(sel4_page, sel4_pd, vaddr, rights, vm_attribs)
} else {
seL4_RISCV_Page_Map(sel4_page, sel4_pd, vaddr, rights,
seL4_RISCV_VMAttributes::ExecuteNever)
}
}

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@ -38,17 +38,18 @@ pub const seL4_MaxUntypedBits: usize = 29;
pub type seL4_X86_ASIDControl = seL4_CPtr;
pub type seL4_X86_ASIDPool = seL4_CPtr;
pub type seL4_X86_IOSpace = seL4_CPtr;
pub type seL4_X86_IOPort = seL4_CPtr;
pub type seL4_X86_Page = seL4_CPtr;
pub type seL4_X86_PageDirectory = seL4_CPtr;
pub type seL4_X86_PageTable = seL4_CPtr;
pub type seL4_X86_IOPageTable = seL4_CPtr;
pub type seL4_X86_IOPort = seL4_CPtr;
pub type seL4_X86_IOSpace = seL4_CPtr;
pub type seL4_X86_PageDirectory = seL4_CPtr;
pub type seL4_X86_Page = seL4_CPtr;
pub type seL4_X86_PageTable = seL4_CPtr;
#[cfg(feature = "arch_generic")]
include!("x86_generic.rs");
error_types!(u32);
pub const Default_VMAttributes: usize = 0;
#[repr(C)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum seL4_ObjectType {
@ -102,6 +103,13 @@ pub enum seL4_X86_VMAttributes {
Uncacheable = 3,
WriteCombining = 4,
}
impl From<u32> for seL4_X86_VMAttributes {
fn from(val: u32) -> seL4_x86_VMAttributes {
unsafe { ::core::mem::transmute(val & 7) }
}
}
pub const seL4_X86_Default_VMAttributes: seL4_X86_VMAttributes =
seL4_X86_VMAttributes::WriteBack;
#[repr(C)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]

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@ -35,22 +35,23 @@ pub const seL4_NumExclusiveWatchpoints: usize = 0;
pub const seL4_FirstDualFunctionMonitor: usize = 0;
pub const seL4_NumDualFunctionMonitors: usize = 4;
pub type seL4_X64_PML4 = seL4_CPtr; // XXX X86 v X64
pub type seL4_X86_ASIDControl = seL4_CPtr;
pub type seL4_X86_ASIDPool = seL4_CPtr;
pub type seL4_X86_IOSpace = seL4_CPtr;
pub type seL4_X86_IOPort = seL4_CPtr;
pub type seL4_X86_Page = seL4_CPtr;
pub type seL4_X86_PageDirectory = seL4_CPtr;
pub type seL4_X86_PageTable = seL4_CPtr;
pub type seL4_X86_IOPageTable = seL4_CPtr;
pub type seL4_X86_IOPortControl = seL4_CPtr;
pub type seL4_X86_IOPort = seL4_CPtr;
pub type seL4_X86_IOSpace = seL4_CPtr;
pub type seL4_X86_PageDirectory = seL4_CPtr;
pub type seL4_X86_Page = seL4_CPtr;
pub type seL4_X86_PageTable = seL4_CPtr;
pub type seL4_X86_PDPT = seL4_CPtr;
pub type seL4_X64_PML4 = seL4_CPtr;
#[cfg(feature = "arch_generic")]
include!("x86_generic.rs");
error_types!(u64);
pub const Default_VMAttributes: usize = 0;
#[repr(C)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum seL4_ObjectType {
@ -109,6 +110,13 @@ pub enum seL4_X86_VMAttributes {
Uncacheable = 3,
WriteCombining = 4,
}
impl From<u32> for seL4_X86_VMAttributes {
fn from(val: u32) -> seL4_x86_VMAttributes {
unsafe { ::core::mem::transmute(val & 7) }
}
}
pub const seL4_X86_Default_VMAttributes: seL4_X86_VMAttributes =
seL4_X86_VMAttributes::WriteBack;
#[repr(C)]
#[derive(Debug, Clone, Copy, PartialEq, Eq)]

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@ -0,0 +1,21 @@
// Arch-independent aliases.
pub type seL4_ASIDControl = seL4_X86_ASIDControl;
pub type seL4_ASIDPool = seL4_X86_ASIDPool;
pub type seL4_PageDirectory = seL4_X86_PageDirectory;
pub type seL4_Page = seL4_X86_Page;
pub type seL4_PageTable = seL4_X86_PageTable;
pub type seL4_VMAttributes = seL4_X86_VMAttributes;
pub use seL4_ObjectType::seL4_X86_LargePageObject as seL4_LargePageObject;
pub use seL4_ObjectType::seL4_X86_PageDirectoryObject as seL4_PageDirectoryObject;
pub use seL4_ObjectType::seL4_X86_PageTableObject as seL4_PageTableObject;
pub use seL4_ObjectType::seL4_X86_SmallPageObject as seL4_SmallPageObject;
pub use seL4_X86_Default_VMAttributes as seL4_Default_VMAttributes;
pub use seL4_X86_ASIDControl_MakePool as seL4_ASIDControl_MakePool;
pub use seL4_X86_ASIDPool_Assign as seL4_ASIDPool_Assign;
pub use seL4_X86_PageTable_Map as seL4_PageTable_Map;
pub use seL4_X86_Page_GetAddress as seL4_Page_GetAddress;
pub use seL4_X86_Page_Map as seL4_Page_Map;
pub use seL4_X86_Page_Unmap as seL4_Page_Unmap;