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HV: centralize the pci cfg read/write sanity checking code
Do the pci cfg read/write sanity checking before the request is dispatched to submodules, so that the checking is centralized rather than scattered across multiple files/places Tracked-On: #2534 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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a403128a46
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026250fd8a
@ -91,12 +91,6 @@ void vdev_hostbridge_deinit(__unused const struct pci_vdev *vdev)
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int32_t vdev_hostbridge_cfgread(const struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t *val)
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{
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/* Assumption: access needed to be aligned on 1/2/4 bytes */
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if ((offset & (bytes - 1U)) != 0U) {
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*val = 0xFFFFFFFFU;
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return -EINVAL;
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}
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*val = pci_vdev_read_cfg(vdev, offset, bytes);
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return 0;
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@ -105,11 +99,6 @@ int32_t vdev_hostbridge_cfgread(const struct pci_vdev *vdev, uint32_t offset,
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int32_t vdev_hostbridge_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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{
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/* Assumption: access needed to be aligned on 1/2/4 bytes */
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if ((offset & (bytes - 1U)) != 0U) {
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return -EINVAL;
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}
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if (!pci_bar_access(offset)) {
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pci_vdev_write_cfg(vdev, offset, bytes, val);
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}
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@ -118,6 +118,7 @@ static int32_t vmsi_remap(const struct pci_vdev *vdev, bool enable)
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int32_t vmsi_cfgread(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val)
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{
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int32_t ret;
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/* For PIO access, we emulate Capability Structures only */
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if (msicap_access(vdev, offset)) {
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*val = pci_vdev_read_cfg(vdev, offset, bytes);
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@ -105,12 +105,6 @@ void vdev_pt_deinit(const struct pci_vdev *vdev)
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int32_t vdev_pt_cfgread(const struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t *val)
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{
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/* Assumption: access needed to be aligned on 1/2/4 bytes */
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if ((offset & (bytes - 1U)) != 0U) {
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*val = 0xFFFFFFFFU;
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return -EINVAL;
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}
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/* PCI BARs is emulated */
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if (pci_bar_access(offset)) {
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*val = pci_vdev_read_cfg(vdev, offset, bytes);
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@ -184,11 +178,6 @@ static void vdev_pt_cfgwrite_bar(struct pci_vdev *vdev, uint32_t offset,
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int32_t vdev_pt_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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{
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/* Assumption: access needed to be aligned on 1/2/4 bytes */
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if ((offset & (bytes - 1U)) != 0U) {
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return -EINVAL;
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}
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/* PCI BARs are emulated */
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if (pci_bar_access(offset)) {
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vdev_pt_cfgwrite_bar(vdev, offset, bytes, val);
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@ -50,7 +50,7 @@ void sharing_mode_cfgread(__unused struct acrn_vpci *vpci, union pci_bdf bdf,
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vdev = sharing_mode_find_vdev_sos(bdf);
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/* vdev == NULL: Could be hit for PCI enumeration from guests */
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if ((vdev == NULL) || ((bytes != 1U) && (bytes != 2U) && (bytes != 4U))) {
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if (vdev == NULL) {
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*val = ~0U;
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} else {
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if ((vmsi_cfgread(vdev, offset, bytes, val) != 0)
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@ -67,15 +67,13 @@ void sharing_mode_cfgwrite(__unused struct acrn_vpci *vpci, union pci_bdf bdf,
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{
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struct pci_vdev *vdev;
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if ((bytes == 1U) || (bytes == 2U) || (bytes == 4U)) {
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vdev = sharing_mode_find_vdev_sos(bdf);
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if (vdev != NULL) {
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if ((vmsi_cfgwrite(vdev, offset, bytes, val) != 0)
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&& (vmsix_cfgwrite(vdev, offset, bytes, val) != 0)
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) {
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/* Not handled by any handlers, passthru to physical device */
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pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val);
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}
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vdev = sharing_mode_find_vdev_sos(bdf);
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if (vdev != NULL) {
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if ((vmsi_cfgwrite(vdev, offset, bytes, val) != 0)
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&& (vmsix_cfgwrite(vdev, offset, bytes, val) != 0)
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) {
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/* Not handled by any handlers, passthru to physical device */
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pci_pdev_write_cfg(vdev->pdev->bdf, offset, bytes, val);
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}
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}
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}
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@ -67,6 +67,21 @@ static void pci_cfgaddr_io_write(struct acrn_vm *vm, uint16_t addr, size_t bytes
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}
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}
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static inline bool vpci_is_valid_access_offset(uint32_t offset, uint32_t bytes)
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{
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return ((offset & (bytes - 1U)) == 0U);
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}
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static inline bool vpci_is_valid_access_byte(uint32_t bytes)
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{
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return ((bytes == 1U) || (bytes == 2U) || (bytes == 4U));
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}
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static inline bool vpci_is_valid_access(uint32_t offset, uint32_t bytes)
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{
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return (vpci_is_valid_access_byte(bytes) && vpci_is_valid_access_offset(offset, bytes));
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}
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static uint32_t pci_cfgdata_io_read(struct acrn_vm *vm, uint16_t addr, size_t bytes)
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{
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struct acrn_vpci *vpci = &vm->vpci;
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@ -75,11 +90,13 @@ static uint32_t pci_cfgdata_io_read(struct acrn_vm *vm, uint16_t addr, size_t by
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uint32_t val = ~0U;
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if (pi->cached_enable) {
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if (vpci_is_valid_access(pi->cached_reg + offset, bytes)) {
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#ifdef CONFIG_PARTITION_MODE
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partition_mode_cfgread(vpci, pi->cached_bdf, pi->cached_reg + offset, bytes, &val);
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partition_mode_cfgread(vpci, pi->cached_bdf, pi->cached_reg + offset, bytes, &val);
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#else
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sharing_mode_cfgread(vpci, pi->cached_bdf, pi->cached_reg + offset, bytes, &val);
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sharing_mode_cfgread(vpci, pi->cached_bdf, pi->cached_reg + offset, bytes, &val);
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#endif
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}
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pci_cfg_clear_cache(pi);
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}
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@ -93,11 +110,13 @@ static void pci_cfgdata_io_write(struct acrn_vm *vm, uint16_t addr, size_t bytes
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uint16_t offset = addr - PCI_CONFIG_DATA;
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if (pi->cached_enable) {
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if (vpci_is_valid_access(pi->cached_reg + offset, bytes)) {
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#ifdef CONFIG_PARTITION_MODE
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partition_mode_cfgwrite(vpci, pi->cached_bdf, pi->cached_reg + offset, bytes, val);
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partition_mode_cfgwrite(vpci, pi->cached_bdf, pi->cached_reg + offset, bytes, val);
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#else
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sharing_mode_cfgwrite(vpci, pi->cached_bdf, pi->cached_reg + offset, bytes, val);
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sharing_mode_cfgwrite(vpci, pi->cached_bdf, pi->cached_reg + offset, bytes, val);
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#endif
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}
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pci_cfg_clear_cache(pi);
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}
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}
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