HV: centralize the pci cfg read/write sanity checking code

Do the pci cfg read/write sanity checking before the request is dispatched to
submodules, so that the checking is centralized rather than scattered across multiple
files/places

Tracked-On: #2534
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
dongshen
2019-03-06 16:24:52 -08:00
committed by Eddie Dong
parent a403128a46
commit 026250fd8a
5 changed files with 32 additions and 36 deletions

View File

@@ -91,12 +91,6 @@ void vdev_hostbridge_deinit(__unused const struct pci_vdev *vdev)
int32_t vdev_hostbridge_cfgread(const struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t *val)
{
/* Assumption: access needed to be aligned on 1/2/4 bytes */
if ((offset & (bytes - 1U)) != 0U) {
*val = 0xFFFFFFFFU;
return -EINVAL;
}
*val = pci_vdev_read_cfg(vdev, offset, bytes);
return 0;
@@ -105,11 +99,6 @@ int32_t vdev_hostbridge_cfgread(const struct pci_vdev *vdev, uint32_t offset,
int32_t vdev_hostbridge_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t val)
{
/* Assumption: access needed to be aligned on 1/2/4 bytes */
if ((offset & (bytes - 1U)) != 0U) {
return -EINVAL;
}
if (!pci_bar_access(offset)) {
pci_vdev_write_cfg(vdev, offset, bytes, val);
}