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HV: centralize the pci cfg read/write sanity checking code

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Do the pci cfg read/write sanity checking before the request is dispatched to
submodules, so that the checking is centralized rather than scattered across multiple
files/places

Tracked-On: #2534
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
dongshen
2019-03-06 16:24:52 -08:00
committed by Eddie Dong
parent a403128a46
commit 026250fd8a
5 changed files with 32 additions and 36 deletions
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1
hypervisor/dm/vpci/msi.c
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@@ -118,6 +118,7 @@ static int32_t vmsi_remap(const struct pci_vdev *vdev, bool enable)
int32_t vmsi_cfgread(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val)
{
int32_t ret;
/* For PIO access, we emulate Capability Structures only */
if (msicap_access(vdev, offset)) {
*val = pci_vdev_read_cfg(vdev, offset, bytes);