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HV:treewide:Replace HOST_GDT_RING0_CODE/DATA_SEL with constant

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MISRA C requires that all unsigned constants should have
the suffix 'U/UL'(e.g. 0xffU), but the assembler may not
accept such C-style constants.

To work this around, HOST_GDT_RING0_CODE_SEL and
HOST_GDT_RING0_DATA_SEL must be explicitly spells
out in assembly with a comment tracking the original
expression from which the magic number is calculated.

V1-->V2:
	Update commit information about HOST_GDT_RING0_CODE_SEL
	and HOST_GDT_RING0_DATA_SEL.
V2-->V3:
	Update comment for HOST_GDT_RING0_CODE_SEL in assembly
	code.

Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Xiangyang Wu 2018-07-13 16:27:30 +08:00 committed by lijinxia
parent f2774e496b
commit 055153bf3e
3 changed files with 14 additions and 8 deletions
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9
hypervisor/arch/x86/cpu_primary.S
View File

@ -112,7 +112,8 @@ cpu_primary_start_32:
lgdt (%ebx) lgdt (%ebx)
/* Perform a long jump based to start executing in 64-bit mode */ /* Perform a long jump based to start executing in 64-bit mode */
ljmp $HOST_GDT_RING0_CODE_SEL, $primary_start_long_mode /* 0x0008 = HOST_GDT_RING0_CODE_SEL */
ljmp $0x0008, $primary_start_long_mode
.code64 .code64
.org 0x200 .org 0x200
@ -150,13 +151,15 @@ primary_start_long_mode:
rex.w ljmp *(%rax) rex.w ljmp *(%rax)
.data .data
jmpbuf: .quad 0 jmpbuf: .quad 0
.word HOST_GDT_RING0_CODE_SEL /* 0x0008 = HOST_GDT_RING0_CODE_SEL */
.word 0x0008
.text .text
after: after:
// load all selector registers with appropriate values // load all selector registers with appropriate values
xor %edx, %edx xor %edx, %edx
lldt %dx lldt %dx
movl $HOST_GDT_RING0_DATA_SEL,%eax /* 0x10 = HOST_GDT_RING0_DATA_SEL*/
movl $0x10,%eax
mov %eax,%ss // Was 32bit POC Stack mov %eax,%ss // Was 32bit POC Stack
mov %eax,%ds // Was 32bit POC Data mov %eax,%ds // Was 32bit POC Data
mov %eax,%es // Was 32bit POC Data mov %eax,%es // Was 32bit POC Data

6
hypervisor/arch/x86/idt.S
View File

@ -24,13 +24,15 @@ HOST_IDTR:
* We'll rearrange and fix up the descriptors at runtime * We'll rearrange and fix up the descriptors at runtime
*/ */
.macro interrupt_descriptor entry, dpl=0 ist=0 .macro interrupt_descriptor entry, dpl=0 ist=0
.long HOST_GDT_RING0_CODE_SEL << 16 /* 0x0008 = HOST_GDT_RING0_CODE_SEL */
.long 0x0008 << 16
.long 0x00008e00 + (dpl << 13) + ist .long 0x00008e00 + (dpl << 13) + ist
.quad entry .quad entry
.endm .endm
.macro trap_descriptor entry, dpl=0, ist=0 .macro trap_descriptor entry, dpl=0, ist=0
.long HOST_GDT_RING0_CODE_SEL << 16 /* 0x0008 = HOST_GDT_RING0_CODE_SEL */
.long 0x0008 << 16
.long 0x00008f00 + (dpl <<13) + ist .long 0x00008f00 + (dpl <<13) + ist
.quad entry .quad entry
.endm .endm

7
hypervisor/arch/x86/trampoline.S
View File

@ -133,14 +133,15 @@ trampoline_fixup_target:
.global trampoline_start64_fixup .global trampoline_start64_fixup
trampoline_start64_fixup: trampoline_start64_fixup:
.long trampoline_start64 .long trampoline_start64
.word HOST_GDT_RING0_CODE_SEL /* 0x0008 = HOST_GDT_RING0_CODE_SEL */
.word 0x0008
.code64 .code64
trampoline_start64: trampoline_start64:
/* Set up all other data segment registers */ /* Set up all other data segment registers */
/* 0x0010 = HOST_GDT_RING0_DATA_SEL */
movl $HOST_GDT_RING0_DATA_SEL, %eax movl $0x0010, %eax
mov %eax, %ss mov %eax, %ss
mov %eax, %ds mov %eax, %ds
mov %eax, %es mov %eax, %es