github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-20 12:42:54 +00:00
Code Issues Projects Releases Wiki Activity

hv: cpu: refine secondary cpu start up

Browse Source 
1) add a write memory barrier after setting pcpu_sync to one to let this change
visible to AP immediately.
2) there's only BSP will set pcpu_sync, so there's no memory order issue between CPUs.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Li, Fei1 2019-07-03 19:54:09 +08:00 committed by wenlingz
parent 5930e96d12
commit 05a4ee8074
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
hypervisor/arch/x86/cpu.c
View File

@ -5,7 +5,6 @@
*/ */
#include <types.h> #include <types.h>
#include <atomic.h>
#include <bits.h> #include <bits.h>
#include <page.h> #include <page.h>
#include <e820.h> #include <e820.h>
@ -311,7 +310,8 @@ bool start_pcpus(uint64_t mask)
uint64_t expected_start_mask = mask; uint64_t expected_start_mask = mask;
/* secondary cpu start up will wait for pcpu_sync -> 0UL */ /* secondary cpu start up will wait for pcpu_sync -> 0UL */
atomic_store64(&pcpu_sync, 1UL); pcpu_sync = 1UL;
cpu_write_memory_barrier();
i = ffs64(expected_start_mask); i = ffs64(expected_start_mask);
while (i != INVALID_BIT_INDEX) { while (i != INVALID_BIT_INDEX) {
@ -326,7 +326,7 @@ bool start_pcpus(uint64_t mask)
} }
/* Trigger event to allow secondary CPUs to continue */ /* Trigger event to allow secondary CPUs to continue */
atomic_store64(&pcpu_sync, 0UL); pcpu_sync = 0UL;
return ((pcpu_active_bitmap & mask) == mask); return ((pcpu_active_bitmap & mask) == mask);
} }