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hv: multi-arch add RISC-V barrier library implementation

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Follow multi-arch design, implement the mandatory arch barrier
functions declared in common barrier.h for risc-v support.

Tracked-On: #8803
Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com>
Co-developed-by: Haoyu Tang <haoyu.tang@intel.com>
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Reviewed-by: Yifan Liu  <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This commit is contained in:
Haicheng Li
2025-09-07 11:27:56 +08:00
committed by acrnsi-robot
parent f67a437e5a
commit 090aaf4c34
2 changed files with 30 additions and 2 deletions
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4
hypervisor/include/arch/riscv/asm/cpu.h
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@@ -12,9 +12,9 @@
#include <lib/util.h>
#include <debug/logmsg.h>
#include <board_info.h>
#include <barrier.h>
#define barrier() __asm__ __volatile__("fence": : :"memory")
#define cpu_relax() barrier() /* TODO: replace with yield instruction */
#define cpu_relax() cpu_memory_barrier() /* TODO: replace with yield instruction */
#define NR_CPUS MAX_PCPU_NUM
#define LONG_BYTEORDER 3

28
hypervisor/include/arch/riscv/asm/lib/barrier.h Normal file
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@@ -0,0 +1,28 @@
/*
* Copyright (C) 2023-2025 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Authors:
* Haicheng Li <haicheng.li@intel.com>
*/
#ifndef RISCV_LIB_BARRIER_H
#define RISCV_LIB_BARRIER_H
/* Synchronizes all read accesses to/from memory */
static inline void arch_cpu_read_memory_barrier(void)
{
asm volatile ("fence r,r" : : : "memory");
}
static inline void arch_cpu_write_memory_barrier(void)
{
asm volatile ("fence w,w" : : : "memory");
}
/* Synchronizes all read and write accesses to/from memory */
static inline void arch_cpu_memory_barrier(void)
{
asm volatile ("fence rw,rw" : : : "memory");
}
#endif /* RISCV_LIB_BARRIER_H */