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make detect_cpu_cap as internal function
call detect_cpu_cap in init_cpu_capabilities Tracked-On: #1842 Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
Jason Chen CJ
wenlingz
parent
e22217fd8f
commit
0ad6da998c
@ -116,8 +116,6 @@ void init_cpu_pre(uint16_t pcpu_id)
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panic("x2APIC is not present!");
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}
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detect_cpu_cap();
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early_init_lapic();
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init_percpu_lapic_id();
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@ -88,91 +88,6 @@ static inline bool is_fast_string_erms_supported_and_enabled(void)
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return ret;
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}
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static uint64_t get_address_mask(uint8_t limit)
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{
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return ((1UL << limit) - 1UL) & PAGE_MASK;
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}
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void init_cpu_capabilities(void)
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{
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uint32_t eax, unused;
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uint32_t family, model;
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cpuid(CPUID_VENDORSTRING,
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&boot_cpu_data.cpuid_level,
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&unused, &unused, &unused);
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cpuid(CPUID_FEATURES, &eax, &unused,
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&boot_cpu_data.cpuid_leaves[FEAT_1_ECX],
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&boot_cpu_data.cpuid_leaves[FEAT_1_EDX]);
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family = (eax >> 8U) & 0xffU;
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if (family == 0xFU) {
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family += (eax >> 20U) & 0xffU;
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}
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boot_cpu_data.family = (uint8_t)family;
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model = (eax >> 4U) & 0xfU;
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if (family >= 0x06U) {
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model += ((eax >> 16U) & 0xfU) << 4U;
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}
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boot_cpu_data.model = (uint8_t)model;
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cpuid(CPUID_EXTEND_FEATURE, &unused,
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&boot_cpu_data.cpuid_leaves[FEAT_7_0_EBX],
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&boot_cpu_data.cpuid_leaves[FEAT_7_0_ECX],
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&boot_cpu_data.cpuid_leaves[FEAT_7_0_EDX]);
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cpuid(CPUID_MAX_EXTENDED_FUNCTION,
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&boot_cpu_data.extended_cpuid_level,
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&unused, &unused, &unused);
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if (boot_cpu_data.extended_cpuid_level >= CPUID_EXTEND_FUNCTION_1) {
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cpuid(CPUID_EXTEND_FUNCTION_1, &unused, &unused,
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&boot_cpu_data.cpuid_leaves[FEAT_8000_0001_ECX],
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&boot_cpu_data.cpuid_leaves[FEAT_8000_0001_EDX]);
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}
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if (boot_cpu_data.extended_cpuid_level >= CPUID_EXTEND_ADDRESS_SIZE) {
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cpuid(CPUID_EXTEND_ADDRESS_SIZE, &eax,
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&boot_cpu_data.cpuid_leaves[FEAT_8000_0008_EBX],
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&unused, &unused);
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/* EAX bits 07-00: #Physical Address Bits
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* bits 15-08: #Linear Address Bits
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*/
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boot_cpu_data.virt_bits = (uint8_t)((eax >> 8U) & 0xffU);
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boot_cpu_data.phys_bits = (uint8_t)(eax & 0xffU);
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boot_cpu_data.physical_address_mask =
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get_address_mask(boot_cpu_data.phys_bits);
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}
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/* For speculation defence.
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* The default way is to set IBRS at vmexit and then do IBPB at vcpu
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* context switch(ibrs_type == IBRS_RAW).
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* Now provide an optimized way (ibrs_type == IBRS_OPT) which set
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* STIBP and do IBPB at vmexit,since having STIBP always set has less
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* impact than having IBRS always set. Also since IBPB is already done
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* at vmexit, it is no necessary to do so at vcpu context switch then.
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*/
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ibrs_type = IBRS_NONE;
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/* Currently for APL, if we enabled retpoline, then IBRS should not
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* take effect
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* TODO: add IA32_ARCH_CAPABILITIES[1] check, if this bit is set, IBRS
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* should be set all the time instead of relying on retpoline
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*/
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#ifndef CONFIG_RETPOLINE
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if (cpu_has_cap(X86_FEATURE_IBRS_IBPB)) {
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ibrs_type = IBRS_RAW;
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if (cpu_has_cap(X86_FEATURE_STIBP)) {
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ibrs_type = IBRS_OPT;
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}
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}
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#endif
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}
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/*check allowed ONEs setting in vmx control*/
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static bool is_ctrl_setting_allowed(uint64_t msr_val, uint32_t ctrl)
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{
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@ -270,13 +185,99 @@ static void detect_vmx_mmu_cap(void)
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cpu_caps.vmx_vpid = (uint32_t) (val >> 32U);
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}
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void detect_cpu_cap(void)
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static void detect_cpu_cap(void)
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{
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detect_apicv_cap();
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detect_ept_cap();
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detect_vmx_mmu_cap();
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}
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static uint64_t get_address_mask(uint8_t limit)
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{
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return ((1UL << limit) - 1UL) & PAGE_MASK;
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}
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void init_cpu_capabilities(void)
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{
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uint32_t eax, unused;
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uint32_t family, model;
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cpuid(CPUID_VENDORSTRING,
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&boot_cpu_data.cpuid_level,
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&unused, &unused, &unused);
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cpuid(CPUID_FEATURES, &eax, &unused,
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&boot_cpu_data.cpuid_leaves[FEAT_1_ECX],
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&boot_cpu_data.cpuid_leaves[FEAT_1_EDX]);
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family = (eax >> 8U) & 0xffU;
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if (family == 0xFU) {
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family += (eax >> 20U) & 0xffU;
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}
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boot_cpu_data.family = (uint8_t)family;
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model = (eax >> 4U) & 0xfU;
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if (family >= 0x06U) {
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model += ((eax >> 16U) & 0xfU) << 4U;
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}
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boot_cpu_data.model = (uint8_t)model;
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cpuid(CPUID_EXTEND_FEATURE, &unused,
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&boot_cpu_data.cpuid_leaves[FEAT_7_0_EBX],
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&boot_cpu_data.cpuid_leaves[FEAT_7_0_ECX],
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&boot_cpu_data.cpuid_leaves[FEAT_7_0_EDX]);
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cpuid(CPUID_MAX_EXTENDED_FUNCTION,
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&boot_cpu_data.extended_cpuid_level,
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&unused, &unused, &unused);
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if (boot_cpu_data.extended_cpuid_level >= CPUID_EXTEND_FUNCTION_1) {
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cpuid(CPUID_EXTEND_FUNCTION_1, &unused, &unused,
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&boot_cpu_data.cpuid_leaves[FEAT_8000_0001_ECX],
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&boot_cpu_data.cpuid_leaves[FEAT_8000_0001_EDX]);
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}
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if (boot_cpu_data.extended_cpuid_level >= CPUID_EXTEND_ADDRESS_SIZE) {
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cpuid(CPUID_EXTEND_ADDRESS_SIZE, &eax,
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&boot_cpu_data.cpuid_leaves[FEAT_8000_0008_EBX],
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&unused, &unused);
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/* EAX bits 07-00: #Physical Address Bits
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* bits 15-08: #Linear Address Bits
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*/
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boot_cpu_data.virt_bits = (uint8_t)((eax >> 8U) & 0xffU);
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boot_cpu_data.phys_bits = (uint8_t)(eax & 0xffU);
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boot_cpu_data.physical_address_mask =
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get_address_mask(boot_cpu_data.phys_bits);
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}
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detect_cpu_cap();
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/* For speculation defence.
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* The default way is to set IBRS at vmexit and then do IBPB at vcpu
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* context switch(ibrs_type == IBRS_RAW).
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* Now provide an optimized way (ibrs_type == IBRS_OPT) which set
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* STIBP and do IBPB at vmexit,since having STIBP always set has less
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* impact than having IBRS always set. Also since IBPB is already done
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* at vmexit, it is no necessary to do so at vcpu context switch then.
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*/
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ibrs_type = IBRS_NONE;
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/* Currently for APL, if we enabled retpoline, then IBRS should not
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* take effect
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* TODO: add IA32_ARCH_CAPABILITIES[1] check, if this bit is set, IBRS
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* should be set all the time instead of relying on retpoline
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*/
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#ifndef CONFIG_RETPOLINE
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if (cpu_has_cap(X86_FEATURE_IBRS_IBPB)) {
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ibrs_type = IBRS_RAW;
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if (cpu_has_cap(X86_FEATURE_STIBP)) {
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ibrs_type = IBRS_OPT;
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}
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}
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#endif
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}
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static bool is_ept_supported(void)
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{
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return (cpu_caps.ept_features != 0U);
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@ -68,7 +68,6 @@ bool cpu_has_vmx_ept_cap(uint32_t bit_mask);
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bool cpu_has_vmx_vpid_cap(uint32_t bit_mask);
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void init_cpu_capabilities(void);
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void init_cpu_model_name(void);
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void detect_cpu_cap(void);
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bool check_cpu_security_cap(void);
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void cpu_l1d_flush(void);
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int detect_hardware_support(void);
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