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acrn-config: Fixes for BAR remapping logic

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This patch does the following
1) Removes the limitation on BAR size for 1 GB
2) Align the BAR address to the BAR size

Tracked-On: #4586
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Sainath Grandhi 2020-04-02 22:42:14 -07:00 committed by wenlingz
parent dc7f218314
commit 140077f225
3 changed files with 8 additions and 15 deletions
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19
misc/acrn-config/board_config/pci_devices_h.py
View File

@ -14,10 +14,6 @@ PCI_END_HEADER = r"""
#endif /* PCI_DEVICES_H_ */""" #endif /* PCI_DEVICES_H_ */"""
MEM_ALIGN = 2 * board_cfg_lib.SIZE_M
#TODO: Support 64Bit Bar for huge MMIO than HUGE_MMIO_LIMIT
SUPPORT_HUGE_HI_MMIO = False
HUGE_MMIO_LIMIT = board_cfg_lib.SIZE_2G / 2
HI_MMIO_OFFSET = 0 HI_MMIO_OFFSET = 0
class Bar_Mem: class Bar_Mem:
@ -62,7 +58,9 @@ def get_size(line):
# get size string from format, Region n: Memory at x ... [size=NK] # get size string from format, Region n: Memory at x ... [size=NK]
size_str = line.split()[-1].strip(']').split('=')[1] size_str = line.split()[-1].strip(']').split('=')[1]
if 'M' in size_str: if 'G' in size_str:
size = int(size_str.strip('G')) * board_cfg_lib.SIZE_G
elif 'M' in size_str:
size = int(size_str.strip('M')) * board_cfg_lib.SIZE_M size = int(size_str.strip('M')) * board_cfg_lib.SIZE_M
elif 'K' in size_str: elif 'K' in size_str:
size = int(size_str.strip('K')) * board_cfg_lib.SIZE_K size = int(size_str.strip('K')) * board_cfg_lib.SIZE_K
@ -71,13 +69,13 @@ def get_size(line):
return size return size
# round up the running bar_addr to the size of the incoming bar "line"
def remap_bar_addr_to_high(bar_addr, line): def remap_bar_addr_to_high(bar_addr, line):
"""Generate vbar address""" """Generate vbar address"""
global HI_MMIO_OFFSET global HI_MMIO_OFFSET
cur_addr = board_cfg_lib.round_up(bar_addr, MEM_ALIGN)
size = get_size(line) size = get_size(line)
HI_MMIO_OFFSET = board_cfg_lib.round_up(cur_addr + size, MEM_ALIGN) cur_addr = board_cfg_lib.round_up(bar_addr, size)
HI_MMIO_OFFSET = cur_addr + size
return cur_addr return cur_addr
@ -105,11 +103,6 @@ def parser_pci():
if bar_addr >= board_cfg_lib.SIZE_4G or bar_addr < board_cfg_lib.SIZE_2G: if bar_addr >= board_cfg_lib.SIZE_4G or bar_addr < board_cfg_lib.SIZE_2G:
if not tmp_bar_attr.remappable: if not tmp_bar_attr.remappable:
continue continue
#TODO: Support 64Bit Bar for huge MMIO than HUGE_MMIO_LIMIT
if not SUPPORT_HUGE_HI_MMIO and get_size(line) >= HUGE_MMIO_LIMIT:
tmp_bar_attr.remappable = False
PCI_DEV_BAR_DESC.pci_dev_dic[pci_bdf] = tmp_bar_attr
continue
bar_addr = remap_bar_addr_to_high(HI_MMIO_OFFSET, line) bar_addr = remap_bar_addr_to_high(HI_MMIO_OFFSET, line)
tmp_bar_mem.remapped = True tmp_bar_mem.remapped = True

2
misc/acrn-config/library/board_cfg_lib.py
View File

@ -43,7 +43,7 @@ SIZE_K = common.SIZE_K
SIZE_M = common.SIZE_M SIZE_M = common.SIZE_M
SIZE_2G = common.SIZE_2G SIZE_2G = common.SIZE_2G
SIZE_4G = common.SIZE_4G SIZE_4G = common.SIZE_4G
SIZE_G = common.SIZE_G
def prepare(): def prepare():
""" check environment """ """ check environment """

2
misc/acrn-config/library/common.py
View File

@ -29,7 +29,7 @@ SIZE_K = 1024
SIZE_M = SIZE_K * 1024 SIZE_M = SIZE_K * 1024
SIZE_2G = 2 * SIZE_M * SIZE_K SIZE_2G = 2 * SIZE_M * SIZE_K
SIZE_4G = 2 * SIZE_2G SIZE_4G = 2 * SIZE_2G
SIZE_G = SIZE_M * 1024
class MultiItem(): class MultiItem():