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https://github.com/projectacrn/acrn-hypervisor.git
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HV:Added support to setup tool & start/stop profing
profiling_set_control:
Receives tool control information from guest and sets control switches accordingly,
tool control information includes:
type - sep/socwatch
action - Start/stop
feature - What to collect(core/lbr/vm switch)
This function provides interface to start and stop profiling data collection
profiling_start_pmu:
Initialize sep state and enable PMU counters
SMP calls profiling_enable_pmu
profiling_stop_pmu:
Reset sep state and Disable all the PMU counters
SMP calls profiling_disable_pmu
profiling_enable_pmu:
Enable all the Performance Monitoring Control registers.
Unmask LAPIC entry for PMC register to enable performance monitoring
Walk through the entries and write to PMU control regiesters
profiling_disable_pmu:
Disable all Performance Monitoring Control registers
Tracked-On: projectacrn#1409
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Chinthapally, Manisha <manisha.chinthapally@intel.com>
This commit is contained in:
Manisha Chinthapally
wenlingz
parent
898b9c8d4a
commit
1786f6222a
@ -13,9 +13,14 @@
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#define MAJOR_VERSION 1
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#define MINOR_VERSION 0
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#define LVT_PERFCTR_BIT_UNMASK 0xFFFEFFFFU
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#define LVT_PERFCTR_BIT_MASK 0x10000U
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#define VALID_DEBUGCTL_BIT_MASK 0x1801U
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static uint64_t sep_collection_switch;
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static uint64_t socwatch_collection_switch;
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static bool in_pmu_profiling;
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static uint32_t profiling_pmi_irq = IRQ_INVALID;
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@ -79,7 +84,73 @@ static void profiling_initialize_pmi(void)
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*/
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static void profiling_enable_pmu(void)
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{
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/* to be implemented */
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uint32_t lvt_perf_ctr;
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uint32_t i;
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uint32_t group_id;
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struct profiling_msr_op *msrop = NULL;
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struct sep_state *ss = &get_cpu_var(profiling_info.sep_state);
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering cpu%d",
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__func__, get_cpu_id());
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if (ss == NULL) {
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dev_dbg(ACRN_ERR_PROFILING, "%s: exiting cpu%d",
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__func__, get_cpu_id());
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return;
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}
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/* Unmask LAPIC LVT entry for PMC register */
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lvt_perf_ctr = (uint32_t) msr_read(MSR_IA32_EXT_APIC_LVT_PMI);
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dev_dbg(ACRN_DBG_PROFILING, "%s: 0x%x, 0x%llx",
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__func__, MSR_IA32_EXT_APIC_LVT_PMI, lvt_perf_ctr);
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lvt_perf_ctr &= LVT_PERFCTR_BIT_UNMASK;
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msr_write(MSR_IA32_EXT_APIC_LVT_PMI, lvt_perf_ctr);
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dev_dbg(ACRN_DBG_PROFILING, "%s: 0x%x, 0x%llx",
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__func__, MSR_IA32_EXT_APIC_LVT_PMI, lvt_perf_ctr);
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if (ss->guest_debugctl_value != 0U) {
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/* Set the VM Exit MSR Load in VMCS */
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if (ss->vmexit_msr_cnt == 0) {
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ss->vmexit_msr_cnt = 1;
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ss->vmexit_msr_list[0].msr_idx
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= MSR_IA32_DEBUGCTL;
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ss->vmexit_msr_list[0].msr_data
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= ss->guest_debugctl_value &
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VALID_DEBUGCTL_BIT_MASK;
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exec_vmwrite64(VMX_EXIT_MSR_LOAD_ADDR_FULL,
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hva2hpa(ss->vmexit_msr_list));
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exec_vmwrite(VMX_EXIT_MSR_LOAD_COUNT,
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(uint64_t)ss->vmexit_msr_cnt);
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}
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/* VMCS GUEST field */
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ss->saved_debugctl_value
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= exec_vmread64(VMX_GUEST_IA32_DEBUGCTL_FULL);
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exec_vmwrite64(VMX_GUEST_IA32_DEBUGCTL_FULL,
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(ss->guest_debugctl_value & VALID_DEBUGCTL_BIT_MASK));
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}
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group_id = ss->current_pmi_group_id;
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for (i = 0U; i < MAX_MSR_LIST_NUM; i++) {
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msrop = &(ss->pmi_start_msr_list[group_id][i]);
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if (msrop != NULL) {
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if (msrop->msr_id == (uint32_t)-1) {
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break;
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}
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if (msrop->msr_op_type == (uint8_t)MSR_OP_WRITE) {
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msr_write(msrop->msr_id, msrop->value);
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: MSRWRITE cpu%d, msr_id=0x%x, msr_val=0x%llx",
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__func__, get_cpu_id(), msrop->msr_id, msrop->value);
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}
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}
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}
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ss->pmu_state = PMU_RUNNING;
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dev_dbg(ACRN_DBG_PROFILING, "%s: exiting cpu%d",
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__func__, get_cpu_id());
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}
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/*
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@ -87,7 +158,57 @@ static void profiling_enable_pmu(void)
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*/
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static void profiling_disable_pmu(void)
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{
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/* to be implemented */
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uint32_t lvt_perf_ctr;
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uint32_t i;
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uint32_t group_id;
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struct profiling_msr_op *msrop = NULL;
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struct sep_state *ss = &get_cpu_var(profiling_info.sep_state);
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering cpu%d",
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__func__, get_cpu_id());
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if (ss == NULL) {
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dev_dbg(ACRN_ERR_PROFILING, "%s: exiting cpu%d",
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__func__, get_cpu_id());
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return;
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}
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if (ss->vmexit_msr_cnt == 1) {
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/* Set the VM Exit MSR Load in VMCS */
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exec_vmwrite(VMX_EXIT_MSR_LOAD_COUNT, 0x0U);
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exec_vmwrite64(VMX_GUEST_IA32_DEBUGCTL_FULL,
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ss->saved_debugctl_value);
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ss->vmexit_msr_cnt = 0;
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}
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group_id = ss->current_pmi_group_id;
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for (i = 0U; i < MAX_MSR_LIST_NUM; i++) {
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msrop = &(ss->pmi_stop_msr_list[group_id][i]);
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if (msrop != NULL) {
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if (msrop->msr_id == (uint32_t)-1) {
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break;
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}
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if (msrop->msr_op_type == (uint8_t)MSR_OP_WRITE) {
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msr_write(msrop->msr_id, msrop->value);
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: MSRWRITE cpu%d, msr_id=0x%x, msr_val=0x%llx",
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__func__, get_cpu_id(), msrop->msr_id, msrop->value);
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}
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}
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}
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/* Mask LAPIC LVT entry for PMC register */
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lvt_perf_ctr = (uint32_t) msr_read(MSR_IA32_EXT_APIC_LVT_PMI);
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lvt_perf_ctr |= LVT_PERFCTR_BIT_MASK;
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msr_write(MSR_IA32_EXT_APIC_LVT_PMI, lvt_perf_ctr);
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ss->pmu_state = PMU_SETUP;
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dev_dbg(ACRN_DBG_PROFILING, "%s: exiting cpu%d",
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__func__, get_cpu_id());
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}
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/*
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@ -106,6 +227,101 @@ static void profiling_pmi_handler(__unused unsigned int irq, __unused void *data
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/* to be implemented */
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}
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/*
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* Initialize sep state and enable PMU counters
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*/
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void profiling_start_pmu(void)
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{
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uint16_t i;
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering", __func__);
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if (in_pmu_profiling) {
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return;
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}
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for (i = 0U; i < phys_cpu_num; i++) {
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if (per_cpu(profiling_info.sep_state, i).pmu_state != PMU_SETUP) {
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pr_err("%s: invalid pmu_state %u on cpu%d",
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__func__, get_cpu_var(profiling_info.sep_state).pmu_state, i);
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return;
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}
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}
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for (i = 0U; i < phys_cpu_num; i++) {
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per_cpu(profiling_info.ipi_cmd, i) = IPI_PMU_START;
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per_cpu(profiling_info.sep_state, i).samples_logged = 0U;
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per_cpu(profiling_info.sep_state, i).samples_dropped = 0U;
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per_cpu(profiling_info.sep_state, i).valid_pmi_count = 0U;
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per_cpu(profiling_info.sep_state, i).total_pmi_count = 0U;
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per_cpu(profiling_info.sep_state, i).total_vmexit_count = 0U;
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per_cpu(profiling_info.sep_state, i).frozen_well = 0U;
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per_cpu(profiling_info.sep_state, i).frozen_delayed = 0U;
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per_cpu(profiling_info.sep_state, i).nofrozen_pmi = 0U;
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per_cpu(profiling_info.sep_state, i).pmu_state = PMU_RUNNING;
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}
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smp_call_function(pcpu_active_bitmap, profiling_ipi_handler, NULL);
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in_pmu_profiling = true;
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dev_dbg(ACRN_DBG_PROFILING, "%s: done", __func__);
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}
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/*
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* Reset sep state and Disable all the PMU counters
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*/
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void profiling_stop_pmu(void)
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{
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uint16_t i;
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering", __func__);
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if (!in_pmu_profiling) {
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return;
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}
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for (i = 0U; i < phys_cpu_num; i++) {
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per_cpu(profiling_info.ipi_cmd, i) = IPI_PMU_STOP;
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if (per_cpu(profiling_info.sep_state, i).pmu_state == PMU_RUNNING) {
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per_cpu(profiling_info.sep_state, i).pmu_state = PMU_SETUP;
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}
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: pmi_cnt[%d] = total:%u valid=%u, vmexit_cnt=%u",
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__func__, i, per_cpu(profiling_info.sep_state, i).total_pmi_count,
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per_cpu(profiling_info.sep_state, i).valid_pmi_count,
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per_cpu(profiling_info.sep_state, i).total_vmexit_count);
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: cpu%d frozen well:%u frozen delayed=%u, nofrozen_pmi=%u",
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__func__, i, per_cpu(profiling_info.sep_state, i).frozen_well,
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per_cpu(profiling_info.sep_state, i).frozen_delayed,
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per_cpu(profiling_info.sep_state, i).nofrozen_pmi);
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: cpu%d samples captured:%u samples dropped=%u",
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__func__, i, per_cpu(profiling_info.sep_state, i).samples_logged,
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per_cpu(profiling_info.sep_state, i).samples_dropped);
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per_cpu(profiling_info.sep_state, i).samples_logged = 0U;
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per_cpu(profiling_info.sep_state, i).samples_dropped = 0U;
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per_cpu(profiling_info.sep_state, i).valid_pmi_count = 0U;
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per_cpu(profiling_info.sep_state, i).total_pmi_count = 0U;
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per_cpu(profiling_info.sep_state, i).total_vmexit_count = 0U;
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per_cpu(profiling_info.sep_state, i).frozen_well = 0U;
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per_cpu(profiling_info.sep_state, i).frozen_delayed = 0U;
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per_cpu(profiling_info.sep_state, i).nofrozen_pmi = 0U;
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}
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smp_call_function(pcpu_active_bitmap, profiling_ipi_handler, NULL);
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in_pmu_profiling = false;
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dev_dbg(ACRN_DBG_PROFILING, "%s: done.", __func__);
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}
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/*
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* Performs MSR operations on all the CPU's
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*/
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@ -259,9 +475,115 @@ int32_t profiling_get_control(struct vm *vm, uint64_t addr)
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/*
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* Update the profiling type based on control switch
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*/
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int32_t profiling_set_control(__unused struct vm *vm, __unused uint64_t addr)
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int32_t profiling_set_control(struct vm *vm, uint64_t addr)
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{
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/* to be implemented */
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uint64_t old_switch;
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uint64_t new_switch;
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uint64_t i;
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struct profiling_control prof_control;
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(void)memset((void *)&prof_control, 0U, sizeof(prof_control));
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering", __func__);
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if (copy_from_gpa(vm, &prof_control, addr, sizeof(prof_control)) != 0) {
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pr_err("%s: Unable to copy addr from vm\n", __func__);
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return -EINVAL;
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}
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switch (prof_control.collector_id) {
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case COLLECT_PROFILE_DATA:
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old_switch = sep_collection_switch;
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new_switch = prof_control.switches;
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sep_collection_switch = prof_control.switches;
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dev_dbg(ACRN_DBG_PROFILING,
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" old_switch: %llu sep_collection_switch: %llu!",
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old_switch, sep_collection_switch);
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for (i = 0U; i < (uint64_t)MAX_SEP_FEATURE_ID; i++) {
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if ((new_switch ^ old_switch) & (0x1U << i)) {
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switch (i) {
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case CORE_PMU_SAMPLING:
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case CORE_PMU_COUNTING:
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if (new_switch & (0x1U << i)) {
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profiling_start_pmu();
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} else {
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profiling_stop_pmu();
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}
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break;
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case LBR_PMU_SAMPLING:
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break;
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case VM_SWITCH_TRACING:
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break;
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default:
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: feature not supported %u",
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__func__, i);
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break;
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}
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}
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}
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break;
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case COLLECT_POWER_DATA:
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: configuring socwatch", __func__);
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socwatch_collection_switch = prof_control.switches;
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dev_dbg(ACRN_DBG_PROFILING,
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"socwatch_collection_switch: %llu!",
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socwatch_collection_switch);
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if (socwatch_collection_switch != 0UL) {
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: socwatch start collection invoked!", __func__);
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for (i = 0U; i < (uint64_t)MAX_SOCWATCH_FEATURE_ID; i++) {
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if (socwatch_collection_switch & (0x1U << i)) {
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switch (i) {
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case SOCWATCH_COMMAND:
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break;
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case SOCWATCH_VM_SWITCH_TRACING:
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: socwatch vm-switch feature requested!",
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__func__);
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break;
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default:
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: socwatch feature not supported %u",
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__func__, i);
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break;
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}
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}
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}
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for (i = 0U; i < phys_cpu_num; i++) {
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per_cpu(profiling_info.soc_state, i)
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= SW_RUNNING;
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}
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} else { /* stop socwatch collection */
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: socwatch stop collection invoked or collection switch not set!",
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__func__);
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for (i = 0U; i < phys_cpu_num; i++) {
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per_cpu(profiling_info.soc_state, i)
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= SW_STOPPED;
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}
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}
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break;
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default:
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pr_err("%s: unknown collector %d",
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__func__, prof_control.collector_id);
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break;
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}
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if (copy_to_gpa(vm, &prof_control, addr, sizeof(prof_control)) != 0) {
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pr_err("%s: Unable to copy addr to vm\n", __func__);
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return -EINVAL;
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}
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dev_dbg(ACRN_DBG_PROFILING, "%s: exiting", __func__);
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return 0;
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}
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@ -505,6 +827,12 @@ void profiling_setup(void)
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profiling_pmi_irq = (uint32_t)retval;
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}
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per_cpu(profiling_info.sep_state, cpu).valid_pmi_count = 0U;
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per_cpu(profiling_info.sep_state, cpu).total_pmi_count = 0U;
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per_cpu(profiling_info.sep_state, cpu).total_vmexit_count = 0U;
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per_cpu(profiling_info.sep_state, cpu).pmu_state = PMU_INITIALIZED;
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per_cpu(profiling_info.sep_state, cpu).vmexit_msr_cnt = 0;
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msr_write(MSR_IA32_EXT_APIC_LVT_PMI,
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VECTOR_PMI | LVT_PERFCTR_BIT_MASK);
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@ -11,6 +11,7 @@
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#define MAX_NR_VCPUS 8
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#define MAX_NR_VMS 6
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#define MAX_MSR_LIST_NUM 15U
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#define MAX_GROUP_NUM 1U
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@ -51,6 +52,18 @@ typedef enum PROFILING_SEP_FEATURE {
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MAX_SEP_FEATURE_ID
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} profiling_sep_feature;
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typedef enum SOCWATCH_STATE {
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SW_SETUP = 0,
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SW_RUNNING,
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SW_STOPPED
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} socwatch_state;
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typedef enum PROFILING_SOCWATCH_FEATURE {
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SOCWATCH_COMMAND = 0,
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SOCWATCH_VM_SWITCH_TRACING,
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MAX_SOCWATCH_FEATURE_ID
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} profiling_socwatch_feature;
|
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|
||||
struct profiling_version_info {
|
||||
int32_t major;
|
||||
int32_t minor;
|
||||
@ -120,6 +133,12 @@ struct profiling_vmsw_config {
|
||||
struct profiling_msr_op exit_list[MAX_MSR_LIST_NUM];
|
||||
};
|
||||
|
||||
struct vmexit_msr {
|
||||
uint32_t msr_idx;
|
||||
uint32_t reserved;
|
||||
uint64_t msr_data;
|
||||
};
|
||||
|
||||
struct sep_state {
|
||||
sep_pmu_state pmu_state;
|
||||
|
||||
@ -146,7 +165,20 @@ struct sep_state {
|
||||
struct profiling_msr_op
|
||||
vmsw_exit_msr_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
|
||||
|
||||
/* sep handling statistics */
|
||||
uint32_t samples_logged;
|
||||
uint32_t samples_dropped;
|
||||
uint32_t valid_pmi_count;
|
||||
uint32_t total_pmi_count;
|
||||
uint32_t total_vmexit_count;
|
||||
uint32_t frozen_well;
|
||||
uint32_t frozen_delayed;
|
||||
uint32_t nofrozen_pmi;
|
||||
|
||||
struct vmexit_msr vmexit_msr_list[MAX_MSR_LIST_NUM];
|
||||
int32_t vmexit_msr_cnt;
|
||||
uint64_t guest_debugctl_value;
|
||||
uint64_t saved_debugctl_value;
|
||||
} __aligned(8);
|
||||
|
||||
/*
|
||||
@ -155,6 +187,7 @@ struct sep_state {
|
||||
struct profiling_info_wrapper {
|
||||
struct sep_state sep_state;
|
||||
ipi_commands ipi_cmd;
|
||||
socwatch_state soc_state;
|
||||
} __aligned(8);
|
||||
|
||||
int32_t profiling_get_version_info(struct vm *vm, uint64_t addr);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user