mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-24 22:42:53 +00:00
HV:Added support to configure PMI and VM switch info
This patch provides interface to configure(setup before actual
collection) PMI and VM switch tracing information.
profiling_config_pmi:
Receives required information for configuring PMI from guest,
populates the information info per_cpu region and SMP calls profiling_initilaize_pmi
profiling_initialize_pmi:
Configure the PMU's for sep/socwatch profiling.
Initial write of PMU registers.
Walk through the entries and write the value of the register accordingly.
profiling_config_vmsw:
Receives required information for configuring
VMswitch from guest, Configure for VM-switch data on all cpus
profiling_initialize_vmsw: initializes VMSwitch tracing
Tracked-On: projectacrn#1409
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Manisha <manisha.chinthapally@intel.com>
This commit is contained in:
Chinthapally, Manisha
wenlingz
parent
df549096f2
commit
898b9c8d4a
@ -8,6 +8,7 @@
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#include <hypervisor.h>
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#define ACRN_DBG_PROFILING 5U
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#define ACRN_ERR_PROFILING 3U
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#define MAJOR_VERSION 1
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#define MINOR_VERSION 0
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@ -20,15 +21,57 @@ static uint32_t profiling_pmi_irq = IRQ_INVALID;
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static void profiling_initialize_vmsw(void)
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{
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/* to be implemented */
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering cpu%d",
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__func__, get_cpu_id());
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dev_dbg(ACRN_DBG_PROFILING, "%s: exiting cpu%d",
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__func__, get_cpu_id());
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}
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/*
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* Configure the PMU's for sep/socwatch profiling.
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* Initial write of PMU registers.
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* Walk through the entries and write the value of the register accordingly.
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* Note: current_group is always set to 0, only 1 group is supported.
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*/
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static void profiling_initialize_pmi(void)
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{
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/* to be implemented */
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uint32_t i, group_id;
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struct profiling_msr_op *msrop = NULL;
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struct sep_state *ss = &get_cpu_var(profiling_info.sep_state);
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering cpu%d",
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__func__, get_cpu_id());
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if (ss == NULL) {
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dev_dbg(ACRN_ERR_PROFILING, "%s: exiting cpu%d",
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__func__, get_cpu_id());
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return;
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}
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group_id = ss->current_pmi_group_id = 0U;
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for (i = 0U; i < MAX_MSR_LIST_NUM; i++) {
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msrop = &(ss->pmi_initial_msr_list[group_id][i]);
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if (msrop != NULL) {
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if (msrop->msr_id == (uint32_t)-1) {
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break;
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}
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if (msrop->msr_id == MSR_IA32_DEBUGCTL) {
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ss->guest_debugctl_value = msrop->value;
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}
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if (msrop->msr_op_type == (uint8_t)MSR_OP_WRITE) {
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msr_write(msrop->msr_id, msrop->value);
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dev_dbg(ACRN_DBG_PROFILING,
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"%s: MSRWRITE cpu%d, msr_id=0x%x, msr_val=0x%llx",
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__func__, get_cpu_id(), msrop->msr_id, msrop->value);
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}
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}
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}
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ss->pmu_state = PMU_SETUP;
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dev_dbg(ACRN_DBG_PROFILING, "%s: exiting cpu%d",
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__func__, get_cpu_id());
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}
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/*
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@ -225,23 +268,142 @@ int32_t profiling_set_control(__unused struct vm *vm, __unused uint64_t addr)
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/*
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* Configure PMI on all cpus
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*/
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int32_t profiling_configure_pmi(__unused struct vm *vm, __unused uint64_t addr)
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int32_t profiling_configure_pmi(struct vm *vm, uint64_t addr)
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{
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/* to be implemented
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* call to smp_call_function profiling_ipi_handler
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*/
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uint16_t i;
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struct profiling_pmi_config pmi_config;
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(void)memset((void *)&pmi_config, 0U, sizeof(pmi_config));
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering", __func__);
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if (copy_from_gpa(vm, &pmi_config, addr, sizeof(pmi_config)) != 0) {
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pr_err("%s: Unable to copy addr from vm\n", __func__);
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return -EINVAL;
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}
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for (i = 0U; i < phys_cpu_num; i++) {
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if (!((per_cpu(profiling_info.sep_state, i).pmu_state ==
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PMU_INITIALIZED) ||
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(per_cpu(profiling_info.sep_state, i).pmu_state ==
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PMU_SETUP))) {
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pr_err("%s: invalid pmu_state %u on cpu%d",
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__func__, per_cpu(profiling_info.sep_state, i).pmu_state, i);
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return -EINVAL;
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}
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}
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if (pmi_config.num_groups == 0U ||
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pmi_config.num_groups > MAX_GROUP_NUM) {
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pr_err("%s: invalid num_groups %u",
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__func__, pmi_config.num_groups);
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return -EINVAL;
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}
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for (i = 0U; i < phys_cpu_num; i++) {
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per_cpu(profiling_info.ipi_cmd, i) = IPI_PMU_CONFIG;
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per_cpu(profiling_info.sep_state, i).num_pmi_groups
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= pmi_config.num_groups;
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(void)memcpy_s((void *)per_cpu(profiling_info.sep_state, i).pmi_initial_msr_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM*MAX_GROUP_NUM,
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(void *)pmi_config.initial_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM*MAX_GROUP_NUM);
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(void)memcpy_s((void *)per_cpu(profiling_info.sep_state, i).pmi_start_msr_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM*MAX_GROUP_NUM,
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(void *)pmi_config.start_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM*MAX_GROUP_NUM);
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(void)memcpy_s((void *)per_cpu(profiling_info.sep_state, i).pmi_stop_msr_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM*MAX_GROUP_NUM,
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(void *)pmi_config.stop_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM*MAX_GROUP_NUM);
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(void)memcpy_s((void *)per_cpu(profiling_info.sep_state, i).pmi_entry_msr_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM*MAX_GROUP_NUM,
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(void *)pmi_config.entry_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM*MAX_GROUP_NUM);
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(void)memcpy_s((void *)per_cpu(profiling_info.sep_state, i).pmi_exit_msr_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM*MAX_GROUP_NUM,
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(void *)pmi_config.exit_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM*MAX_GROUP_NUM);
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}
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smp_call_function(pcpu_active_bitmap, profiling_ipi_handler, NULL);
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if (copy_to_gpa(vm, &pmi_config, addr, sizeof(pmi_config)) != 0) {
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pr_err("%s: Unable to copy addr to vm\n", __func__);
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return -EINVAL;
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}
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dev_dbg(ACRN_DBG_PROFILING, "%s: exiting", __func__);
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return 0;
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}
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/*
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* Configure for VM-switch data on all cpus
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*/
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int32_t profiling_configure_vmsw(__unused struct vm *vm, __unused uint64_t addr)
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int32_t profiling_configure_vmsw(struct vm *vm, uint64_t addr)
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{
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/* to be implemented
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* call to smp_call_function profiling_ipi_handler
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*/
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return 0;
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uint16_t i;
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int32_t ret = 0;
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struct profiling_vmsw_config vmsw_config;
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(void)memset((void *)&vmsw_config, 0U, sizeof(vmsw_config));
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dev_dbg(ACRN_DBG_PROFILING, "%s: entering", __func__);
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if (copy_from_gpa(vm, &vmsw_config, addr, sizeof(vmsw_config)) != 0) {
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pr_err("%s: Unable to copy addr from vm\n", __func__);
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return -EINVAL;
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}
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switch (vmsw_config.collector_id) {
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case COLLECT_PROFILE_DATA:
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for (i = 0U; i < phys_cpu_num; i++) {
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per_cpu(profiling_info.ipi_cmd, i) = IPI_VMSW_CONFIG;
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(void)memcpy_s(
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(void *)per_cpu(profiling_info.sep_state, i).vmsw_initial_msr_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM,
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(void *)vmsw_config.initial_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM);
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(void)memcpy_s(
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(void *)per_cpu(profiling_info.sep_state, i).vmsw_entry_msr_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM,
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(void *)vmsw_config.entry_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM);
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(void)memcpy_s(
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(void *)per_cpu(profiling_info.sep_state, i).vmsw_exit_msr_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM,
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(void *)vmsw_config.exit_list,
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sizeof(struct profiling_msr_op)*MAX_MSR_LIST_NUM);
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}
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smp_call_function(pcpu_active_bitmap, profiling_ipi_handler, NULL);
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break;
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case COLLECT_POWER_DATA:
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break;
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default:
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pr_err("%s: unknown collector %d",
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__func__, vmsw_config.collector_id);
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ret = -EINVAL;
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break;
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}
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if (copy_to_gpa(vm, &vmsw_config, addr, sizeof(vmsw_config)) != 0) {
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pr_err("%s: Unable to copy addr to vm\n", __func__);
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return -EINVAL;
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}
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dev_dbg(ACRN_DBG_PROFILING, "%s: exiting", __func__);
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return ret;
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}
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/*
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@ -349,4 +511,4 @@ void profiling_setup(void)
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dev_dbg(ACRN_DBG_PROFILING, "%s: exiting", __func__);
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}
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#endif
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#endif
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@ -11,10 +11,19 @@
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#define MAX_NR_VCPUS 8
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#define MAX_NR_VMS 6
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#define MAX_MSR_LIST_NUM 15U
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#define MAX_GROUP_NUM 1U
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#define COLLECT_PROFILE_DATA 0
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#define COLLECT_POWER_DATA 1
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enum MSR_CMD_TYPE {
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MSR_OP_NONE = 0,
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MSR_OP_READ,
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MSR_OP_WRITE,
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MSR_OP_READ_CLEAR
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};
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typedef enum IPI_COMMANDS {
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IPI_MSR_OP = 0,
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IPI_PMU_CONFIG,
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@ -24,6 +33,14 @@ typedef enum IPI_COMMANDS {
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IPI_UNKNOWN,
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} ipi_commands;
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typedef enum SEP_PMU_STATE {
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PMU_INITIALIZED = 0,
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PMU_SETUP,
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PMU_RUNNING,
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PMU_UNINITIALIZED,
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PMU_UNKNOWN
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} sep_pmu_state;
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typedef enum PROFILING_SEP_FEATURE {
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CORE_PMU_SAMPLING = 0,
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CORE_PMU_COUNTING,
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@ -75,12 +92,70 @@ struct profiling_vm_info_list {
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struct profiling_vm_info vm_list[MAX_NR_VMS];
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};
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struct profiling_msr_op {
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/* value to write or location to write into */
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uint64_t value;
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/* MSR address to read/write; last entry will have value of -1 */
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uint32_t msr_id;
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/* parameter; usage depends on operation */
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uint16_t param;
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uint8_t msr_op_type;
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uint8_t reg_type;
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};
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struct profiling_pmi_config {
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uint32_t num_groups;
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uint32_t trigger_count;
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struct profiling_msr_op initial_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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struct profiling_msr_op start_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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struct profiling_msr_op stop_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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struct profiling_msr_op entry_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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struct profiling_msr_op exit_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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};
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struct profiling_vmsw_config {
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int32_t collector_id;
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struct profiling_msr_op initial_list[MAX_MSR_LIST_NUM];
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struct profiling_msr_op entry_list[MAX_MSR_LIST_NUM];
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struct profiling_msr_op exit_list[MAX_MSR_LIST_NUM];
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};
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struct sep_state {
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sep_pmu_state pmu_state;
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uint32_t current_pmi_group_id;
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uint32_t num_pmi_groups;
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struct profiling_msr_op
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pmi_initial_msr_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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struct profiling_msr_op
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pmi_start_msr_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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struct profiling_msr_op
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pmi_stop_msr_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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struct profiling_msr_op
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pmi_entry_msr_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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struct profiling_msr_op
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pmi_exit_msr_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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uint32_t current_vmsw_group_id;
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uint32_t num_msw_groups;
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struct profiling_msr_op
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vmsw_initial_msr_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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struct profiling_msr_op
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vmsw_entry_msr_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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struct profiling_msr_op
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vmsw_exit_msr_list[MAX_GROUP_NUM][MAX_MSR_LIST_NUM];
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uint64_t guest_debugctl_value;
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} __aligned(8);
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/*
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* Wrapper containing SEP sampling/profiling related data structures
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*/
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struct profiling_info_wrapper {
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struct sep_state sep_state;
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ipi_commands ipi_cmd;
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};
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} __aligned(8);
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int32_t profiling_get_version_info(struct vm *vm, uint64_t addr);
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int32_t profiling_get_pcpu_id(struct vm *vm, uint64_t addr);
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