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https://github.com/projectacrn/acrn-hypervisor.git
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HV: Adding passthru vdev device support for partition hypervisor
V4: - Renamed members for struct pcibar and changed code accordingly V3: - Do not use ASSERT - Use EPT_XX defines when claling ept_mr_add - Report 64-bit MMIO physical bar to UOS as 32-bit virtual bar (assume bar size is always less than 4GB), which removed quite some of 64-bit bar handling code Reviewed-by: Anthony Xu <anthony.xu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
dongshen
lijinxia
parent
5f3ea06feb
commit
181de19cba
@ -78,4 +78,76 @@
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void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
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uint32_t offset, uint32_t bytes, uint32_t *val);
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static inline uint8_t
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pci_vdev_read_cfg_u8(struct pci_vdev *vdev, uint32_t offset)
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{
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return (*(uint8_t *)(&vdev->cfgdata[0] + offset));
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}
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static inline uint16_t pci_vdev_read_cfg_u16(struct pci_vdev *vdev,
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uint32_t offset)
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{
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return (*(uint16_t *)(&vdev->cfgdata[0] + offset));
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}
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static inline uint32_t pci_vdev_read_cfg_u32(struct pci_vdev *vdev,
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uint32_t offset)
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{
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return (*(uint32_t *)(&vdev->cfgdata[0] + offset));
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}
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static inline void
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pci_vdev_write_cfg_u8(struct pci_vdev *vdev, uint32_t offset, uint8_t val)
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{
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*(uint8_t *)(vdev->cfgdata + offset) = val;
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}
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static inline void
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pci_vdev_write_cfg_u16(struct pci_vdev *vdev, uint32_t offset, uint16_t val)
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{
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*(uint16_t *)(vdev->cfgdata + offset) = val;
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}
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static inline void
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pci_vdev_write_cfg_u32(struct pci_vdev *vdev, uint32_t offset, uint32_t val)
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{
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*(uint32_t *)(vdev->cfgdata + offset) = val;
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}
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static inline uint32_t pci_vdev_read_cfg(struct pci_vdev *vdev,
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uint32_t offset, uint32_t bytes)
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{
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uint32_t val;
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switch (bytes) {
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case 1U:
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val = pci_vdev_read_cfg_u8(vdev, offset);
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break;
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case 2U:
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val = pci_vdev_read_cfg_u16(vdev, offset);
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break;
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default:
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val = pci_vdev_read_cfg_u32(vdev, offset);
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break;
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}
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return val;
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}
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static inline void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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{
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switch (bytes) {
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case 1U:
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pci_vdev_write_cfg_u8(vdev, offset, val);
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break;
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case 2U:
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pci_vdev_write_cfg_u16(vdev, offset, val);
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break;
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default:
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pci_vdev_write_cfg_u32(vdev, offset, val);
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break;
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}
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}
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#endif /* PCI_PRIV_H_ */
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292
hypervisor/dm/vpci/pci_pt.c
Normal file
292
hypervisor/dm/vpci/pci_pt.c
Normal file
@ -0,0 +1,292 @@
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/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* Passthrough PCI device related operations */
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#include <hypervisor.h>
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#include <hv_lib.h>
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#include <acrn_common.h>
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#include <hv_arch.h>
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#include <hv_debug.h>
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#include "pci_priv.h"
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static spinlock_t pci_device_lock = { .head = 0, .tail = 0 };
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static uint32_t pci_pdev_calc_address(uint16_t bdf, uint32_t offset)
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{
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uint32_t addr = bdf;
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addr <<= 8;
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addr |= (offset | PCI_CFG_ENABLE);
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return addr;
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}
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static uint32_t pci_pdev_read_cfg(struct pci_pdev *pdev,
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uint32_t offset, uint32_t bytes)
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{
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uint32_t addr;
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uint32_t val;
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spinlock_obtain(&pci_device_lock);
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addr = pci_pdev_calc_address(pdev->bdf, offset);
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/* Write address to ADDRESS register */
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pio_write(addr, PCI_CONFIG_ADDR, 4);
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/* Read result from DATA register */
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switch (bytes) {
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case 1U:
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val = pio_read8(PCI_CONFIG_DATA + (offset & 3U));
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break;
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case 2U:
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val = pio_read16(PCI_CONFIG_DATA + (offset & 2U));
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break;
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default:
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val = pio_read32(PCI_CONFIG_DATA);
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break;
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}
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spinlock_release(&pci_device_lock);
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return val;
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}
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static void pci_pdev_write_cfg(struct pci_pdev *pdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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{
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uint32_t addr;
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spinlock_obtain(&pci_device_lock);
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addr = pci_pdev_calc_address(pdev->bdf, offset);
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/* Write address to ADDRESS register */
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pio_write(addr, PCI_CONFIG_ADDR, 4);
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/* Write value to DATA register */
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switch (bytes) {
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case 1U:
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pio_write8(val, PCI_CONFIG_DATA + (offset & 3U));
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break;
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case 2U:
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pio_write16(val, PCI_CONFIG_DATA + (offset & 2U));
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break;
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default:
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pio_write32(val, PCI_CONFIG_DATA);
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break;
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}
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spinlock_release(&pci_device_lock);
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}
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static int vdev_pt_init_validate(struct pci_vdev *vdev)
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{
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uint32_t idx;
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for (idx = 0; idx < (uint32_t)PCI_BAR_COUNT; idx++) {
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if (vdev->bar[idx].type != PCIM_BAR_MEM_32) {
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return -EINVAL;
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}
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}
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return 0;
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}
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static void vdev_pt_init_bar_registers(struct pci_vdev *vdev)
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{
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uint32_t idx;
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for (idx = 0; idx < (uint32_t)PCI_BAR_COUNT; idx++) {
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/* Initialize the BAR register in config space */
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pci_vdev_write_cfg_u32(vdev, PCIR_BAR(idx),
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PCI_BAR(vdev->bar[idx].base, vdev->bar[idx].type));
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}
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}
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static int vdev_pt_init(struct pci_vdev *vdev)
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{
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int ret;
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struct vm *vm = vdev->vpci->vm;
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ret = vdev_pt_init_validate(vdev);
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if (ret != 0) {
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pr_err("virtual bar can only be of type PCIM_BAR_MEM_32!");
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return ret;
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}
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/* Create an iommu domain for target VM if not created */
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if (vm->iommu == NULL) {
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if (vm->arch_vm.nworld_eptp == 0UL) {
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vm->arch_vm.nworld_eptp = alloc_paging_struct();
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}
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vm->iommu = create_iommu_domain(vm->vm_id,
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HVA2HPA(vm->arch_vm.nworld_eptp), 48U);
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}
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ret = assign_iommu_device(vm->iommu,
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PCI_BUS(vdev->pdev.bdf), LOBYTE(vdev->pdev.bdf));
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vdev_pt_init_bar_registers(vdev);
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return ret;
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}
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static int vdev_pt_deinit(struct pci_vdev *vdev)
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{
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int ret;
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struct vm *vm = vdev->vpci->vm;
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ret = unassign_iommu_device(vm->iommu, PCI_BUS(vdev->pdev.bdf),
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LOBYTE(vdev->pdev.bdf));
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return ret;
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}
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static int bar_access(uint32_t coff)
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{
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if ((coff >= PCIR_BAR(0U)) && (coff < PCIR_BAR(PCI_BAR_COUNT))) {
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return 1;
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} else {
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return 0;
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}
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}
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static int vdev_pt_cfgread(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t *val)
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{
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/* Assumption: access needed to be aligned on 1/2/4 bytes */
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if ((offset & (bytes - 1)) != 0U) {
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*val = 0xffffffffU;
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return -EINVAL;
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}
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/* PCI BARs is emulated */
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if (bar_access(offset)) {
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*val = pci_vdev_read_cfg(vdev, offset, bytes);
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} else {
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*val = pci_pdev_read_cfg(&vdev->pdev, offset, bytes);
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}
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return 0;
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}
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static int vdev_pt_remap_bar(struct pci_vdev *vdev, uint32_t idx,
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uint32_t new_base)
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{
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int error = 0;
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struct vm *vm = vdev->vpci->vm;
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if (vdev->bar[idx].base != 0) {
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error = ept_mr_del(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
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vdev->bar[idx].base,
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vdev->bar[idx].size);
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if (error) {
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return error;
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}
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}
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if (new_base != 0U) {
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/* Map the physical BAR in the guest MMIO space */
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error = ept_mr_add(vm,
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vdev->pdev.bar[idx].base, /* HPA */
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new_base, /*GPA*/
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vdev->bar[idx].size,
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EPT_WR | EPT_RD | EPT_UNCACHED);
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if (error) {
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return error;
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}
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}
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return error;
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}
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static uint32_t memen(struct pci_vdev *vdev)
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{
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return pci_pdev_read_cfg(&vdev->pdev, PCIR_COMMAND, 2)
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& PCIM_CMD_MEMEN;
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}
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static void vdev_pt_cfgwrite_bar(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t new_bar_uos)
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{
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uint32_t idx;
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uint32_t new_bar, mask;
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bool bar_update_normal = 1;
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bool do_map;
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int error;
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idx = (offset - PCIR_BAR(0U)) / 4U;
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mask = ~(vdev->bar[idx].size - 1U);
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bar_update_normal = (new_bar_uos != (uint32_t)~0U);
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new_bar = new_bar_uos & mask;
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new_bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
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if (PCI_BAR_BASE(new_bar) == vdev->bar[idx].base) {
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return;
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}
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do_map = (memen(vdev)) && bar_update_normal;
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if (do_map) {
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error = vdev_pt_remap_bar(vdev, idx, PCI_BAR_BASE(new_bar));
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if (error) {
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pr_err("vdev_pt_remap_bar failed: %d", idx);
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}
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}
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pci_vdev_write_cfg_u32(vdev, offset, new_bar);
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vdev->bar[idx].base = PCI_BAR_BASE(new_bar);
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}
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static int vdev_pt_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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{
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/* Assumption: access needed to be aligned on 1/2/4 bytes */
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if ((offset & (bytes - 1)) != 0U) {
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return -EINVAL;
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}
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/* PCI BARs are emulated */
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if (bar_access(offset)) {
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vdev_pt_cfgwrite_bar(vdev, offset, bytes, val);
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} else {
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/* Write directly to physical device's config space */
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pci_pdev_write_cfg(&vdev->pdev, offset, bytes, val);
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}
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return 0;
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}
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struct pci_vdev_ops pci_ops_vdev_pt = {
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.init = vdev_pt_init,
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.deinit = vdev_pt_deinit,
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.cfgwrite = vdev_pt_cfgwrite,
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.cfgread = vdev_pt_cfgread,
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};
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@ -92,6 +92,8 @@ struct vpci {
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struct pci_addr_info addr_info;
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};
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extern struct pci_vdev_ops pci_ops_vdev_pt;
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void vpci_init(struct vm *vm);
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void vpci_cleanup(struct vm *vm);
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@ -19,7 +19,7 @@ static struct vpci_vdev_array vpci_vdev_array1 = {
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{/*vdev 1*/
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.vbdf = PCI_BDF(0x00U, 0x01U, 0x00U),
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.ops = NULL,
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.ops = &pci_ops_vdev_pt,
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.bar = {
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[0] = {
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.base = 0UL,
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@ -65,7 +65,7 @@ static struct vpci_vdev_array vpci_vdev_array2 = {
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{/*vdev 1*/
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.vbdf = PCI_BDF(0x00U, 0x01U, 0x00U),
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.ops = NULL,
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.ops = &pci_ops_vdev_pt,
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.bar = {
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[0] = {
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.base = 0UL,
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