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https://github.com/projectacrn/acrn-hypervisor.git
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hv: virq: refine pending event inject coding style
In order to combine vlapic_apicv_inject_pir and vcpu_inject_vlapic_int. Tracked-On: #1842 Signed-off-by: Li, Fei1 <fei1.li@intel.com>
This commit is contained in:
Li, Fei1
wenlingz
parent
fde2c07c0a
commit
1db8123c2d
@ -111,17 +111,22 @@ static bool vcpu_pending_request(struct acrn_vcpu *vcpu)
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{
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struct acrn_vlapic *vlapic;
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uint32_t vector = 0U;
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bool pending = false;
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/* Query vLapic to get vector to inject */
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vlapic = vcpu_vlapic(vcpu);
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if (!is_apicv_advanced_feature_supported()) {
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/* Query vLapic to get vector to inject */
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vlapic = vcpu_vlapic(vcpu);
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/* check and raise request if we have a deliverable irq in LAPIC IRR */
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if (vlapic_find_deliverable_intr(vlapic, &vector)) {
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/* we have pending IRR */
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vcpu_make_request(vcpu, ACRN_REQUEST_EVENT);
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/* check and raise request if we have a deliverable irq in LAPIC IRR */
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if (vlapic_find_deliverable_intr(vlapic, &vector)) {
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/* we have pending IRR */
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vcpu_make_request(vcpu, ACRN_REQUEST_EVENT);
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}
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pending = vcpu->arch.pending_req != 0UL;
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}
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return vcpu->arch.pending_req != 0UL;
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return pending;
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}
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void vcpu_make_request(struct acrn_vcpu *vcpu, uint16_t eventid)
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@ -144,15 +149,14 @@ void vcpu_make_request(struct acrn_vcpu *vcpu, uint16_t eventid)
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/*
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* This function is only for case that APICv/VID is not supported.
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*
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* @retval 1 when INT is injected to guest.
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* @retval 0 when there is no eligible pending vector.
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* @retval -1 when there is a error.
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* @retval true when INT is injected to guest.
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* @retval false when there is no eligible pending vector.
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*/
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static int32_t vcpu_inject_vlapic_int(struct acrn_vcpu *vcpu)
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static bool vcpu_inject_vlapic_int(struct acrn_vcpu *vcpu)
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{
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struct acrn_vlapic *vlapic = vcpu_vlapic(vcpu);
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uint32_t vector = 0U;
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int32_t ret = 0;
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bool injected = false;
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if (vlapic_find_deliverable_intr(vlapic, &vector)) {
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/*
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@ -161,34 +165,26 @@ static int32_t vcpu_inject_vlapic_int(struct acrn_vcpu *vcpu)
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* - maskable interrupt vectors [16,255] can be delivered
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* through the local APIC.
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*/
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if (!((vector >= 16U) && (vector <= 255U))) {
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dev_dbg(ACRN_DBG_INTR, "invalid vector %d from local APIC", vector);
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ret = -1;
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} else {
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exec_vmwrite32(VMX_ENTRY_INT_INFO_FIELD, VMX_INT_INFO_VALID |
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(vector & 0xFFU));
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vlapic_get_deliverable_intr(vlapic, vector);
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ret = 1;
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}
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exec_vmwrite32(VMX_ENTRY_INT_INFO_FIELD, VMX_INT_INFO_VALID | vector);
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vlapic_get_deliverable_intr(vlapic, vector);
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injected = true;
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}
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vlapic_update_tpr_threshold(vlapic);
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return ret;
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return injected;
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}
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/*
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* @retval 1 when INT is injected to guest.
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* @retval 0 when otherwise
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* @retval true when INT is injected to guest.
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* @retval false when otherwise
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*/
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static int32_t vcpu_do_pending_extint(const struct acrn_vcpu *vcpu)
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static bool vcpu_do_pending_extint(const struct acrn_vcpu *vcpu)
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{
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struct acrn_vm *vm;
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struct acrn_vcpu *primary;
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uint32_t vector;
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int32_t ret = 0;
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bool ret = false;
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vm = vcpu->vm;
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@ -205,7 +201,7 @@ static int32_t vcpu_do_pending_extint(const struct acrn_vcpu *vcpu)
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VMX_INT_INFO_VALID |
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(vector & 0xFFU));
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vpic_intr_accepted(vcpu->vm, vector);
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ret = 1;
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ret = true;
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}
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}
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@ -300,35 +296,31 @@ static void vcpu_inject_exception(struct acrn_vcpu *vcpu, uint32_t vector)
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}
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}
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static int32_t vcpu_inject_hi_exception(struct acrn_vcpu *vcpu)
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static bool vcpu_inject_hi_exception(struct acrn_vcpu *vcpu)
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{
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bool injected = false;
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uint32_t vector = vcpu->arch.exception_info.exception;
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int32_t ret;
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if ((vector == IDT_MC) || (vector == IDT_BP) || (vector == IDT_DB)) {
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vcpu_inject_exception(vcpu, vector);
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ret = 1;
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} else {
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ret = 0;
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injected = true;
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}
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return ret;
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return injected;
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}
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static int32_t vcpu_inject_lo_exception(struct acrn_vcpu *vcpu)
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static bool vcpu_inject_lo_exception(struct acrn_vcpu *vcpu)
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{
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uint32_t vector = vcpu->arch.exception_info.exception;
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int32_t ret;
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bool injected = false;
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/* high priority exception already be injected */
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if (vector <= NR_MAX_VECTOR) {
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vcpu_inject_exception(vcpu, vector);
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ret = 1;
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} else {
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ret = 0;
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injected = true;
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}
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return ret;
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return injected;
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}
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/* Inject external interrupt to guest */
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@ -426,20 +418,20 @@ int32_t external_interrupt_vmexit_handler(struct acrn_vcpu *vcpu)
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return ret;
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}
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static inline int32_t acrn_inject_pending_vector(struct acrn_vcpu *vcpu, uint64_t *pending_req_bits);
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static inline bool acrn_inject_pending_intr(struct acrn_vcpu *vcpu,
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uint64_t *pending_req_bits, bool injected);
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int32_t acrn_handle_pending_request(struct acrn_vcpu *vcpu)
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{
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bool injected = false;
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int32_t ret = 0;
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uint32_t tmp;
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uint32_t intr_info;
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uint32_t error_code;
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struct acrn_vcpu_arch * arch = &vcpu->arch;
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struct acrn_vcpu_arch *arch = &vcpu->arch;
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uint64_t *pending_req_bits = &arch->pending_req;
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struct acrn_vlapic *vlapic;
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if (bitmap_test_and_clear_lock(ACRN_REQUEST_TRP_FAULT,
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pending_req_bits)) {
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if (bitmap_test_and_clear_lock(ACRN_REQUEST_TRP_FAULT, pending_req_bits)) {
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pr_fatal("Triple fault happen -> shutdown!");
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ret = -EFAULT;
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} else {
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@ -467,38 +459,39 @@ int32_t acrn_handle_pending_request(struct acrn_vcpu *vcpu)
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exec_vmwrite32(VMX_ENTRY_INT_INFO_FIELD, intr_info);
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arch->inject_event_pending = false;
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injected = true;
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} else {
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/* SDM Vol 3 - table 6-2, inject high priority exception before
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* maskable hardware interrupt */
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if (vcpu_inject_hi_exception(vcpu) == 0) {
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injected = vcpu_inject_hi_exception(vcpu);
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if (!injected) {
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/* inject NMI before maskable hardware interrupt */
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if (bitmap_test_and_clear_lock(ACRN_REQUEST_NMI, pending_req_bits)) {
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/* Inject NMI vector = 2 */
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exec_vmwrite32(VMX_ENTRY_INT_INFO_FIELD,
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VMX_INT_INFO_VALID | (VMX_INT_TYPE_NMI << 8U) | IDT_NMI);
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injected = true;
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} else {
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ret = acrn_inject_pending_vector(vcpu, pending_req_bits);
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/* handling pending vector injection:
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* there are many reason inject failed, we need re-inject again
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* here should take care
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* - SW exception (not maskable by IF)
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* - external interrupt, if IF clear, will keep in IDT_VEC_INFO_FIELD
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* at next vm exit?
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*/
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if ((arch->idt_vectoring_info & VMX_INT_INFO_VALID) != 0U) {
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exec_vmwrite32(VMX_ENTRY_INT_INFO_FIELD, arch->idt_vectoring_info);
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arch->idt_vectoring_info = 0U;
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injected = true;
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}
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}
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}
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}
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/*
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* From SDM Vol3 26.3.2.5:
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* Once the virtual interrupt is recognized, it will be delivered
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* in VMX non-root operation immediately after VM entry(including
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* any specified event injection) completes.
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*
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* So the hardware can handle vmcs event injection and
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* evaluation/delivery of apicv virtual interrupts in one time
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* vm-entry.
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*
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* Here to sync the pending interrupts to irr and update rvi if
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* needed. And then try to handle vmcs event injection.
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*/
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if (is_apicv_advanced_feature_supported() &&
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bitmap_test_and_clear_lock(ACRN_REQUEST_EVENT, pending_req_bits)) {
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vlapic = vcpu_vlapic(vcpu);
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vlapic_apicv_inject_pir(vlapic);
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if (!acrn_inject_pending_intr(vcpu, pending_req_bits, injected)) {
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/* if there is no eligible vector before this point */
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/* SDM Vol3 table 6-2, inject lowpri exception */
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(void)vcpu_inject_lo_exception(vcpu);
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}
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/*
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@ -516,7 +509,7 @@ int32_t acrn_handle_pending_request(struct acrn_vcpu *vcpu)
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*/
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if (arch->irq_window_enabled != 1U) {
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if (bitmap_test(ACRN_REQUEST_EXTINT, pending_req_bits) ||
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(!is_apicv_advanced_feature_supported() && vcpu_pending_request(vcpu))) {
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vcpu_pending_request(vcpu)) {
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tmp = exec_vmread32(VMX_PROC_VM_EXEC_CONTROLS);
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tmp |= VMX_PROCBASED_CTLS_IRQ_WIN;
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exec_vmwrite32(VMX_PROC_VM_EXEC_CONTROLS, tmp);
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@ -529,51 +522,45 @@ int32_t acrn_handle_pending_request(struct acrn_vcpu *vcpu)
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}
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/*
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* @retval 1 1 when INT is injected to guest.
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* @retval 0 when there is no eligible pending vector.
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* @retval -1 when there is a error.
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* @retval true 1 when INT is injected to guest.
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* @retval false when there is no eligible pending vector.
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*/
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static inline int32_t acrn_inject_pending_vector(struct acrn_vcpu *vcpu, uint64_t *pending_req_bits)
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static inline bool acrn_inject_pending_intr(struct acrn_vcpu *vcpu,
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uint64_t *pending_req_bits, bool injected)
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{
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int32_t ret = 0;
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struct acrn_vcpu_arch * arch = &vcpu->arch;
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bool ret = injected;
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struct acrn_vlapic *vlapic;
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bool guest_irq_enabled = is_guest_irq_enabled(vcpu);
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/* handling pending vector injection:
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* there are many reason inject failed, we need re-inject again
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* here should take care
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* - SW exception (not maskable by IF)
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* - external interrupt, if IF clear, will keep in IDT_VEC_INFO_FIELD
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* at next vm exit?
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*/
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if ((arch->idt_vectoring_info & VMX_INT_INFO_VALID) != 0U) {
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exec_vmwrite32(VMX_ENTRY_INT_INFO_FIELD,
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arch->idt_vectoring_info);
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} else {
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/* Guest interruptable or not */
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if (is_guest_irq_enabled(vcpu)) {
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/* Inject external interrupt first */
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if (bitmap_test_and_clear_lock(ACRN_REQUEST_EXTINT, pending_req_bits)) {
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/* has pending external interrupts */
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ret = vcpu_do_pending_extint(vcpu);
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} else {
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/*
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* For "virtual-interrupt delivery" disabled case, if
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* the virtual interrupt injection conditions are satified,
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* then inject through vmcs.
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*/
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if ((!is_apicv_advanced_feature_supported()) &&
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(bitmap_test_and_clear_lock(ACRN_REQUEST_EVENT,
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pending_req_bits))) {
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ret = vcpu_inject_vlapic_int(vcpu);
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}
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}
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if (guest_irq_enabled && (!ret)) {
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/* Inject external interrupt first */
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if (bitmap_test_and_clear_lock(ACRN_REQUEST_EXTINT, pending_req_bits)) {
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/* has pending external interrupts */
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ret = vcpu_do_pending_extint(vcpu);
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}
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}
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/* if there is no eligible vector before this point */
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if (ret == 0) {
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/* SDM Vol3 table 6-2, inject lowpri exception */
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ret = vcpu_inject_lo_exception(vcpu);
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if (bitmap_test_and_clear_lock(ACRN_REQUEST_EVENT, pending_req_bits)) {
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/*
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* From SDM Vol3 26.3.2.5:
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* Once the virtual interrupt is recognized, it will be delivered
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* in VMX non-root operation immediately after VM entry(including
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* any specified event injection) completes.
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*
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* So the hardware can handle vmcs event injection and
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* evaluation/delivery of apicv virtual interrupts in one time
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* vm-entry.
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*
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* Here to sync the pending interrupts to irr and update rvi if
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* needed. And then try to handle vmcs event injection.
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*/
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if (is_apicv_advanced_feature_supported()) {
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vlapic = vcpu_vlapic(vcpu);
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vlapic_apicv_inject_pir(vlapic);
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} else {
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if (guest_irq_enabled && (!ret)) {
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ret = vcpu_inject_vlapic_int(vcpu);
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}
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}
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}
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