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hv: tlfs: fix the incorrect vLAPIC freq MSR

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When LAPIC timer is working in oneshot or periodic mode, OS uses
initial counter register/current counter register to program
a timer. Both initial counter and current counter depend on the
LAPIC frequency. ACRN emulated vLAPIC timer based on the TSC.
vLAPIC freq is the same as TSC freq.

Tracked-On: #7876
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
This commit is contained in:
Jian Jun Chen 2022-07-19 10:02:31 +08:00 committed by acrnsi-robot
parent a3449c4893
commit 22a302599a
1 changed files with 2 additions and 2 deletions
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4
hypervisor/arch/x86/guest/hyperv.c
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@ -212,8 +212,8 @@ hyperv_rdmsr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t *rval)
*rval = get_tsc_khz() * 1000UL; *rval = get_tsc_khz() * 1000UL;
break; break;
case HV_X64_MSR_APIC_FREQUENCY: case HV_X64_MSR_APIC_FREQUENCY:
/* both KVM and XEN hardcode the APIC freq as 1GHz ... */ /* vLAPIC freq is the same as TSC freq */
*rval = 1000000000UL; *rval = get_tsc_khz() * 1000UL;
break; break;
default: default:
pr_err("hv: %s: unexpected MSR[0x%x] read", __func__, msr); pr_err("hv: %s: unexpected MSR[0x%x] read", __func__, msr);