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hv: pae: fix bug when calculate PDPT address
There are two bugs related to PDPT address calculation for PAE mode. 1. Current code doesn't ignore the "Ignored" fileds when load pdpt registers. Mask the "Ignored" fileds according to SDM Figure 4-7 Vol3. 2. Current code only ignores 4bits instead of 5bits in low "Ignored" filed when calculate PDPT address in PAE mode for guest memory address translation. Tracked-On: #2561 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -211,7 +211,7 @@ static int32_t local_gva2gpa_pae(struct acrn_vcpu *vcpu, struct page_walk_info *
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uint64_t addr;
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int32_t ret = -EFAULT;
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addr = pw_info->top_entry & 0xFFFFFFF0U;
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addr = get_pae_pdpt_addr(pw_info->top_entry);
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base = (uint64_t *)gpa2hva(vcpu->vm, addr);
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if (base != NULL) {
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index = (gva >> 30U) & 0x3UL;
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@ -43,7 +43,7 @@ static void load_pdptrs(const struct acrn_vcpu *vcpu)
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{
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uint64_t guest_cr3 = exec_vmread(VMX_GUEST_CR3);
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/* TODO: check whether guest cr3 is valid */
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uint64_t *guest_cr3_hva = (uint64_t *)gpa2hva(vcpu->vm, guest_cr3);
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uint64_t *guest_cr3_hva = (uint64_t *)gpa2hva(vcpu->vm, get_pae_pdpt_addr(guest_cr3));
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stac();
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exec_vmwrite64(VMX_GUEST_PDPTE0_FULL, get_pgentry(guest_cr3_hva + 0UL));
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@ -176,6 +176,11 @@ static inline void clflush(volatile void *p)
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asm volatile ("clflush (%0)" :: "r"(p));
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}
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/* get PDPT address from CR3 vaule in PAE mode */
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static inline uint64_t get_pae_pdpt_addr(uint64_t cr3)
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{
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return (cr3 & 0xFFFFFFE0UL);
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}
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/**
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* @}
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