debug: enable console and shell for risc-v

For now, BOARD should use the qemu-riscv for risc-v.
For RISC-V:
make hypervisor BOARD=qemu-riscv SCENARIO=shared ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu-
For x86:
make hypervisor BOARD=qemu SCENARIO=shared [ARCH=x86]

Tracked-On: #8805
Signed-off-by: Fei Li <fei1.li@intel.com>

hypervisor/Makefile

@@ -130,6 +130,10 @@ OBJCOPY ?= objcopy
 
 include arch/$(ARCH)/Makefile
 
+LIB_DEBUG = $(HV_MODDIR)/libdebug.a
+LIB_RELEASE = $(HV_MODDIR)/librelease.a
+
+export ARCH
 export CC AS AR LD OBJCOPY
 export CFLAGS ASFLAGS ARFLAGS LDFLAGS ARCH_CFLAGS ARCH_ASFLAGS ARCH_ARFLAGS ARCH_LDFLAGS
 export HV_OBJDIR HV_MODDIR CONFIG_RELEASE INCLUDE_PATH
@@ -151,8 +155,6 @@ endif
 COMMON_C_SRCS += common/notify.c
 COMMON_C_SRCS += common/percpu.c
 COMMON_C_SRCS += common/cpu.c
-COMMON_C_SRCS += lib/memory.c
-COMMON_C_SRCS += lib/bits.c
 COMMON_C_SRCS += common/ticks.c
 COMMON_C_SRCS += common/delay.c
 COMMON_C_SRCS += common/timer.c
@@ -162,8 +164,12 @@ COMMON_C_SRCS += common/schedule.c
 ifeq ($(CONFIG_SCHED_NOOP),y)
 COMMON_C_SRCS += common/sched_noop.c
 endif
+COMMON_C_SRCS += common/sbuf.c
+COMMON_C_SRCS += common/logmsg.c
 
 # library componment
+COMMON_C_SRCS += lib/memory.c
+COMMON_C_SRCS += lib/bits.c
 COMMON_C_SRCS += lib/string.c
 COMMON_C_SRCS += lib/crypto/crypto_api.c
 COMMON_C_SRCS += lib/crypto/mbedtls/hkdf.c
@@ -175,19 +181,19 @@ ifdef STACK_PROTECTOR
 COMMON_C_SRCS += lib/stack_protector.c
 endif
 
+# dm componment
+COMMON_C_SRCS += dm/vuart.c
+
 ifeq ($(ARCH),x86)
 COMMON_C_SRCS += common/irq.c
 COMMON_C_SRCS += common/event.c
 COMMON_C_SRCS += common/efi_mmap.c
-COMMON_C_SRCS += common/sbuf.c
 COMMON_C_SRCS += common/vm_event.c
 COMMON_C_SRCS += common/hv_main.c
 COMMON_C_SRCS += common/vm_load.c
 COMMON_C_SRCS += common/hypercall.c
 COMMON_C_SRCS += common/ptdev.c
-COMMON_C_SRCS += common/logmsg.c
 COMMON_C_SRCS += dm/vrtc.c
-COMMON_C_SRCS += dm/vuart.c
 COMMON_C_SRCS += dm/io_req.c
 COMMON_C_SRCS += dm/vpci/vdev.c
 COMMON_C_SRCS += dm/vpci/vpci.c

hypervisor/arch/riscv/Makefile

@@ -49,9 +49,11 @@ HOST_C_SRCS += arch/riscv/timer.c
 HOST_C_SRCS += arch/riscv/trap.c
 HOST_C_SRCS += arch/riscv/cpu.c
 HOST_C_SRCS += arch/riscv/mmu.c
-HOST_C_SRCS += arch/riscv/logmsg.c
 HOST_C_SRCS += arch/riscv/irq.c
 
+#HV guest C source
+HOST_C_SRCS += arch/riscv/guest/vm.c
+
 # Virtual platform assembly sources
 VP_S_SRCS +=
 

hypervisor/arch/riscv/init.c

@@ -12,6 +12,8 @@
 #include <per_cpu.h>
 #include <logmsg.h>
 #include <timer.h>
+#include <console.h>
+#include <shell.h>
 
 static void init_pcpu_comm_post(void);
 
@@ -28,6 +30,23 @@ static void init_pcpu_comm_post(void);
 	);									\
 }
 
+static void init_debug_pre(void)
+{
+	console_init();
+}
+
+static void init_debug_post(uint16_t pcpu_id)
+{
+	if (pcpu_id == BSP_CPU_ID) {
+		/* Initialize the shell */
+		shell_init();
+	}
+
+	if (pcpu_id == VUART_TIMER_CPU) {
+		console_setup_timer();
+	}
+}
+
 /* C entry point for boot CPU */
 void init_primary_pcpu(uint64_t hart_id, uint64_t fdt_paddr)
 {
@@ -44,6 +63,8 @@ void init_primary_pcpu(uint64_t hart_id, uint64_t fdt_paddr)
 	 */
 	pcpu_set_current_state(pcpu_id, PCPU_STATE_INITIALIZING);
 
+	init_debug_pre();
+
 	if (!start_pcpus(AP_MASK)) {
 		panic("Failed to start all secondary cores!");
 	}
@@ -82,10 +103,17 @@ static void init_pcpu_comm_post(void)
 
 	pcpu_id = get_pcpu_id();
 
+	if (pcpu_id == BSP_CPU_ID) {
+		/* Print Hypervisor Banner */
+		print_hv_banner();
+	}
+
+	init_interrupt(pcpu_id);
 	timer_init();
 
 	/* to be implemented */
 	init_sched(pcpu_id);
 
+	init_debug_post(pcpu_id);
 	run_idle_thread();
 }

hypervisor/arch/riscv/logmsg.c

@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2018-2022 Intel Corporation.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <types.h>
-
-/* FIXME: Temporary RISC-V build workaround
- * This file provides pr_xxx function stubs to satisfy existing
- * code dependencies. Remove this file and migrate to the common
- * logmsg.c implementation once the debug module is properly
- * integrated.
- */
-void do_logmsg(uint32_t severity, const char *fmt, ...)
-{
-	(void)severity;
-	(void)fmt;
-}

hypervisor/arch/x86/Makefile

@@ -19,8 +19,6 @@ VP_DM_MOD = $(HV_MODDIR)/vp_dm_mod.a
 VP_TRUSTY_MOD = $(HV_MODDIR)/vp_trusty_mod.a
 VP_X86_TEE_MOD = $(HV_MODDIR)/vp_x86_tee_mod.a
 VP_HCALL_MOD = $(HV_MODDIR)/vp_hcall_mod.a
-LIB_DEBUG = $(HV_MODDIR)/libdebug.a
-LIB_RELEASE = $(HV_MODDIR)/librelease.a
 SYS_INIT_MOD = $(HV_MODDIR)/sys_init_mod.a
 
 ARCH_CFLAGS += -m64 -mno-mmx -mno-sse -mno-sse2 -mno-80387 -mno-fp-ret-in-387

hypervisor/debug/uart16550.c

@@ -10,7 +10,7 @@
 #include <uart16550.h>
 #include <io.h>
 #include <mmu.h>
-#include <asm/cpu.h>
+#include <cpu.h>
 
 #define MAX_BDF_LEN 8
 

misc/config_tools/data/qemu-riscv/qemu-riscv.xml

@@ -42,8 +42,8 @@
         Version: Not Specified
         </BASE_BOARD_INFO>
   <PCI_DEVICE>
-        00:01.0 1af4: 1041 Network controller: Virtio network device
-        00:02.0 1af4: 1043 Communication controller: Virtio console
+        00:01.0 Network controller: Virtio network device
+        00:02.0 Communication controller: Virtio console
         </PCI_DEVICE>
   <PCI_VID_PID>
         00:01.0 0200: 1af4:1041

misc/config_tools/data/qemu-riscv/shared.xml

@@ -11,6 +11,8 @@
       <RELOC_ENABLED>n</RELOC_ENABLED>
       <SCHEDULER>SCHED_NOOP</SCHEDULER>
       <ACRNTRACE_ENABLED>n</ACRNTRACE_ENABLED>
+      <SERIAL_8250_PCI>n</SERIAL_8250_PCI>
+      <VMCS9900>n</VMCS9900>
     </FEATURES>
     <MEMORY>
       <STACK_SIZE>0x2000</STACK_SIZE>