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https://github.com/projectacrn/acrn-hypervisor.git
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acrn-config: code refactoring for CAT/MBA
1.Modify clos_mask and mba_delay as a member of the union type. 2.Move HV_SUPPORTED_MAX_CLOS ,MAX_CACHE_CLOS_NUM_ENTRIES and MAX_MBA_CLOS_NUM_ENTRIES to misc_cfg.h file. Tracked-On: #5229 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
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@@ -22,9 +22,9 @@ const uint16_t hv_clos = 0U;
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* clos value (valid_clos_num) that is common between the resources as
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* each resource's clos max value to have consistent allocation.
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*/
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#ifdef CONFIG_RDT_ENABLED
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uint16_t valid_clos_num = HV_SUPPORTED_MAX_CLOS;
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#ifdef CONFIG_RDT_ENABLED
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static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = {
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[RDT_RESOURCE_L3] = {
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.res.cache = {
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@@ -35,7 +35,7 @@ static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = {
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.clos_max = 0U,
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.res_id = RDT_RESID_L3,
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.msr_base = MSR_IA32_L3_MASK_BASE,
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.platform_clos_array = platform_l3_clos_array,
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.platform_clos_array = platform_l3_clos_array,
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},
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[RDT_RESOURCE_L2] = {
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.res.cache = {
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@@ -56,7 +56,7 @@ static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = {
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.clos_max = 0U,
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.res_id = RDT_RESID_MBA,
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.msr_base = MSR_IA32_MBA_MASK_BASE,
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.platform_clos_array = platform_mba_clos_array,
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.platform_clos_array = platform_mba_clos_array,
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},
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};
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@@ -78,11 +78,11 @@ static void init_cat_capability(int res)
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#ifdef CONFIG_CDP_ENABLED
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res_cap_info[res].res.cache.is_cdp_enabled = ((ecx & 0x4U) != 0U);
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#else
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res_cap_info[res].res.cache.is_cdp_enabled = false;
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res_cap_info[res].res.cache.is_cdp_enabled = false;
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#endif
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if (res_cap_info[res].res.cache.is_cdp_enabled) {
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res_cap_info[res].clos_max = (uint16_t)((edx & 0xffffU) >> 1U) + 1U;
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/* enable CDP before setting COS to simplify CAT mask rempping
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/* enable CDP before setting COS to simplify CAT mask remapping
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* and prevent unintended behavior.
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*/
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msr_write(res_cap_info[res].res.cache.msr_qos_cfg, 0x1UL);
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@@ -107,7 +107,7 @@ static void init_mba_capability(int res)
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}
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/*
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* @pre valid_clos_num > 0U
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* @pre valid_clos_num > 0U
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*/
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void init_rdt_info(void)
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{
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@@ -148,7 +148,7 @@ void init_rdt_info(void)
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/*
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* @pre res < RDT_NUM_RESOURCES
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* @pre res_clos_info[i].mba_delay <= res_cap_info[res].res.membw.mba_max
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* @pre length of res_clos_info[i].clos_mask <= cbm_len && all 1's in clos_mask is continuous
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* @pre length of res_clos_info[i].clos_mask <= cbm_len && all 1's in clos_mask is continuous
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*/
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static void setup_res_clos_msr(uint16_t pcpu_id, uint16_t res, struct platform_clos_info *res_clos_info)
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{
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@@ -163,10 +163,10 @@ static void setup_res_clos_msr(uint16_t pcpu_id, uint16_t res, struct platform_c
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switch (res) {
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case RDT_RESOURCE_L3:
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case RDT_RESOURCE_L2:
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val = (uint64_t)res_clos_info[i].clos_mask;
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val = (uint64_t)res_clos_info[i].value.clos_mask;
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break;
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case RDT_RESOURCE_MBA:
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val = (uint64_t)res_clos_info[i].mba_delay;
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val = (uint64_t)res_clos_info[i].value.mba_delay;
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break;
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default:
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ASSERT(res < RDT_NUM_RESOURCES, "Support only 3 RDT resources. res=%d is invalid", res);
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@@ -10,13 +10,16 @@
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#include <board_info.h>
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#include <host_pm.h>
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#include <pci.h>
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#include <misc_cfg.h>
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/* forward declarations */
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struct acrn_vm;
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struct platform_clos_info {
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uint16_t mba_delay;
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uint32_t clos_mask;
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union {
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uint16_t mba_delay;
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uint32_t clos_mask;
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}value;
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uint32_t msr_index;
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};
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@@ -28,9 +31,9 @@ struct vmsix_on_msi_info {
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extern struct dmar_info plat_dmar_info;
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#ifdef CONFIG_RDT_ENABLED
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extern struct platform_clos_info platform_l2_clos_array[HV_SUPPORTED_MAX_CLOS];
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extern struct platform_clos_info platform_l3_clos_array[HV_SUPPORTED_MAX_CLOS];
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extern struct platform_clos_info platform_mba_clos_array[HV_SUPPORTED_MAX_CLOS];
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extern struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
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extern struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
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extern struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
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#endif
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extern const struct cpu_state_table board_cpu_state_tbl;
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