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acrn-config: code refactoring for CAT/MBA

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1.Modify clos_mask and mba_delay as a member of the union type.
2.Move HV_SUPPORTED_MAX_CLOS ,MAX_CACHE_CLOS_NUM_ENTRIES and
MAX_MBA_CLOS_NUM_ENTRIES to misc_cfg.h file.

Tracked-On: #5229
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
Wei Liu
2020-08-23 17:05:46 -07:00
committed by wenlingz
parent 7eb103478a
commit 29ac258134
20 changed files with 272 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
misc/vm_configs/boards/nuc7i7dnb/board.c
View File

@@ -71,9 +71,9 @@ struct dmar_info plat_dmar_info = {
};
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_l3_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_mba_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
#endif
static const struct cpu_cx_data board_cpu_cx[3] = {

1
misc/vm_configs/boards/nuc7i7dnb/board_info.h
View File

@@ -8,7 +8,6 @@
#define BOARD_INFO_H
#define MAX_PCPU_NUM 4U
#define HV_SUPPORTED_MAX_CLOS 0U
#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U
#define MAX_HIDDEN_PDEVS_NUM 0U

6
misc/vm_configs/boards/whl-ipc-i5/board.c
View File

@@ -72,9 +72,9 @@ struct dmar_info plat_dmar_info = {
};
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_l3_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_mba_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
#endif
static const struct cpu_cx_data board_cpu_cx[3] = {

1
misc/vm_configs/boards/whl-ipc-i5/board_info.h
View File

@@ -8,7 +8,6 @@
#define BOARD_INFO_H
#define MAX_PCPU_NUM 4U
#define HV_SUPPORTED_MAX_CLOS 0U
#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U
#define MAX_HIDDEN_PDEVS_NUM 0U

6
misc/vm_configs/boards/whl-ipc-i7/board.c
View File

@@ -72,9 +72,9 @@ struct dmar_info plat_dmar_info = {
};
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_l3_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_mba_clos_array[HV_SUPPORTED_MAX_CLOS];
struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
#endif
static const struct cpu_cx_data board_cpu_cx[3] = {

1
misc/vm_configs/boards/whl-ipc-i7/board_info.h
View File

@@ -8,7 +8,6 @@
#define BOARD_INFO_H
#define MAX_PCPU_NUM 4U
#define HV_SUPPORTED_MAX_CLOS 0U
#define MAX_VMSIX_ON_MSI_PDEVS_NUM 0U
#define MAX_HIDDEN_PDEVS_NUM 0U

22
misc/vm_configs/scenarios/hybrid/nuc7i7dnb/misc_cfg.h
View File

@@ -25,4 +25,26 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/hybrid/whl-ipc-i5/misc_cfg.h
View File

@@ -25,4 +25,26 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/hybrid/whl-ipc-i7/misc_cfg.h
View File

@@ -25,4 +25,26 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/misc_cfg.h
View File

@@ -25,6 +25,28 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#define VM0_PASSTHROUGH_TPM
#define VM0_TPM_BUFFER_BASE_ADDR 0xFED40000UL
#define VM0_TPM_BUFFER_SIZE 0x5000UL

22
misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i7/misc_cfg.h
View File

@@ -25,6 +25,28 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#define VM0_PASSTHROUGH_TPM
#define VM0_TPM_BUFFER_BASE_ADDR 0xFED40000UL
#define VM0_TPM_BUFFER_SIZE 0x5000UL

22
misc/vm_configs/scenarios/industry/nuc7i7dnb/misc_cfg.h
View File

@@ -25,4 +25,26 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/industry/whl-ipc-i5/misc_cfg.h
View File

@@ -25,4 +25,26 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/industry/whl-ipc-i7/misc_cfg.h
View File

@@ -25,4 +25,26 @@
"hvlog=2M@0xe00000 " \
"memmap=0x200000$0xe00000"
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/logical_partition/nuc7i7dnb/misc_cfg.h
View File

@@ -7,4 +7,26 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/logical_partition/whl-ipc-i5/misc_cfg.h
View File

@@ -7,4 +7,26 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */

22
misc/vm_configs/scenarios/logical_partition/whl-ipc-i7/misc_cfg.h
View File

@@ -7,4 +7,26 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#endif
#endif /* MISC_CFG_H */