mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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DM: gvt: Identical mapping for GPU DSM refine to support EHL/TGL
Windows graphic driver obtains DSM address from in-BAR mmio register which has passthroughed. Not like the other platforms obtained from pci configure space register which has virtualized. GPU GuC must use WOPCM in DSM, besides, Windows OS wants to manage DSM also. These two reason force acrn has to keep identical mapping to avoid trap mmio BAR to do the emulation. Tracked-On: #5880 Signed-off-by: Peng Sun <peng.p.sun@intel.com>
This commit is contained in:
ppsun
wenlingz
parent
b80c388b52
commit
2a96c567b8
@ -54,20 +54,14 @@ static char bootargs[BOOT_ARG_LEN];
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* Begin Limit Type Length
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* 0: 0 - 0xA0000 RAM 0xA0000
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* 1: 0x100000 - lowmem part1 RAM 0x0
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* 2: gpu_rsvd_bot - gpu_rsvd_top (reserved) 0x4004000
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* 3: lowmem part2 - 0x7f800000 (reserved) 0x0
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* 4: SW SRAM_bot - 0x80000000 (reserved) SOFTWARE_SRAM_MAX_SIZE
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* 5: 0xDB000000 - 0xDF000000 (reserved) 64MB
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* 6: 0xDF000000 - 0xE0000000 (reserved) 16MB
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* 7: 0xE0000000 - 0x100000000 MCFG, MMIO 512MB
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* 8: 0x140000000 - highmem RAM highmem - 5GB
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* 2: SW SRAM_bot - SW SRAM_top (reserved) SOFTWARE_SRAM_MAX_SIZE
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* 3: gpu_rsvd_bot - gpu_rsvd_top (reserved) 0x4004000
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* 4: lowmem part2 - 0x80000000 (reserved) 0x0
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* 5: 0xE0000000 - 0x100000000 MCFG, MMIO 512MB
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* 6: 0x140000000 - highmem RAM highmem - 5GB
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*
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* FIXME: Do we need to reserve DSM and OPREGION for GVTD here.
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*/
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#define GPU_DSM_OPREGION_BASE_GPA 0x3B800000
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#define GPU_DSM_OPREGION_SIZE 0x4004000
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const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
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{ /* 0 to video memory */
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.baseaddr = 0x00000000,
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@ -81,30 +75,30 @@ const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
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.type = E820_TYPE_RAM
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},
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{ /* TGL GPU DSM & OpRegion area */
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.baseaddr = GPU_DSM_OPREGION_BASE_GPA,
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.length = GPU_DSM_OPREGION_SIZE,
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.type = E820_TYPE_RESERVED
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},
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{ /* lowmem part2 to lowmem_limit */
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.baseaddr = GPU_DSM_OPREGION_BASE_GPA + GPU_DSM_OPREGION_SIZE,
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.length = 0x0,
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.type = E820_TYPE_RESERVED
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},
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/*
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* Software SRAM area: base: 0x7f800000, size: 0x800000
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* Software SRAM area: size: 0x800000
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* In native, the Software SRAM region should be part of DRAM memory.
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* But one fixed Software SRAM gpa is friendly for virtualization due
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* to decoupled with various guest memory size.
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*/
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{
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.baseaddr = SOFTWARE_SRAM_BASE_GPA,
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.length = SOFTWARE_SRAM_MAX_SIZE,
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.baseaddr = 0x0,
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.length = 0x0,
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.type = E820_TYPE_RESERVED
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},
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{ /* GPU DSM & OpRegion reserved region */
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.baseaddr = 0x0,
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.length = 0x0,
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.type = E820_TYPE_RESERVED
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},
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{ /* lowmem part2 to lowmem_limit */
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.baseaddr = 0x0,
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.length = 0x0,
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.type = E820_TYPE_RESERVED
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},
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{ /* ECFG_BASE to 4GB */
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.baseaddr = PCI_EMUL_ECFG_BASE,
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.length = (4 * GB) - PCI_EMUL_ECFG_BASE,
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@ -225,32 +219,65 @@ uint32_t
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acrn_create_e820_table(struct vmctx *ctx, struct e820_entry *e820)
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{
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uint32_t removed = 0, k;
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uint32_t gpu_rsvmem_base_gpa = 0;
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uint64_t software_sram_base_gpa = 0;
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memcpy(e820, e820_default_entries, sizeof(e820_default_entries));
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if (ctx->lowmem <= e820[LOWRAM_E820_ENTRY + 2].baseaddr) {
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e820[LOWRAM_E820_ENTRY].length =
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(ctx->lowmem < e820[LOWRAM_E820_ENTRY+1].baseaddr ? ctx->lowmem :
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e820[LOWRAM_E820_ENTRY+1].baseaddr) - e820[LOWRAM_E820_ENTRY].baseaddr;
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memmove(&e820[LOWRAM_E820_ENTRY + 2], &e820[LOWRAM_E820_ENTRY + 3],
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sizeof(struct e820_entry) *
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(NUM_E820_ENTRIES - (LOWRAM_E820_ENTRY + 3)));
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removed++;
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/* FIXME: Here wastes 8MB memory if pSRAM is enabled, and 64MB+16KB if
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* GPU reserved memory is exist.
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*
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* Determines the GPU region due to DSM identical mapping.
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*/
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gpu_rsvmem_base_gpa = get_gpu_rsvmem_base_gpa();
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if (gpu_rsvmem_base_gpa) {
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e820[LOWRAM_E820_ENTRY + 2].baseaddr = gpu_rsvmem_base_gpa;
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e820[LOWRAM_E820_ENTRY + 2].length = get_gpu_rsvmem_size();
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} else {
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e820[LOWRAM_E820_ENTRY].length = e820[LOWRAM_E820_ENTRY+1].baseaddr -
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e820[LOWRAM_E820_ENTRY].baseaddr;
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e820[LOWRAM_E820_ENTRY + 2].length =
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((ctx->lowmem < e820[LOWRAM_E820_ENTRY + 3].baseaddr) ? ctx->lowmem :
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e820[LOWRAM_E820_ENTRY + 3].baseaddr) - e820[LOWRAM_E820_ENTRY + 2].baseaddr;
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e820[LOWRAM_E820_ENTRY + 2].baseaddr = ctx->lowmem_limit;
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}
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/* remove [5GB, highmem) if it's empty */
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if (ctx->highmem > 0) {
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e820[HIGHRAM_E820_ENTRY - removed].type = E820_TYPE_RAM;
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e820[HIGHRAM_E820_ENTRY - removed].length = ctx->highmem;
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/* Always put SW SRAM before GPU region and keep 1MB boundary for protection. */
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software_sram_base_gpa = get_software_sram_base_gpa();
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if (software_sram_base_gpa) {
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e820[LOWRAM_E820_ENTRY + 1].baseaddr = software_sram_base_gpa;
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e820[LOWRAM_E820_ENTRY + 1].length = get_software_sram_size();
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} else {
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removed++;
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e820[LOWRAM_E820_ENTRY + 1].baseaddr = e820[LOWRAM_E820_ENTRY + 2].baseaddr;
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}
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if (ctx->lowmem <= e820[LOWRAM_E820_ENTRY + 1].baseaddr) {
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/* Caculation for lowmem part1 */
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e820[LOWRAM_E820_ENTRY].length =
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ctx->lowmem - e820[LOWRAM_E820_ENTRY].baseaddr;
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} else {
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/* Caculation for lowmem part1 */
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e820[LOWRAM_E820_ENTRY].length =
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e820[LOWRAM_E820_ENTRY + 1].baseaddr - e820[LOWRAM_E820_ENTRY].baseaddr;
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/* Caculation for lowmem part2 */
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e820[LOWRAM_E820_ENTRY + 3].baseaddr =
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e820[LOWRAM_E820_ENTRY + 2].baseaddr + e820[LOWRAM_E820_ENTRY + 2].length;
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if (ctx->lowmem > e820[LOWRAM_E820_ENTRY + 3].baseaddr) {
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e820[LOWRAM_E820_ENTRY + 3].length =
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ctx->lowmem - e820[LOWRAM_E820_ENTRY + 3].baseaddr;
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e820[LOWRAM_E820_ENTRY + 3].type = E820_TYPE_RAM;
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}
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}
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/* Caculation for highmem */
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if (ctx->highmem > 0) {
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e820[HIGHRAM_E820_ENTRY].type = E820_TYPE_RAM;
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e820[HIGHRAM_E820_ENTRY].length = ctx->highmem;
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}
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/* Remove empty entries in e820 table */
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for (k = 0; k < (NUM_E820_ENTRIES - 1 - removed); k++) {
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if (e820[k].length == 0x0) {
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memmove(&e820[k], &e820[k + 1], sizeof(struct e820_entry) *
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(NUM_E820_ENTRIES - (k + 1)));
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k--;
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removed++;
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}
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}
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pr_info("SW_LOAD: build e820 %d entries to addr: %p\r\n",
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@ -59,48 +59,13 @@
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#define PCI_BDF_GPU 0x00000010 /* 00:02.0 */
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/* Reserved region in e820 table for GVT
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* for GVT-g use:
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* [0xDF000000, 0xDF800000) 8M, GOP FB, used OvmfPkg/GvtGopDxe for 1080p@30
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* [0xDFFFD000, 0xDFFFF000) 8K, OpRegion, used by GvtGopDxe and GVT-g
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* [0xDFFFF000, 0XE0000000) 4K, Reserved, not used
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* for TGL GVT-d use:
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* [0x3B800000, 0x3F800000) 64M, Date Stolen Memory
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* [0x3F800000, 0X3F804000] 16K, OpRegion and Extended OpRegion
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* for EHL/WHL/KBL GVT-d use:
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* [0xDB000000, 0xDF000000) 64M, DSM, used by native GOP and gfx driver
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* [0xDFFFC000, 0xDFFFE000) 8K, OpRegion, used by native GOP and gfx driver
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* [0xDFFFE000, 0XE0000000] 8K, Extended OpRegion, store raw VBT
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* OpRegion: 8KB(0x2000)
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* [ OpRegion Header ] Offset: 0x0
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* [ Mailbox #1: ACPI ] Offset: 0x100
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* [ Mailbox #2: SWSCI ] Offset: 0x200
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* [ Mailbox #3: ASLE ] Offset: 0x300
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* [ Mailbox #4: VBT ] Offset: 0x400
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* [ Mailbox #5: ASLE EXT ] Offset: 0x1C00
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* Extended OpRegion: 8KB(0x2000)
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* [ Raw VBT ] Offset: 0x0
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* If VBT <= 6KB, stores in Mailbox #4
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* If VBT > 6KB, stores in Extended OpRegion
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* ASLE.rvda stores the location of VBT.
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* For OpRegion 2.1+: ASLE.rvda = offset to OpRegion base address
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* For OpRegion 2.0: ASLE.rvda = physical address, not support currently
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*/
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#define GPU_DSM_GPA 0xDB000000
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#define GPU_DSM_SIZE 0x4000000
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#define GPU_OPREGION_GPA 0xDFFFC000
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#define GPU_OPREGION_SIZE 0x4000
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/*
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* TODO: Forced DSM/OPREGION size requires native BIOS configuration.
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* This limitation need remove in future
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*/
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extern uint64_t audio_nhlt_len;
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uint32_t gpu_dsm_hpa = 0;
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uint32_t gpu_dsm_gpa = 0;
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uint32_t gpu_opregion_hpa = 0;
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uint32_t gpu_opregion_gpa = 0;
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extern uint64_t audio_nhlt_len;
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/* reference count for libpciaccess init/deinit */
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static int pciaccess_ref_cnt;
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static pthread_mutex_t ref_cnt_mtx = PTHREAD_MUTEX_INITIALIZER;
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@ -472,6 +437,18 @@ has_virt_pcicfg_regs_on_def_gpu(int offset)
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return ((offset == PCIR_BDSM) || (offset == PCIR_ASLS_CTL));
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}
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uint32_t
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get_gpu_rsvmem_base_gpa()
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{
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return gpu_opregion_gpa;
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}
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uint32_t
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get_gpu_rsvmem_size()
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{
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return GPU_OPREGION_SIZE + GPU_DSM_SIZE;
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}
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/*
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* passthrough GPU DSM(Data Stolen Memory) and Opregion to guest
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*/
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@ -487,24 +464,6 @@ passthru_gpu_dsm_opregion(struct vmctx *ctx, struct passthru_dev *ptdev,
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switch (device) {
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case INTEL_ELKHARTLAKE:
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/* BDSM register has 64 bits.
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* bits 63:20 contains the base address of stolen memory
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*/
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gpu_dsm_hpa = read_config(ptdev->phys_dev, PCIR_GEN11_BDSM_DW0, 4);
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dsm_mask_val = gpu_dsm_hpa & ~PCIM_BDSM_MASK;
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gpu_dsm_hpa &= PCIM_BDSM_MASK;
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gpu_dsm_hpa |= (uint64_t)read_config(ptdev->phys_dev, PCIR_GEN11_BDSM_DW1, 4) << 32;
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gpu_dsm_gpa = GPU_DSM_GPA;
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pci_set_cfgdata32(ptdev->dev, PCIR_GEN11_BDSM_DW0, gpu_dsm_gpa | dsm_mask_val);
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/* write 0 to high 32-bits of BDSM on EHL platform */
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pci_set_cfgdata32(ptdev->dev, PCIR_GEN11_BDSM_DW1, 0);
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gpu_opregion_gpa = GPU_OPREGION_GPA;
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ptdev->has_virt_pcicfg_regs = &has_virt_pcicfg_regs_on_ehl_gpu;
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break;
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case INTEL_TIGERLAKE:
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/* BDSM register has 64 bits.
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* bits 63:20 contains the base address of stolen memory
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@ -523,8 +482,6 @@ passthru_gpu_dsm_opregion(struct vmctx *ctx, struct passthru_dev *ptdev,
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/* write 0 to high 32-bits of BDSM on EHL platform */
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pci_set_cfgdata32(ptdev->dev, PCIR_GEN11_BDSM_DW1, 0);
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gpu_opregion_gpa = gpu_dsm_gpa + GPU_DSM_SIZE;
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ptdev->has_virt_pcicfg_regs = &has_virt_pcicfg_regs_on_ehl_gpu;
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break;
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/* If on default platforms, such as KBL,WHL */
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@ -537,12 +494,11 @@ passthru_gpu_dsm_opregion(struct vmctx *ctx, struct passthru_dev *ptdev,
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pci_set_cfgdata32(ptdev->dev, PCIR_BDSM, gpu_dsm_gpa | dsm_mask_val);
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gpu_opregion_gpa = GPU_OPREGION_GPA;
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ptdev->has_virt_pcicfg_regs = &has_virt_pcicfg_regs_on_def_gpu;
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break;
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}
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gpu_opregion_gpa = gpu_dsm_gpa - GPU_OPREGION_SIZE;
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pci_set_cfgdata32(ptdev->dev, PCIR_ASLS_CTL, gpu_opregion_gpa | (opregion_phys & ~PCIM_ASLS_OPREGION_MASK));
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/* initialize the EPT mapping for passthrough GPU dsm region */
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@ -1095,13 +1095,13 @@ int create_and_inject_vrtct(struct vmctx *ctx)
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uint8_t *vrtct;
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struct vm_memmap memmap = {
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.type = VM_MMIO,
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.gpa = SOFTWARE_SRAM_BASE_GPA,
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/* HPA base and size of Software SRAM shall be parsed from vRTCT. */
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.hpa = 0,
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.len = 0,
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.prot = PROT_ALL
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};
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memmap.gpa = get_software_sram_base_gpa();
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native_rtct_fd = open(RTCT_NATIVE_FILE_PATH_IN_SOS, O_RDONLY);
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if (native_rtct_fd < 0) {
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pr_err("failed to open /sys/firmware/acpi/tables/PTCT !!!!! errno:%d\n", errno);
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@ -35,6 +35,7 @@
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static uint64_t software_sram_base_hpa;
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static uint64_t software_sram_size;
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static uint64_t software_sram_base_gpa;
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static uint8_t vrtct_checksum(uint8_t *vrtct, uint32_t length)
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{
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@ -209,7 +210,7 @@ static void remap_software_sram_regions(struct acpi_table_hdr *vrtct)
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foreach_rtct_entry(vrtct, entry) {
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if (entry->type == RTCT_ENTRY_TYPE_PSRAM) {
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sw_sram_region = (struct rtct_entry_data_psram *)entry->data;
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sw_sram_region->base = SOFTWARE_SRAM_BASE_GPA + (sw_sram_region->base - hpa_bottom);
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sw_sram_region->base = software_sram_base_gpa + (sw_sram_region->base - hpa_bottom);
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}
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}
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}
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@ -287,6 +288,11 @@ uint64_t get_software_sram_base_hpa(void)
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return software_sram_base_hpa;
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}
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uint64_t get_software_sram_base_gpa(void)
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{
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return software_sram_base_gpa;
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}
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uint64_t get_software_sram_size(void)
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{
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return software_sram_size;
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@ -306,6 +312,7 @@ uint8_t *build_vrtct(struct vmctx *ctx, void *cfg)
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struct acrn_vm_config vm_cfg;
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struct acpi_table_hdr *rtct_cfg, *vrtct = NULL;
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uint64_t dm_cpu_bitmask, hv_cpu_bitmask, guest_pcpu_bitmask;
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uint32_t gpu_rsvmem_base_gpa = 0;
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if ((cfg == NULL) || (ctx == NULL))
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return NULL;
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@ -351,6 +358,14 @@ uint8_t *build_vrtct(struct vmctx *ctx, void *cfg)
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pr_info("%s, dm_cpu_bitmask:0x%x, hv_cpu_bitmask:0x%x, guest_cpu_bitmask: 0x%x\n",
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__func__, dm_cpu_bitmask, hv_cpu_bitmask, guest_pcpu_bitmask);
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gpu_rsvmem_base_gpa = get_gpu_rsvmem_base_gpa();
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software_sram_size = SOFTWARE_SRAM_MAX_SIZE;
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/* TODO: It is better to put one boundary between GPU region and SW SRAM
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* for protection.
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*/
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software_sram_base_gpa = ((gpu_rsvmem_base_gpa ? gpu_rsvmem_base_gpa : 0x80000000UL) -
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software_sram_size) & ~software_sram_size;
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if (passthru_rtct_to_guest(vrtct, rtct_cfg, guest_pcpu_bitmask)) {
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pr_err("%s, initialize vRTCT fail.", __func__);
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goto error;
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@ -263,6 +263,45 @@ int create_mmio_rsvd_rgn(uint64_t start,
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uint64_t end, int idx, int bar_type, struct pci_vdev *vdev);
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void destory_mmio_rsvd_rgns(struct pci_vdev *vdev);
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/* Reserved region in e820 table for GVT
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* for GVT-g use:
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* [0xDF000000, 0xDF800000) 8M, GOP FB, used OvmfPkg/GvtGopDxe for 1080p@30
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* [0xDFFFD000, 0xDFFFF000) 8K, OpRegion, used by GvtGopDxe and GVT-g
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* [0xDFFFF000, 0XE0000000) 4K, Reserved, not used
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* for TGL/EHL GVT-d use: identical mapping, same with host layout
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* [gpu_opregion_hpa, gpu_opregion_hpa+size) 16K, OpRegion and Extended OpRegion
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* [gpu_dsm_hpa, gpu_dsm_hpa+size] 64M, Date Stolen Memory
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* for WHL/KBL GVT-d use:
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* [0x7BFFC000, 0x7BFFE000) 8K, OpRegion, used by native GOP and gfx driver
|
||||
* [0x7BFFE000, 0X7C000000] 8K, Extended OpRegion, store raw VBT
|
||||
* [0x7C000000, 0x80000000] 64M, DSM, used by native GOP and gfx driver
|
||||
* OpRegion: 8KB(0x2000)
|
||||
* [ OpRegion Header ] Offset: 0x0
|
||||
* [ Mailbox #1: ACPI ] Offset: 0x100
|
||||
* [ Mailbox #2: SWSCI ] Offset: 0x200
|
||||
* [ Mailbox #3: ASLE ] Offset: 0x300
|
||||
* [ Mailbox #4: VBT ] Offset: 0x400
|
||||
* [ Mailbox #5: ASLE EXT ] Offset: 0x1C00
|
||||
* Extended OpRegion: 8KB(0x2000)
|
||||
* [ Raw VBT ] Offset: 0x0
|
||||
* If VBT <= 6KB, stores in Mailbox #4
|
||||
* If VBT > 6KB, stores in Extended OpRegion
|
||||
* ASLE.rvda stores the location of VBT.
|
||||
* For OpRegion 2.1+: ASLE.rvda = offset to OpRegion base address
|
||||
* For OpRegion 2.0: ASLE.rvda = physical address, not support currently
|
||||
*/
|
||||
#define GPU_DSM_GPA 0x7C000000
|
||||
#define GPU_DSM_SIZE 0x4000000
|
||||
#define GPU_OPREGION_SIZE 0x4000
|
||||
/*
|
||||
* TODO: Forced DSM/OPREGION size requires native BIOS configuration.
|
||||
* This limitation need remove in future
|
||||
*/
|
||||
uint32_t get_gpu_rsvmem_base_gpa(void);
|
||||
uint32_t get_gpu_rsvmem_size(void);
|
||||
uint64_t get_software_sram_base_gpa(void);
|
||||
uint64_t get_software_sram_size(void);
|
||||
|
||||
typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
|
||||
int ioapic_irq, void *arg);
|
||||
|
||||
|
||||
@ -1066,8 +1066,8 @@
|
||||
#define PCIM_OSC_CTL_PCIE_CAP_STRUCT 0x10 /* Various Capability Structures */
|
||||
|
||||
/* Graphics definitions */
|
||||
#define INTEL_ELKHARTLAKE 0x4551
|
||||
#define INTEL_TIGERLAKE 0x9a49
|
||||
#define INTEL_ELKHARTLAKE 0x4571
|
||||
#define INTEL_TIGERLAKE 0x9a49
|
||||
#define PCIR_BDSM 0x5C /* BDSM graphics base data of stolen memory register */
|
||||
#define PCIR_GEN11_BDSM_DW0 0xC0
|
||||
#define PCIR_GEN11_BDSM_DW1 0xC4
|
||||
|
||||
@ -39,9 +39,9 @@
|
||||
#define E820_TYPE_ACPI_NVS 4U /* EFI 10 */
|
||||
#define E820_TYPE_UNUSABLE 5U /* EFI 8 */
|
||||
|
||||
#define NUM_E820_ENTRIES 9
|
||||
#define LOWRAM_E820_ENTRY 1
|
||||
#define HIGHRAM_E820_ENTRY 6
|
||||
#define NUM_E820_ENTRIES 7
|
||||
#define LOWRAM_E820_ENTRY 1
|
||||
#define HIGHRAM_E820_ENTRY 6
|
||||
|
||||
/* Defines a single entry in an E820 memory map. */
|
||||
struct e820_entry {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user