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DM: gvt: Identical mapping for GPU DSM refine to support EHL/TGL

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Windows graphic driver obtains DSM address from in-BAR mmio register
which has passthroughed. Not like the other platforms obtained from
pci configure space register which has virtualized. GPU GuC must use
WOPCM in DSM, besides, Windows OS wants to manage DSM also. These two
reason force acrn has to keep identical mapping to avoid trap mmio
BAR to do the emulation.

Tracked-On: #5880
Signed-off-by: Peng Sun <peng.p.sun@intel.com>
This commit is contained in:
ppsun
2021-03-29 08:53:29 +00:00
committed by wenlingz
parent b80c388b52
commit 2a96c567b8
7 changed files with 148 additions and 111 deletions
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39
devicemodel/include/pci_core.h
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@@ -263,6 +263,45 @@ int create_mmio_rsvd_rgn(uint64_t start,
uint64_t end, int idx, int bar_type, struct pci_vdev *vdev);
void destory_mmio_rsvd_rgns(struct pci_vdev *vdev);
/* Reserved region in e820 table for GVT
* for GVT-g use:
* [0xDF000000, 0xDF800000) 8M, GOP FB, used OvmfPkg/GvtGopDxe for 1080p@30
* [0xDFFFD000, 0xDFFFF000) 8K, OpRegion, used by GvtGopDxe and GVT-g
* [0xDFFFF000, 0XE0000000) 4K, Reserved, not used
* for TGL/EHL GVT-d use: identical mapping, same with host layout
* [gpu_opregion_hpa, gpu_opregion_hpa+size) 16K, OpRegion and Extended OpRegion
* [gpu_dsm_hpa, gpu_dsm_hpa+size] 64M, Date Stolen Memory
* for WHL/KBL GVT-d use:
* [0x7BFFC000, 0x7BFFE000) 8K, OpRegion, used by native GOP and gfx driver
* [0x7BFFE000, 0X7C000000] 8K, Extended OpRegion, store raw VBT
* [0x7C000000, 0x80000000] 64M, DSM, used by native GOP and gfx driver
* OpRegion: 8KB(0x2000)
* [ OpRegion Header ] Offset: 0x0
* [ Mailbox #1: ACPI ] Offset: 0x100
* [ Mailbox #2: SWSCI ] Offset: 0x200
* [ Mailbox #3: ASLE ] Offset: 0x300
* [ Mailbox #4: VBT ] Offset: 0x400
* [ Mailbox #5: ASLE EXT ] Offset: 0x1C00
* Extended OpRegion: 8KB(0x2000)
* [ Raw VBT ] Offset: 0x0
* If VBT <= 6KB, stores in Mailbox #4
* If VBT > 6KB, stores in Extended OpRegion
* ASLE.rvda stores the location of VBT.
* For OpRegion 2.1+: ASLE.rvda = offset to OpRegion base address
* For OpRegion 2.0: ASLE.rvda = physical address, not support currently
*/
#define GPU_DSM_GPA 0x7C000000
#define GPU_DSM_SIZE 0x4000000
#define GPU_OPREGION_SIZE 0x4000
/*
* TODO: Forced DSM/OPREGION size requires native BIOS configuration.
* This limitation need remove in future
*/
uint32_t get_gpu_rsvmem_base_gpa(void);
uint32_t get_gpu_rsvmem_size(void);
uint64_t get_software_sram_base_gpa(void);
uint64_t get_software_sram_size(void);
typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
int ioapic_irq, void *arg);

4
devicemodel/include/pcireg.h
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@@ -1066,8 +1066,8 @@
#define PCIM_OSC_CTL_PCIE_CAP_STRUCT 0x10 /* Various Capability Structures */
/* Graphics definitions */
#define INTEL_ELKHARTLAKE 0x4551
#define INTEL_TIGERLAKE 0x9a49
#define INTEL_ELKHARTLAKE 0x4571
#define INTEL_TIGERLAKE 0x9a49
#define PCIR_BDSM 0x5C /* BDSM graphics base data of stolen memory register */
#define PCIR_GEN11_BDSM_DW0 0xC0
#define PCIR_GEN11_BDSM_DW1 0xC4

6
devicemodel/include/sw_load.h
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@@ -39,9 +39,9 @@
#define E820_TYPE_ACPI_NVS 4U /* EFI 10 */
#define E820_TYPE_UNUSABLE 5U /* EFI 8 */
#define NUM_E820_ENTRIES 9
#define LOWRAM_E820_ENTRY 1
#define HIGHRAM_E820_ENTRY 6
#define NUM_E820_ENTRIES 7
#define LOWRAM_E820_ENTRY 1
#define HIGHRAM_E820_ENTRY 6
/* Defines a single entry in an E820 memory map. */
struct e820_entry {