mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-18 11:47:30 +00:00
HV: refine 'struct lapic_regs' definition.
- remove 'PAD3' & 'PAD4' - define local APIC registers by 'struct lapic_reg' type. Tracked-On: #861 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Yonghua Huang
lijinxia
parent
5329ced1ea
commit
2af08d9619
@ -60,7 +60,7 @@ static inline void vlapic_dump_irr(struct acrn_vlapic *vlapic, char *msg)
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for (i = 0U; i < 8U; i++)
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dev_dbg(ACRN_DBG_LAPIC, "%s irr%u 0x%08x",
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msg, i, irrptr[i].val);
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msg, i, irrptr[i].v);
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}
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static inline void vlapic_dump_isr(struct acrn_vlapic *vlapic, char *msg)
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@ -70,7 +70,7 @@ static inline void vlapic_dump_isr(struct acrn_vlapic *vlapic, char *msg)
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for (i = 0U; i < 8U; i++) {
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dev_dbg(ACRN_DBG_LAPIC, "%s isr%u 0x%08x",
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msg, i, isrptr[0].val);
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msg, i, isrptr[0].v);
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}
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}
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#else
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@ -159,14 +159,14 @@ vm_active_cpus(struct vm *vm)
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uint32_t
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vlapic_get_id(struct acrn_vlapic *vlapic)
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{
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uint32_t id = vlapic->apic_page.id;
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uint32_t id = vlapic->apic_page.id.v;
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return id;
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}
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uint8_t
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vlapic_get_apicid(struct acrn_vlapic *vlapic)
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{
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uint32_t apicid = (vlapic->apic_page.id) >> APIC_ID_SHIFT;
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uint32_t apicid = (vlapic->apic_page.id.v) >> APIC_ID_SHIFT;
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return (uint8_t)apicid;
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}
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@ -206,12 +206,13 @@ vlapic_dfr_write_handler(struct acrn_vlapic *vlapic)
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struct lapic_regs *lapic;
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lapic = &(vlapic->apic_page);
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lapic->dfr &= APIC_DFR_MODEL_MASK;
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lapic->dfr |= APIC_DFR_RESERVED;
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lapic->dfr.v &= APIC_DFR_MODEL_MASK;
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lapic->dfr.v |= APIC_DFR_RESERVED;
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if ((lapic->dfr & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_FLAT) {
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if ((lapic->dfr.v & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_FLAT) {
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dev_dbg(ACRN_DBG_LAPIC, "vlapic DFR in Flat Model");
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} else if ((lapic->dfr & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_CLUSTER) {
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} else if ((lapic->dfr.v & APIC_DFR_MODEL_MASK)
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== APIC_DFR_MODEL_CLUSTER) {
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dev_dbg(ACRN_DBG_LAPIC, "vlapic DFR in Cluster Model");
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} else {
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dev_dbg(ACRN_DBG_LAPIC, "DFR in Unknown Model %#x", lapic->dfr);
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@ -224,7 +225,7 @@ vlapic_ldr_write_handler(struct acrn_vlapic *vlapic)
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struct lapic_regs *lapic;
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lapic = &(vlapic->apic_page);
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lapic->ldr &= ~APIC_LDR_RESERVED;
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lapic->ldr.v &= ~APIC_LDR_RESERVED;
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dev_dbg(ACRN_DBG_LAPIC, "vlapic LDR set to %#x", lapic->ldr);
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}
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@ -247,28 +248,28 @@ vlapic_timer_divisor_shift(uint32_t dcr)
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static inline bool
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vlapic_lvtt_oneshot(struct acrn_vlapic *vlapic)
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{
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return (((vlapic->apic_page.lvt[APIC_LVT_TIMER].val) & APIC_LVTT_TM)
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return (((vlapic->apic_page.lvt[APIC_LVT_TIMER].v) & APIC_LVTT_TM)
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== APIC_LVTT_TM_ONE_SHOT);
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}
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static inline bool
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vlapic_lvtt_period(struct acrn_vlapic *vlapic)
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{
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return (((vlapic->apic_page.lvt[APIC_LVT_TIMER].val) & APIC_LVTT_TM)
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return (((vlapic->apic_page.lvt[APIC_LVT_TIMER].v) & APIC_LVTT_TM)
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== APIC_LVTT_TM_PERIODIC);
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}
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static inline bool
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vlapic_lvtt_tsc_deadline(struct acrn_vlapic *vlapic)
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{
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return (((vlapic->apic_page.lvt[APIC_LVT_TIMER].val) & APIC_LVTT_TM)
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return (((vlapic->apic_page.lvt[APIC_LVT_TIMER].v) & APIC_LVTT_TM)
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== APIC_LVTT_TM_TSCDLT);
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}
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static inline bool
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vlapic_lvtt_masked(struct acrn_vlapic *vlapic)
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{
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return ((vlapic->apic_page.lvt[APIC_LVT_TIMER].val) & APIC_LVTT_M)
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return ((vlapic->apic_page.lvt[APIC_LVT_TIMER].v) & APIC_LVTT_M)
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!= 0U;
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}
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@ -381,7 +382,7 @@ static void vlapic_dcr_write_handler(struct acrn_vlapic *vlapic)
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struct lapic_regs *lapic = &(vlapic->apic_page);
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vtimer = &vlapic->vtimer;
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divisor_shift = vlapic_timer_divisor_shift(lapic->dcr_timer);
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divisor_shift = vlapic_timer_divisor_shift(lapic->dcr_timer.v);
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vtimer->divisor_shift = divisor_shift;
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}
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@ -397,7 +398,7 @@ static void vlapic_icrtmr_write_handler(struct acrn_vlapic *vlapic)
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lapic = &(vlapic->apic_page);
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vtimer = &vlapic->vtimer;
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vtimer->tmicr = lapic->icr_timer;
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vtimer->tmicr = lapic->icr_timer.v;
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del_timer(&vtimer->timer);
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if (set_expiration(vlapic)) {
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@ -455,7 +456,7 @@ vlapic_esr_write_handler(struct acrn_vlapic *vlapic)
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struct lapic_regs *lapic;
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lapic = &(vlapic->apic_page);
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lapic->esr = vlapic->esr_pending;
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lapic->esr.v = vlapic->esr_pending;
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vlapic->esr_pending = 0U;
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}
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@ -474,7 +475,7 @@ vlapic_set_intr_ready(struct acrn_vlapic *vlapic, uint32_t vector, bool level)
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"invalid vector %u", vector);
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lapic = &(vlapic->apic_page);
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if ((lapic->svr & APIC_SVR_ENABLE) == 0U) {
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if ((lapic->svr.v & APIC_SVR_ENABLE) == 0U) {
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dev_dbg(ACRN_DBG_LAPIC,
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"vlapic is software disabled, ignoring interrupt %u",
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vector);
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@ -498,7 +499,7 @@ vlapic_set_intr_ready(struct acrn_vlapic *vlapic, uint32_t vector, bool level)
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irrptr = &lapic->irr[0];
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/* If the interrupt is set, don't try to do it again */
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if (bitmap32_test_and_set_lock((uint16_t)(vector & 0x1fU),
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&irrptr[idx].val)) {
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&irrptr[idx].v)) {
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return 0;
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}
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@ -507,10 +508,10 @@ vlapic_set_intr_ready(struct acrn_vlapic *vlapic, uint32_t vector, bool level)
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* the vlapic TMR registers.
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*/
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tmrptr = &lapic->tmr[0];
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if ((tmrptr[idx].val & mask) != (level ? mask : 0U)) {
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if ((tmrptr[idx].v & mask) != (level ? mask : 0U)) {
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dev_dbg(ACRN_DBG_LAPIC,
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"vlapic TMR[%u] is 0x%08x but interrupt is %s-triggered",
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idx, tmrptr[idx].val, level ? "level" : "edge");
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idx, tmrptr[idx].v, level ? "level" : "edge");
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}
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vlapic_dump_irr(vlapic, "vlapic_set_intr_ready");
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@ -568,7 +569,7 @@ vlapic_get_lvtptr(struct acrn_vlapic *vlapic, uint32_t offset)
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switch (offset) {
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case APIC_OFFSET_CMCI_LVT:
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return &lapic->lvt_cmci;
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return &lapic->lvt_cmci.v;
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case APIC_OFFSET_TIMER_LVT:
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case APIC_OFFSET_THERM_LVT:
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case APIC_OFFSET_PERF_LVT:
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@ -576,7 +577,7 @@ vlapic_get_lvtptr(struct acrn_vlapic *vlapic, uint32_t offset)
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case APIC_OFFSET_LINT1_LVT:
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case APIC_OFFSET_ERROR_LVT:
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i = lvt_off_to_idx(offset);
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return &(lapic->lvt[i].val);
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return &(lapic->lvt[i].v);
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default:
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panic("vlapic_get_lvt: invalid LVT\n");
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}
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@ -603,7 +604,7 @@ vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
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val = *lvtptr;
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idx = lvt_off_to_idx(offset);
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if ((lapic->svr & APIC_SVR_ENABLE) == 0U) {
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if ((lapic->svr.v & APIC_SVR_ENABLE) == 0U) {
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val |= APIC_LVT_M;
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}
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mask = APIC_LVT_M | APIC_LVT_DS | APIC_LVT_VECTOR;
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@ -664,25 +665,25 @@ vlapic_mask_lvts(struct acrn_vlapic *vlapic)
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{
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struct lapic_regs *lapic = &(vlapic->apic_page);
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lapic->lvt_cmci |= APIC_LVT_M;
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lapic->lvt_cmci.v |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_CMCI_LVT);
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lapic->lvt[APIC_LVT_TIMER].val |= APIC_LVT_M;
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lapic->lvt[APIC_LVT_TIMER].v |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_TIMER_LVT);
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lapic->lvt[APIC_LVT_THERMAL].val |= APIC_LVT_M;
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lapic->lvt[APIC_LVT_THERMAL].v |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_THERM_LVT);
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lapic->lvt[APIC_LVT_PMC].val |= APIC_LVT_M;
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lapic->lvt[APIC_LVT_PMC].v |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_PERF_LVT);
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lapic->lvt[APIC_LVT_LINT0].val |= APIC_LVT_M;
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lapic->lvt[APIC_LVT_LINT0].v |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT0_LVT);
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lapic->lvt[APIC_LVT_LINT1].val |= APIC_LVT_M;
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lapic->lvt[APIC_LVT_LINT1].v |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT1_LVT);
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lapic->lvt[APIC_LVT_ERROR].val |= APIC_LVT_M;
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lapic->lvt[APIC_LVT_ERROR].v |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_ERROR_LVT);
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}
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@ -730,7 +731,7 @@ dump_isrvec_stk(struct acrn_vlapic *vlapic)
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isrptr = &(vlapic->apic_page.isr[0]);
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for (i = 0U; i < 8U; i++) {
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printf("ISR%u 0x%08x\n", i, isrptr[i].val);
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printf("ISR%u 0x%08x\n", i, isrptr[i].v);
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}
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for (i = 0U; i <= vlapic->isrvec_stk_top; i++) {
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@ -755,7 +756,7 @@ vlapic_update_ppr(struct acrn_vlapic *vlapic)
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* bits is set in the ISRx registers.
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*/
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top_isrvec = (uint32_t)vlapic->isrvec_stk[vlapic->isrvec_stk_top];
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tpr = vlapic->apic_page.tpr;
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tpr = vlapic->apic_page.tpr.v;
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/* update ppr */
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{
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@ -791,7 +792,7 @@ vlapic_update_ppr(struct acrn_vlapic *vlapic)
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isrptr = &(vlapic->apic_page.isr[0]);
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for (vector = 0U; vector < 256U; vector++) {
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idx = vector >> 5U;
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if ((isrptr[idx].val & (1U << (vector & 0x1fU)))
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if ((isrptr[idx].v & (1U << (vector & 0x1fU)))
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!= 0U) {
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isrvec = (uint32_t)vlapic->isrvec_stk[i];
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if ((i > vlapic->isrvec_stk_top) ||
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@ -811,7 +812,7 @@ vlapic_update_ppr(struct acrn_vlapic *vlapic)
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ppr = top_isrvec & 0xf0U;
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}
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vlapic->apic_page.ppr = ppr;
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vlapic->apic_page.ppr.v = ppr;
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dev_dbg(ACRN_DBG_LAPIC, "%s 0x%02x", __func__, ppr);
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}
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@ -828,19 +829,19 @@ vlapic_process_eoi(struct acrn_vlapic *vlapic)
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/* i ranges effectively from 7 to 0 */
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for (i = 8U; i > 0U; ) {
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i--;
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bitpos = (uint32_t)fls32(isrptr[i].val);
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bitpos = (uint32_t)fls32(isrptr[i].v);
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if (bitpos != INVALID_BIT_INDEX) {
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if (vlapic->isrvec_stk_top == 0U) {
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panic("invalid vlapic isrvec_stk_top %u",
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vlapic->isrvec_stk_top);
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}
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isrptr[i].val &= ~(1U << bitpos);
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isrptr[i].v &= ~(1U << bitpos);
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vector = (i * 32U) + bitpos;
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dev_dbg(ACRN_DBG_LAPIC, "EOI vector %u", vector);
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vlapic_dump_isr(vlapic, "vlapic_process_eoi");
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vlapic->isrvec_stk_top--;
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vlapic_update_ppr(vlapic);
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if ((tmrptr[i].val & (1U << bitpos)) != 0U) {
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if ((tmrptr[i].v & (1U << bitpos)) != 0U) {
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/* hook to vIOAPIC */
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vioapic_process_eoi(vlapic->vm, vector);
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}
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@ -986,8 +987,8 @@ vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
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bitmap_clear_lock(vcpu_id, &amask);
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vlapic = vm_lapic_from_vcpu_id(vm, vcpu_id);
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dfr = vlapic->apic_page.dfr;
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ldr = vlapic->apic_page.ldr;
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dfr = vlapic->apic_page.dfr.v;
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ldr = vlapic->apic_page.ldr.v;
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if ((dfr & APIC_DFR_MODEL_MASK) ==
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APIC_DFR_MODEL_FLAT) {
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@ -1019,8 +1020,8 @@ vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
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if (lowprio) {
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if (target == NULL) {
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target = vlapic;
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} else if (target->apic_page.ppr >
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vlapic->apic_page.ppr) {
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} else if (target->apic_page.ppr.v >
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vlapic->apic_page.ppr.v) {
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target = vlapic;
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} else {
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/* target is the dest */
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@ -1048,10 +1049,10 @@ vlapic_set_tpr(struct acrn_vlapic *vlapic, uint32_t val)
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{
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struct lapic_regs *lapic = &(vlapic->apic_page);
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if (lapic->tpr != val) {
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if (lapic->tpr.v != val) {
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dev_dbg(ACRN_DBG_LAPIC,
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"vlapic TPR changed from %#x to %#x", lapic->tpr, val);
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lapic->tpr = val;
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lapic->tpr.v = val;
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vlapic_update_ppr(vlapic);
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}
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}
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@ -1061,7 +1062,7 @@ vlapic_get_tpr(struct acrn_vlapic *vlapic)
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{
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struct lapic_regs *lapic = &(vlapic->apic_page);
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return lapic->tpr;
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return lapic->tpr.v;
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}
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void
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@ -1101,10 +1102,10 @@ vlapic_icrlo_write_handler(struct acrn_vlapic *vlapic)
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struct vcpu *target_vcpu;
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lapic = &(vlapic->apic_page);
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lapic->icr_lo &= ~APIC_DELSTAT_PEND;
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lapic->icr_lo.v &= ~APIC_DELSTAT_PEND;
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icr_low = lapic->icr_lo;
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icr_high = lapic->icr_hi;
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icr_low = lapic->icr_lo.v;
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icr_high = lapic->icr_hi.v;
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dest = icr_high >> APIC_ID_SHIFT;
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vec = icr_low & APIC_VECTOR_MASK;
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mode = icr_low & APIC_DELMODE_MASK;
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@ -1233,11 +1234,11 @@ vlapic_pending_intr(struct acrn_vlapic *vlapic, uint32_t *vecptr)
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/* i ranges effectively from 7 to 0 */
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for (i = 8U; i > 0U; ) {
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i--;
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val = atomic_load32(&irrptr[i].val);
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val = atomic_load32(&irrptr[i].v);
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bitpos = (uint32_t)fls32(val);
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if (bitpos != INVALID_BIT_INDEX) {
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vector = (i * 32U) + bitpos;
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if (prio(vector) > prio(lapic->ppr)) {
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if (prio(vector) > prio(lapic->ppr.v)) {
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if (vecptr != NULL) {
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*vecptr = vector;
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}
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@ -1263,11 +1264,11 @@ vlapic_intr_accepted(struct acrn_vlapic *vlapic, uint32_t vector)
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idx = vector >> 5U;
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irrptr = &lapic->irr[0];
|
||||
atomic_clear32(&irrptr[idx].val, 1U << (vector & 0x1fU));
|
||||
atomic_clear32(&irrptr[idx].v, 1U << (vector & 0x1fU));
|
||||
vlapic_dump_irr(vlapic, "vlapic_intr_accepted");
|
||||
|
||||
isrptr = &lapic->isr[0];
|
||||
isrptr[idx].val |= 1U << (vector & 0x1fU);
|
||||
isrptr[idx].v |= 1U << (vector & 0x1fU);
|
||||
vlapic_dump_isr(vlapic, "vlapic_intr_accepted");
|
||||
|
||||
/*
|
||||
@ -1292,7 +1293,7 @@ vlapic_svr_write_handler(struct acrn_vlapic *vlapic)
|
||||
|
||||
lapic = &(vlapic->apic_page);
|
||||
|
||||
new = lapic->svr;
|
||||
new = lapic->svr.v;
|
||||
old = vlapic->svr_last;
|
||||
vlapic->svr_last = new;
|
||||
|
||||
@ -1348,31 +1349,31 @@ vlapic_read(struct acrn_vlapic *vlapic, uint32_t offset_arg,
|
||||
offset &= ~0x3UL;
|
||||
switch (offset) {
|
||||
case APIC_OFFSET_ID:
|
||||
*data = lapic->id;
|
||||
*data = lapic->id.v;
|
||||
break;
|
||||
case APIC_OFFSET_VER:
|
||||
*data = lapic->version;
|
||||
*data = lapic->version.v;
|
||||
break;
|
||||
case APIC_OFFSET_TPR:
|
||||
*data = vlapic_get_tpr(vlapic);
|
||||
break;
|
||||
case APIC_OFFSET_APR:
|
||||
*data = lapic->apr;
|
||||
*data = lapic->apr.v;
|
||||
break;
|
||||
case APIC_OFFSET_PPR:
|
||||
*data = lapic->ppr;
|
||||
*data = lapic->ppr.v;
|
||||
break;
|
||||
case APIC_OFFSET_EOI:
|
||||
*data = lapic->eoi;
|
||||
*data = lapic->eoi.v;
|
||||
break;
|
||||
case APIC_OFFSET_LDR:
|
||||
*data = lapic->ldr;
|
||||
*data = lapic->ldr.v;
|
||||
break;
|
||||
case APIC_OFFSET_DFR:
|
||||
*data = lapic->dfr;
|
||||
*data = lapic->dfr.v;
|
||||
break;
|
||||
case APIC_OFFSET_SVR:
|
||||
*data = lapic->svr;
|
||||
*data = lapic->svr.v;
|
||||
break;
|
||||
case APIC_OFFSET_ISR0:
|
||||
case APIC_OFFSET_ISR1:
|
||||
@ -1383,7 +1384,7 @@ vlapic_read(struct acrn_vlapic *vlapic, uint32_t offset_arg,
|
||||
case APIC_OFFSET_ISR6:
|
||||
case APIC_OFFSET_ISR7:
|
||||
i = (offset - APIC_OFFSET_ISR0) >> 4;
|
||||
*data = lapic->isr[i].val;
|
||||
*data = lapic->isr[i].v;
|
||||
break;
|
||||
case APIC_OFFSET_TMR0:
|
||||
case APIC_OFFSET_TMR1:
|
||||
@ -1394,7 +1395,7 @@ vlapic_read(struct acrn_vlapic *vlapic, uint32_t offset_arg,
|
||||
case APIC_OFFSET_TMR6:
|
||||
case APIC_OFFSET_TMR7:
|
||||
i = (offset - APIC_OFFSET_TMR0) >> 4;
|
||||
*data = lapic->tmr[i].val;
|
||||
*data = lapic->tmr[i].v;
|
||||
break;
|
||||
case APIC_OFFSET_IRR0:
|
||||
case APIC_OFFSET_IRR1:
|
||||
@ -1405,16 +1406,16 @@ vlapic_read(struct acrn_vlapic *vlapic, uint32_t offset_arg,
|
||||
case APIC_OFFSET_IRR6:
|
||||
case APIC_OFFSET_IRR7:
|
||||
i = (offset - APIC_OFFSET_IRR0) >> 4;
|
||||
*data = lapic->irr[i].val;
|
||||
*data = lapic->irr[i].v;
|
||||
break;
|
||||
case APIC_OFFSET_ESR:
|
||||
*data = lapic->esr;
|
||||
*data = lapic->esr.v;
|
||||
break;
|
||||
case APIC_OFFSET_ICR_LOW:
|
||||
*data = lapic->icr_lo;
|
||||
*data = lapic->icr_lo.v;
|
||||
break;
|
||||
case APIC_OFFSET_ICR_HI:
|
||||
*data = lapic->icr_hi;
|
||||
*data = lapic->icr_hi.v;
|
||||
break;
|
||||
case APIC_OFFSET_CMCI_LVT:
|
||||
case APIC_OFFSET_TIMER_LVT:
|
||||
@ -1436,14 +1437,14 @@ vlapic_read(struct acrn_vlapic *vlapic, uint32_t offset_arg,
|
||||
if (vlapic_lvtt_tsc_deadline(vlapic)) {
|
||||
*data = 0UL;
|
||||
} else {
|
||||
*data = lapic->icr_timer;
|
||||
*data = lapic->icr_timer.v;
|
||||
}
|
||||
break;
|
||||
case APIC_OFFSET_TIMER_CCR:
|
||||
*data = vlapic_get_ccr(vlapic);
|
||||
break;
|
||||
case APIC_OFFSET_TIMER_DCR:
|
||||
*data = lapic->dcr_timer;
|
||||
*data = lapic->dcr_timer.v;
|
||||
break;
|
||||
case APIC_OFFSET_RRR:
|
||||
default:
|
||||
@ -1487,23 +1488,23 @@ vlapic_write(struct acrn_vlapic *vlapic, uint32_t offset,
|
||||
vlapic_process_eoi(vlapic);
|
||||
break;
|
||||
case APIC_OFFSET_LDR:
|
||||
lapic->ldr = data32;
|
||||
lapic->ldr.v = data32;
|
||||
vlapic_ldr_write_handler(vlapic);
|
||||
break;
|
||||
case APIC_OFFSET_DFR:
|
||||
lapic->dfr = data32;
|
||||
lapic->dfr.v = data32;
|
||||
vlapic_dfr_write_handler(vlapic);
|
||||
break;
|
||||
case APIC_OFFSET_SVR:
|
||||
lapic->svr = data32;
|
||||
lapic->svr.v = data32;
|
||||
vlapic_svr_write_handler(vlapic);
|
||||
break;
|
||||
case APIC_OFFSET_ICR_LOW:
|
||||
lapic->icr_lo = data32;
|
||||
lapic->icr_lo.v = data32;
|
||||
retval = vlapic_icrlo_write_handler(vlapic);
|
||||
break;
|
||||
case APIC_OFFSET_ICR_HI:
|
||||
lapic->icr_hi = data32;
|
||||
lapic->icr_hi.v = data32;
|
||||
break;
|
||||
case APIC_OFFSET_CMCI_LVT:
|
||||
case APIC_OFFSET_TIMER_LVT:
|
||||
@ -1521,12 +1522,12 @@ vlapic_write(struct acrn_vlapic *vlapic, uint32_t offset,
|
||||
if (vlapic_lvtt_tsc_deadline(vlapic)) {
|
||||
break;
|
||||
}
|
||||
lapic->icr_timer = data32;
|
||||
lapic->icr_timer.v = data32;
|
||||
vlapic_icrtmr_write_handler(vlapic);
|
||||
break;
|
||||
|
||||
case APIC_OFFSET_TIMER_DCR:
|
||||
lapic->dcr_timer = data32;
|
||||
lapic->dcr_timer.v = data32;
|
||||
vlapic_dcr_write_handler(vlapic);
|
||||
break;
|
||||
|
||||
@ -1564,19 +1565,19 @@ vlapic_reset(struct acrn_vlapic *vlapic)
|
||||
(void)memset((void *)lapic, 0U, CPU_PAGE_SIZE);
|
||||
(void)memset((void *)&(vlapic->pir_desc), 0U, sizeof(vlapic->pir_desc));
|
||||
|
||||
lapic->id = vlapic_build_id(vlapic);
|
||||
lapic->version = VLAPIC_VERSION;
|
||||
lapic->version |= (VLAPIC_MAXLVT_INDEX << MAXLVTSHIFT);
|
||||
lapic->dfr = 0xffffffffU;
|
||||
lapic->svr = APIC_SVR_VECTOR;
|
||||
lapic->id.v = vlapic_build_id(vlapic);
|
||||
lapic->version.v = VLAPIC_VERSION;
|
||||
lapic->version.v |= (VLAPIC_MAXLVT_INDEX << MAXLVTSHIFT);
|
||||
lapic->dfr.v = 0xffffffffU;
|
||||
lapic->svr.v = APIC_SVR_VECTOR;
|
||||
vlapic_mask_lvts(vlapic);
|
||||
vlapic_reset_tmr(vlapic);
|
||||
|
||||
lapic->icr_timer = 0U;
|
||||
lapic->dcr_timer = 0U;
|
||||
lapic->icr_timer.v = 0U;
|
||||
lapic->dcr_timer.v = 0U;
|
||||
vlapic_reset_timer(vlapic);
|
||||
|
||||
vlapic->svr_last = lapic->svr;
|
||||
vlapic->svr_last = lapic->svr.v;
|
||||
|
||||
for (i = 0U; i < (VLAPIC_MAXLVT_INDEX + 1U); i++) {
|
||||
vlapic->lvt_last[i] = 0U;
|
||||
@ -1626,14 +1627,14 @@ void vlapic_restore(struct acrn_vlapic *vlapic, struct lapic_regs *regs)
|
||||
lapic->ldr = regs->ldr;
|
||||
lapic->dfr = regs->dfr;
|
||||
for (i = 0; i < 8; i++) {
|
||||
lapic->tmr[i].val = regs->tmr[i].val;
|
||||
lapic->tmr[i].v = regs->tmr[i].v;
|
||||
}
|
||||
lapic->svr = regs->svr;
|
||||
vlapic_svr_write_handler(vlapic);
|
||||
lapic->lvt[APIC_LVT_TIMER].val = regs->lvt[APIC_LVT_TIMER].val;
|
||||
lapic->lvt[APIC_LVT_LINT0].val = regs->lvt[APIC_LVT_LINT0].val;
|
||||
lapic->lvt[APIC_LVT_LINT1].val = regs->lvt[APIC_LVT_LINT1].val;
|
||||
lapic->lvt[APIC_LVT_ERROR].val = regs->lvt[APIC_LVT_ERROR].val;
|
||||
lapic->lvt[APIC_LVT_TIMER].v = regs->lvt[APIC_LVT_TIMER].v;
|
||||
lapic->lvt[APIC_LVT_LINT0].v = regs->lvt[APIC_LVT_LINT0].v;
|
||||
lapic->lvt[APIC_LVT_LINT1].v = regs->lvt[APIC_LVT_LINT1].v;
|
||||
lapic->lvt[APIC_LVT_ERROR].v = regs->lvt[APIC_LVT_ERROR].v;
|
||||
lapic->icr_timer = regs->icr_timer;
|
||||
lapic->ccr_timer = regs->ccr_timer;
|
||||
lapic->dcr_timer = regs->dcr_timer;
|
||||
@ -1712,7 +1713,7 @@ vlapic_enabled(struct acrn_vlapic *vlapic)
|
||||
struct lapic_regs *lapic = &(vlapic->apic_page);
|
||||
|
||||
if (((vlapic->msr_apicbase & APICBASE_ENABLED) != 0U) &&
|
||||
((lapic->svr & APIC_SVR_ENABLE) != 0U)) {
|
||||
((lapic->svr.v & APIC_SVR_ENABLE) != 0U)) {
|
||||
return true;
|
||||
} else {
|
||||
return false;
|
||||
@ -1731,9 +1732,9 @@ vlapic_set_tmr(struct acrn_vlapic *vlapic, uint32_t vector, bool level)
|
||||
idx = vector >> 5U;
|
||||
mask = 1U << (vector & 0x1fU);
|
||||
if (level) {
|
||||
tmrptr[idx].val |= mask;
|
||||
tmrptr[idx].v |= mask;
|
||||
} else {
|
||||
tmrptr[idx].val &= ~mask;
|
||||
tmrptr[idx].v &= ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1903,7 +1904,8 @@ static void vlapic_timer_expired(void *data)
|
||||
|
||||
/* inject vcpu timer interrupt if not masked */
|
||||
if (!vlapic_lvtt_masked(vlapic)) {
|
||||
vlapic_intr_edge(vcpu, lapic->lvt[APIC_LVT_TIMER].val & APIC_LVTT_VECTOR);
|
||||
vlapic_intr_edge(vcpu,
|
||||
lapic->lvt[APIC_LVT_TIMER].v & APIC_LVTT_VECTOR);
|
||||
}
|
||||
|
||||
if (!vlapic_lvtt_period(vlapic)) {
|
||||
@ -2041,7 +2043,7 @@ apicv_pending_intr(struct acrn_vlapic *vlapic, __unused uint32_t *vecptr)
|
||||
}
|
||||
|
||||
lapic = &(vlapic->apic_page);
|
||||
ppr = lapic->ppr & 0xF0U;
|
||||
ppr = lapic->ppr.v & 0xF0U;
|
||||
|
||||
if (ppr == 0U) {
|
||||
return 1;
|
||||
@ -2076,9 +2078,9 @@ apicv_batch_set_tmr(struct acrn_vlapic *vlapic)
|
||||
e = 256U;
|
||||
|
||||
while (s < e) {
|
||||
val = ptr[(s/TMR_STEP_LEN) + 1].val;
|
||||
val = ptr[(s/TMR_STEP_LEN) + 1].v;
|
||||
val <<= TMR_STEP_LEN;
|
||||
val |= ptr[s/TMR_STEP_LEN].val;
|
||||
val |= ptr[s/TMR_STEP_LEN].v;
|
||||
exec_vmwrite64(vmx_eoi_exit(s), val);
|
||||
|
||||
s += EOI_STEP_LEN;
|
||||
@ -2130,8 +2132,8 @@ vlapic_apicv_inject_pir(struct acrn_vlapic *vlapic)
|
||||
for (i = 0U; i < 4U; i++) {
|
||||
val = atomic_readandclear64(&pir_desc->pir[i]);
|
||||
if (val != 0UL) {
|
||||
irr[i * 2U].val |= (uint32_t)val;
|
||||
irr[(i * 2U) + 1U].val |= (uint32_t)(val >> 32);
|
||||
irr[i * 2U].v |= (uint32_t)val;
|
||||
irr[(i * 2U) + 1U].v |= (uint32_t)(val >> 32);
|
||||
|
||||
pirbase = 64U*i;
|
||||
pirval = val;
|
||||
@ -2237,7 +2239,7 @@ int veoi_vmexit_handler(struct vcpu *vcpu)
|
||||
idx = vector >> 5U;
|
||||
mask = 1U << (vector & 0x1fU);
|
||||
|
||||
if ((tmrptr[idx].val & mask) != 0U) {
|
||||
if ((tmrptr[idx].v & mask) != 0U) {
|
||||
/* hook to vIOAPIC */
|
||||
vioapic_process_eoi(vlapic->vm, vector);
|
||||
}
|
||||
|
||||
@ -241,66 +241,68 @@ void init_lapic(uint16_t pcpu_id)
|
||||
|
||||
void save_lapic(struct lapic_regs *regs)
|
||||
{
|
||||
regs->id = read_lapic_reg32(LAPIC_ID_REGISTER);
|
||||
regs->tpr = read_lapic_reg32(LAPIC_TASK_PRIORITY_REGISTER);
|
||||
regs->apr = read_lapic_reg32(LAPIC_ARBITRATION_PRIORITY_REGISTER);
|
||||
regs->ppr = read_lapic_reg32(LAPIC_PROCESSOR_PRIORITY_REGISTER);
|
||||
regs->ldr = read_lapic_reg32(LAPIC_LOGICAL_DESTINATION_REGISTER);
|
||||
regs->dfr = read_lapic_reg32(LAPIC_DESTINATION_FORMAT_REGISTER);
|
||||
regs->tmr[0].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_0);
|
||||
regs->tmr[1].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_1);
|
||||
regs->tmr[2].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_2);
|
||||
regs->tmr[3].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_3);
|
||||
regs->tmr[4].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_4);
|
||||
regs->tmr[5].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_5);
|
||||
regs->tmr[6].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_6);
|
||||
regs->tmr[7].val = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_7);
|
||||
regs->svr = read_lapic_reg32(LAPIC_SPURIOUS_VECTOR_REGISTER);
|
||||
regs->lvt[APIC_LVT_TIMER].val =
|
||||
regs->id.v = read_lapic_reg32(LAPIC_ID_REGISTER);
|
||||
regs->tpr.v = read_lapic_reg32(LAPIC_TASK_PRIORITY_REGISTER);
|
||||
regs->apr.v = read_lapic_reg32(LAPIC_ARBITRATION_PRIORITY_REGISTER);
|
||||
regs->ppr.v = read_lapic_reg32(LAPIC_PROCESSOR_PRIORITY_REGISTER);
|
||||
regs->ldr.v = read_lapic_reg32(LAPIC_LOGICAL_DESTINATION_REGISTER);
|
||||
regs->dfr.v = read_lapic_reg32(LAPIC_DESTINATION_FORMAT_REGISTER);
|
||||
regs->tmr[0].v = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_0);
|
||||
regs->tmr[1].v = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_1);
|
||||
regs->tmr[2].v = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_2);
|
||||
regs->tmr[3].v = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_3);
|
||||
regs->tmr[4].v = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_4);
|
||||
regs->tmr[5].v = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_5);
|
||||
regs->tmr[6].v = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_6);
|
||||
regs->tmr[7].v = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_7);
|
||||
regs->svr.v = read_lapic_reg32(LAPIC_SPURIOUS_VECTOR_REGISTER);
|
||||
regs->lvt[APIC_LVT_TIMER].v =
|
||||
read_lapic_reg32(LAPIC_LVT_TIMER_REGISTER);
|
||||
regs->lvt[APIC_LVT_LINT0].val =
|
||||
regs->lvt[APIC_LVT_LINT0].v =
|
||||
read_lapic_reg32(LAPIC_LVT_LINT0_REGISTER);
|
||||
regs->lvt[APIC_LVT_LINT1].val =
|
||||
regs->lvt[APIC_LVT_LINT1].v =
|
||||
read_lapic_reg32(LAPIC_LVT_LINT1_REGISTER);
|
||||
regs->lvt[APIC_LVT_ERROR].val =
|
||||
regs->lvt[APIC_LVT_ERROR].v =
|
||||
read_lapic_reg32(LAPIC_LVT_ERROR_REGISTER);
|
||||
regs->icr_timer = read_lapic_reg32(LAPIC_INITIAL_COUNT_REGISTER);
|
||||
regs->ccr_timer = read_lapic_reg32(LAPIC_CURRENT_COUNT_REGISTER);
|
||||
regs->dcr_timer = read_lapic_reg32(LAPIC_DIVIDE_CONFIGURATION_REGISTER);
|
||||
regs->icr_timer.v = read_lapic_reg32(LAPIC_INITIAL_COUNT_REGISTER);
|
||||
regs->ccr_timer.v = read_lapic_reg32(LAPIC_CURRENT_COUNT_REGISTER);
|
||||
regs->dcr_timer.v =
|
||||
read_lapic_reg32(LAPIC_DIVIDE_CONFIGURATION_REGISTER);
|
||||
}
|
||||
|
||||
static void restore_lapic(struct lapic_regs *regs)
|
||||
{
|
||||
write_lapic_reg32(LAPIC_ID_REGISTER, regs->id);
|
||||
write_lapic_reg32(LAPIC_TASK_PRIORITY_REGISTER, regs->tpr);
|
||||
write_lapic_reg32(LAPIC_LOGICAL_DESTINATION_REGISTER, regs->ldr );
|
||||
write_lapic_reg32(LAPIC_DESTINATION_FORMAT_REGISTER, regs->dfr );
|
||||
write_lapic_reg32(LAPIC_SPURIOUS_VECTOR_REGISTER, regs->svr );
|
||||
write_lapic_reg32(LAPIC_ID_REGISTER, regs->id.v);
|
||||
write_lapic_reg32(LAPIC_TASK_PRIORITY_REGISTER, regs->tpr.v);
|
||||
write_lapic_reg32(LAPIC_LOGICAL_DESTINATION_REGISTER, regs->ldr.v);
|
||||
write_lapic_reg32(LAPIC_DESTINATION_FORMAT_REGISTER, regs->dfr.v);
|
||||
write_lapic_reg32(LAPIC_SPURIOUS_VECTOR_REGISTER, regs->svr.v);
|
||||
write_lapic_reg32(LAPIC_LVT_TIMER_REGISTER,
|
||||
regs->lvt[APIC_LVT_TIMER].val);
|
||||
regs->lvt[APIC_LVT_TIMER].v);
|
||||
|
||||
write_lapic_reg32(LAPIC_LVT_LINT0_REGISTER,
|
||||
regs->lvt[APIC_LVT_LINT0].val);
|
||||
regs->lvt[APIC_LVT_LINT0].v);
|
||||
write_lapic_reg32(LAPIC_LVT_LINT1_REGISTER,
|
||||
regs->lvt[APIC_LVT_LINT1].val);
|
||||
regs->lvt[APIC_LVT_LINT1].v);
|
||||
|
||||
write_lapic_reg32(LAPIC_LVT_ERROR_REGISTER,
|
||||
regs->lvt[APIC_LVT_ERROR].val);
|
||||
write_lapic_reg32(LAPIC_INITIAL_COUNT_REGISTER, regs->icr_timer);
|
||||
write_lapic_reg32(LAPIC_DIVIDE_CONFIGURATION_REGISTER, regs->dcr_timer);
|
||||
regs->lvt[APIC_LVT_ERROR].v);
|
||||
write_lapic_reg32(LAPIC_INITIAL_COUNT_REGISTER, regs->icr_timer.v);
|
||||
write_lapic_reg32(LAPIC_DIVIDE_CONFIGURATION_REGISTER,
|
||||
regs->dcr_timer.v);
|
||||
|
||||
|
||||
write_lapic_reg32(LAPIC_ARBITRATION_PRIORITY_REGISTER, regs->apr);
|
||||
write_lapic_reg32(LAPIC_PROCESSOR_PRIORITY_REGISTER, regs->ppr);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_0, regs->tmr[0].val);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_1, regs->tmr[1].val);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_2, regs->tmr[2].val);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_3, regs->tmr[3].val);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_4, regs->tmr[4].val);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_5, regs->tmr[5].val);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_6, regs->tmr[6].val);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_7, regs->tmr[7].val);
|
||||
write_lapic_reg32(LAPIC_CURRENT_COUNT_REGISTER, regs->ccr_timer);
|
||||
write_lapic_reg32(LAPIC_ARBITRATION_PRIORITY_REGISTER, regs->apr.v);
|
||||
write_lapic_reg32(LAPIC_PROCESSOR_PRIORITY_REGISTER, regs->ppr.v);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_0, regs->tmr[0].v);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_1, regs->tmr[1].v);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_2, regs->tmr[2].v);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_3, regs->tmr[3].v);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_4, regs->tmr[4].v);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_5, regs->tmr[5].v);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_6, regs->tmr[6].v);
|
||||
write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_7, regs->tmr[7].v);
|
||||
write_lapic_reg32(LAPIC_CURRENT_COUNT_REGISTER, regs->ccr_timer.v);
|
||||
}
|
||||
|
||||
void suspend_lapic(void)
|
||||
|
||||
@ -118,55 +118,38 @@
|
||||
/******************************************************************************
|
||||
* LOCAL APIC structure
|
||||
*/
|
||||
|
||||
#ifndef LOCORE
|
||||
|
||||
#define PAD3 uint32_t: 32; uint32_t: 32; uint32_t: 32
|
||||
#define PAD4 uint32_t: 32; uint32_t: 32; uint32_t: 32; uint32_t: 32
|
||||
|
||||
struct lapic_reg {
|
||||
uint32_t val; PAD3;
|
||||
uint32_t v;
|
||||
uint32_t pad[3];
|
||||
};
|
||||
|
||||
struct lapic_regs {
|
||||
/* reserved */ PAD4;
|
||||
/* reserved */ PAD4;
|
||||
uint32_t id; PAD3;
|
||||
uint32_t version; PAD3;
|
||||
/* reserved */ PAD4;
|
||||
/* reserved */ PAD4;
|
||||
/* reserved */ PAD4;
|
||||
/* reserved */ PAD4;
|
||||
uint32_t tpr; PAD3;
|
||||
uint32_t apr; PAD3;
|
||||
uint32_t ppr; PAD3;
|
||||
uint32_t eoi; PAD3;
|
||||
/* reserved */ PAD4;
|
||||
uint32_t ldr; PAD3;
|
||||
uint32_t dfr; PAD3;
|
||||
uint32_t svr; PAD3;
|
||||
struct lapic_reg rsv0[2];
|
||||
struct lapic_reg id;
|
||||
struct lapic_reg version;
|
||||
struct lapic_reg rsv1[4];
|
||||
struct lapic_reg tpr;
|
||||
struct lapic_reg apr;
|
||||
struct lapic_reg ppr;
|
||||
struct lapic_reg eoi;
|
||||
struct lapic_reg rsv2;
|
||||
struct lapic_reg ldr;
|
||||
struct lapic_reg dfr;
|
||||
struct lapic_reg svr;
|
||||
struct lapic_reg isr[8];
|
||||
struct lapic_reg tmr[8];
|
||||
struct lapic_reg irr[8];
|
||||
uint32_t esr; PAD3;
|
||||
/* reserved */ PAD4;
|
||||
/* reserved */ PAD4;
|
||||
/* reserved */ PAD4;
|
||||
/* reserved */ PAD4;
|
||||
/* reserved */ PAD4;
|
||||
/* reserved */ PAD4;
|
||||
uint32_t lvt_cmci; PAD3;
|
||||
uint32_t icr_lo; PAD3;
|
||||
uint32_t icr_hi; PAD3;
|
||||
struct lapic_reg esr;
|
||||
struct lapic_reg rsv3[6];
|
||||
struct lapic_reg lvt_cmci;
|
||||
struct lapic_reg icr_lo;
|
||||
struct lapic_reg icr_hi;
|
||||
struct lapic_reg lvt[6];
|
||||
uint32_t icr_timer; PAD3;
|
||||
uint32_t ccr_timer; PAD3;
|
||||
/* reserved */ PAD4;
|
||||
/* reserved */ PAD4;
|
||||
/* reserved */ PAD4;
|
||||
/* reserved */ PAD4;
|
||||
uint32_t dcr_timer; PAD3;
|
||||
/* reserved */ PAD4;
|
||||
struct lapic_reg icr_timer;
|
||||
struct lapic_reg ccr_timer;
|
||||
struct lapic_reg rsv4[4];
|
||||
struct lapic_reg dcr_timer;
|
||||
struct lapic_reg rsv5;
|
||||
} __aligned(CPU_PAGE_SIZE);
|
||||
|
||||
enum LAPIC_REGISTERS {
|
||||
@ -249,8 +232,10 @@ enum LAPIC_REGISTERS {
|
||||
*/
|
||||
|
||||
struct ioapic {
|
||||
uint32_t ioregsel; PAD3;
|
||||
uint32_t iowin; PAD3;
|
||||
uint32_t ioregsel;
|
||||
uint32_t rsv0[3];
|
||||
uint32_t iowin;
|
||||
uint32_t rsv1[3];
|
||||
};
|
||||
|
||||
/* IOAPIC Redirection Table (RTE) Entry structure */
|
||||
@ -262,12 +247,6 @@ union ioapic_rte {
|
||||
} u;
|
||||
};
|
||||
|
||||
#undef PAD4
|
||||
#undef PAD3
|
||||
|
||||
#endif /* !LOCORE */
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* various code 'logical' values
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user