mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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HV:treewide:rename struct pic and iommu_domain
For data structure types "struct pic and struct iommu_domain", its name is identical with variable name in the same scope. This MISRA C violation is detected. Naming convention rule:If the data structure type is used by only one module and its name meaning is simplistic, its name needs prefix shorten module name. Naming convention rule:Variable name can be shortened from its data structure type name. The following udpates are made: struct pic pic-->struct i8259_reg_state i8259 struct iommu_domain iommu_domain-->struct iommu_domain iommu V1-->V2: Update "struct iommu_domain iommu_domain-->struct iommu_domain iommu" Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Xiangyang Wu
lijinxia
parent
17771c0ac2
commit
2c95a8c4aa
@ -268,9 +268,9 @@ int shutdown_vm(struct vm *vm)
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/* TODO: De-initialize I/O Emulation */
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free_io_emulation_resource(vm);
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/* Free iommu_domain */
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if (vm->iommu_domain != NULL) {
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destroy_iommu_domain(vm->iommu_domain);
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/* Free iommu */
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if (vm->iommu != NULL) {
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destroy_iommu_domain(vm->iommu);
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}
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bitmap_clear_lock(vm->attr.id, &vmid_bitmap);
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@ -45,7 +45,7 @@ enum irqstate {
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IRQSTATE_PULSE
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};
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struct pic {
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struct i8259_reg_state {
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bool ready;
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uint8_t icw_num;
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uint8_t rd_cmd_reg;
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@ -71,7 +71,7 @@ struct pic {
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struct acrn_vpic {
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struct vm *vm;
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spinlock_t lock;
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struct pic pic[2];
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struct i8259_reg_state i8259[2];
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};
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#define NR_VPIC_PINS_PER_CHIP 8U
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@ -81,36 +81,36 @@ struct acrn_vpic {
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/*
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* Loop over all the pins in priority order from highest to lowest.
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*/
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#define PIC_PIN_FOREACH(pinvar, pic, tmpvar) \
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for (tmpvar = 0U, pinvar = (pic->lowprio + 1U) & 0x7U; \
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#define PIC_PIN_FOREACH(pinvar, i8259, tmpvar) \
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for (tmpvar = 0U, pinvar = (i8259->lowprio + 1U) & 0x7U; \
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tmpvar < NR_VPIC_PINS_PER_CHIP; \
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tmpvar++, pinvar = (pinvar + 1U) & 0x7U)
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static void vpic_set_pinstate(struct acrn_vpic *vpic, uint8_t pin, bool newstate);
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static inline bool master_pic(struct acrn_vpic *vpic, struct pic *pic)
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static inline bool master_pic(struct acrn_vpic *vpic, struct i8259_reg_state *i8259)
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{
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if (pic == &vpic->pic[0]) {
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if (i8259 == &vpic->i8259[0]) {
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return true;
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} else {
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return false;
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}
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}
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static inline uint8_t vpic_get_highest_isrpin(struct pic *pic)
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static inline uint8_t vpic_get_highest_isrpin(struct i8259_reg_state *i8259)
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{
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uint8_t bit, pin, i;
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PIC_PIN_FOREACH(pin, pic, i) {
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PIC_PIN_FOREACH(pin, i8259, i) {
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bit = (uint8_t)(1U << pin);
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if ((pic->service & bit) != 0U) {
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if ((i8259->service & bit) != 0U) {
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/*
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* An IS bit that is masked by an IMR bit will not be
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* cleared by a non-specific EOI in Special Mask Mode.
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*/
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if ((pic->smm != 0U) && (pic->mask & bit) != 0U) {
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if ((i8259->smm != 0U) && (i8259->mask & bit) != 0U) {
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continue;
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} else {
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return pin;
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@ -121,7 +121,7 @@ static inline uint8_t vpic_get_highest_isrpin(struct pic *pic)
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return VPIC_INVALID_PIN;
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}
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static inline uint8_t vpic_get_highest_irrpin(struct pic *pic)
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static inline uint8_t vpic_get_highest_irrpin(struct i8259_reg_state *i8259)
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{
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uint8_t serviced, bit, pin, tmp;
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@ -130,8 +130,8 @@ static inline uint8_t vpic_get_highest_irrpin(struct pic *pic)
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* a slave is in service, the slave is not locked out from the
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* master's priority logic.
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*/
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serviced = pic->service;
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if (pic->sfn) {
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serviced = i8259->service;
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if (i8259->sfn) {
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serviced &= ~(uint8_t)(1U << 2U);
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}
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@ -141,11 +141,11 @@ static inline uint8_t vpic_get_highest_irrpin(struct pic *pic)
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* other levels that are not masked. In other words the ISR has no
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* bearing on the levels that can generate interrupts.
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*/
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if (pic->smm != 0U) {
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if (i8259->smm != 0U) {
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serviced = 0U;
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}
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PIC_PIN_FOREACH(pin, pic, tmp) {
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PIC_PIN_FOREACH(pin, i8259, tmp) {
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bit = (uint8_t)(1U << pin);
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/*
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@ -160,7 +160,7 @@ static inline uint8_t vpic_get_highest_irrpin(struct pic *pic)
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* If an interrupt is asserted and not masked then return
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* the corresponding 'pin' to the caller.
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*/
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if ((pic->request & bit) != 0 && (pic->mask & bit) == 0) {
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if ((i8259->request & bit) != 0 && (i8259->mask & bit) == 0) {
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return pin;
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}
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}
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@ -170,40 +170,40 @@ static inline uint8_t vpic_get_highest_irrpin(struct pic *pic)
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static void vpic_notify_intr(struct acrn_vpic *vpic)
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{
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struct pic *pic;
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struct i8259_reg_state *i8259;
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uint8_t pin;
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/*
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* First check the slave.
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*/
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pic = &vpic->pic[1];
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pin = vpic_get_highest_irrpin(pic);
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if (!pic->intr_raised && pin < NR_VPIC_PINS_PER_CHIP) {
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i8259 = &vpic->i8259[1];
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pin = vpic_get_highest_irrpin(i8259);
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if (!i8259->intr_raised && pin < NR_VPIC_PINS_PER_CHIP) {
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dev_dbg(ACRN_DBG_PIC,
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"pic slave notify pin = %hhu (imr 0x%x irr 0x%x isr 0x%x)\n",
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pin, pic->mask, pic->request, pic->service);
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pin, i8259->mask, i8259->request, i8259->service);
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/*
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* Cascade the request from the slave to the master.
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*/
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pic->intr_raised = true;
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i8259->intr_raised = true;
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vpic_set_pinstate(vpic, (uint8_t)2U, true);
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vpic_set_pinstate(vpic, (uint8_t)2U, false);
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} else {
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dev_dbg(ACRN_DBG_PIC,
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"pic slave no eligible interrupt (imr 0x%x irr 0x%x isr 0x%x)",
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pic->mask, pic->request, pic->service);
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i8259->mask, i8259->request, i8259->service);
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}
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/*
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* Then check the master.
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*/
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pic = &vpic->pic[0];
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pin = vpic_get_highest_irrpin(pic);
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if (!pic->intr_raised && pin < NR_VPIC_PINS_PER_CHIP) {
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i8259 = &vpic->i8259[0];
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pin = vpic_get_highest_irrpin(i8259);
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if (!i8259->intr_raised && pin < NR_VPIC_PINS_PER_CHIP) {
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dev_dbg(ACRN_DBG_PIC,
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"pic master notify pin = %hhu (imr 0x%x irr 0x%x isr 0x%x)\n",
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pin, pic->mask, pic->request, pic->service);
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pin, i8259->mask, i8259->request, i8259->service);
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/*
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* From Section 3.6.2, "Interrupt Modes", in the
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@ -230,7 +230,7 @@ static void vpic_notify_intr(struct acrn_vpic *vpic)
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* as ExtINT to indicate that the PIC is the source of the
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* interrupt.
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*/
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pic->intr_raised = true;
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i8259->intr_raised = true;
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if (vpic->vm->vpic_wire_mode == VPIC_WIRE_INTR) {
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struct vcpu *vcpu = vcpu_from_vid(vpic->vm, 0U);
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@ -248,24 +248,24 @@ static void vpic_notify_intr(struct acrn_vpic *vpic)
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} else {
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dev_dbg(ACRN_DBG_PIC,
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"pic master no eligible interrupt (imr 0x%x irr 0x%x isr 0x%x)",
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pic->mask, pic->request, pic->service);
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i8259->mask, i8259->request, i8259->service);
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}
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}
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static int vpic_icw1(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
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static int vpic_icw1(struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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{
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic icw1 0x%x\n",
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 icw1 0x%x\n",
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vpic->vm, val);
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pic->ready = false;
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i8259->ready = false;
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pic->icw_num = 1U;
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pic->request = 0U;
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pic->mask = 0U;
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pic->lowprio = 7U;
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pic->rd_cmd_reg = 0U;
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pic->poll = false;
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pic->smm = 0U;
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i8259->icw_num = 1U;
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i8259->request = 0U;
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i8259->mask = 0U;
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i8259->lowprio = 7U;
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i8259->rd_cmd_reg = 0U;
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i8259->poll = false;
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i8259->smm = 0U;
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if ((val & ICW1_SNGL) != 0) {
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dev_dbg(ACRN_DBG_PIC, "vpic cascade mode required\n");
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@ -277,36 +277,36 @@ static int vpic_icw1(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
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return -1;
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}
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pic->icw_num++;
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i8259->icw_num++;
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return 0;
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}
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static int vpic_icw2(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
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static int vpic_icw2(struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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{
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic icw2 0x%x\n",
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 icw2 0x%x\n",
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vpic->vm, val);
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pic->irq_base = val & 0xf8U;
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i8259->irq_base = val & 0xf8U;
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pic->icw_num++;
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i8259->icw_num++;
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return 0;
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}
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static int vpic_icw3(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
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static int vpic_icw3(struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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{
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic icw3 0x%x\n",
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 icw3 0x%x\n",
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vpic->vm, val);
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pic->icw_num++;
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i8259->icw_num++;
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return 0;
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}
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static int vpic_icw4(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
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static int vpic_icw4(struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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{
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic icw4 0x%x\n",
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 icw4 0x%x\n",
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vpic->vm, val);
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if ((val & ICW4_8086) == 0U) {
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@ -316,12 +316,12 @@ static int vpic_icw4(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
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}
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if ((val & ICW4_AEOI) != 0U) {
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pic->aeoi = true;
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i8259->aeoi = true;
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}
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if ((val & ICW4_SFNM) != 0U) {
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if (master_pic(vpic, pic)) {
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pic->sfn = true;
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if (master_pic(vpic, i8259)) {
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i8259->sfn = true;
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} else {
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dev_dbg(ACRN_DBG_PIC,
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"Ignoring special fully nested mode on slave pic: %#x",
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@ -329,63 +329,63 @@ static int vpic_icw4(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
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}
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}
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pic->icw_num = 0U;
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pic->ready = true;
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i8259->icw_num = 0U;
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i8259->ready = true;
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return 0;
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}
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bool vpic_is_pin_mask(struct acrn_vpic *vpic, uint8_t virt_pin_arg)
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{
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struct pic *pic;
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struct i8259_reg_state *i8259;
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uint8_t virt_pin = virt_pin_arg;
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if (virt_pin < 8U) {
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pic = &vpic->pic[0];
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i8259 = &vpic->i8259[0];
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} else if (virt_pin < 16U) {
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pic = &vpic->pic[1];
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i8259 = &vpic->i8259[1];
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virt_pin -= 8U;
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} else {
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return true;
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}
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if ((pic->mask & (1U << virt_pin)) != 0U) {
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if ((i8259->mask & (1U << virt_pin)) != 0U) {
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return true;
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} else {
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return false;
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}
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}
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static int vpic_ocw1(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
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static int vpic_ocw1(struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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{
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uint8_t pin, i, bit;
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uint8_t old = pic->mask;
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uint8_t old = i8259->mask;
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic ocw1 0x%x\n",
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 ocw1 0x%x\n",
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vpic->vm, val);
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pic->mask = val & 0xffU;
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i8259->mask = val & 0xffU;
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/* query and setup if pin/irq is for passthrough device */
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PIC_PIN_FOREACH(pin, pic, i) {
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PIC_PIN_FOREACH(pin, i8259, i) {
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bit = (uint8_t)(1U << pin);
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/* remap for active: interrupt mask -> unmask
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* remap for deactive: when vIOAPIC take it over
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*/
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if (((pic->mask & bit) == 0U) && ((old & bit) != 0U)) {
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if (((i8259->mask & bit) == 0U) && ((old & bit) != 0U)) {
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struct ptdev_intx_info intx;
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/* master pic pin2 connect with slave pic,
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/* master i8259 pin2 connect with slave i8259,
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* not device, so not need pt remap
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*/
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if ((pin == 2U) && master_pic(vpic, pic)) {
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if ((pin == 2U) && master_pic(vpic, i8259)) {
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continue;
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}
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intx.virt_pin = pin;
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intx.vpin_src = PTDEV_VPIN_PIC;
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if (!master_pic(vpic, pic)) {
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if (!master_pic(vpic, i8259)) {
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intx.virt_pin += 8U;
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}
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ptdev_intx_pin_remap(vpic->vm, &intx);
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@ -395,12 +395,12 @@ static int vpic_ocw1(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
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return 0;
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}
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static int vpic_ocw2(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
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static int vpic_ocw2(struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
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{
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic ocw2 0x%x\n",
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 ocw2 0x%x\n",
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vpic->vm, val);
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pic->rotate = ((val & OCW2_R) != 0U);
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i8259->rotate = ((val & OCW2_R) != 0U);
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if ((val & OCW2_EOI) != 0U) {
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uint8_t isr_bit;
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@ -410,26 +410,26 @@ static int vpic_ocw2(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
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isr_bit = val & 0x7U;
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} else {
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/* non-specific EOI */
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isr_bit = vpic_get_highest_isrpin(pic);
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isr_bit = vpic_get_highest_isrpin(i8259);
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}
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if (isr_bit < NR_VPIC_PINS_PER_CHIP) {
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pic->service &= ~(uint8_t)(1U << isr_bit);
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i8259->service &= ~(uint8_t)(1U << isr_bit);
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if (pic->rotate) {
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pic->lowprio = isr_bit;
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if (i8259->rotate) {
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i8259->lowprio = isr_bit;
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}
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}
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/* if level ack PTDEV */
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if ((pic->elc & (1U << (isr_bit & 0x7U))) != 0U) {
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if ((i8259->elc & (1U << (isr_bit & 0x7U))) != 0U) {
|
||||
ptdev_intx_ack(vpic->vm,
|
||||
(master_pic(vpic, pic) ? isr_bit : isr_bit + 8U),
|
||||
(master_pic(vpic, i8259) ? isr_bit : isr_bit + 8U),
|
||||
PTDEV_VPIN_PIC);
|
||||
}
|
||||
} else if ((val & OCW2_SL) != 0U && pic->rotate) {
|
||||
} else if ((val & OCW2_SL) != 0U && i8259->rotate) {
|
||||
/* specific priority */
|
||||
pic->lowprio = val & 0x7U;
|
||||
i8259->lowprio = val & 0x7U;
|
||||
} else {
|
||||
/* TODO: Any action required in this case? */
|
||||
}
|
||||
@ -437,24 +437,24 @@ static int vpic_ocw2(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vpic_ocw3(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
|
||||
static int vpic_ocw3(struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
|
||||
{
|
||||
dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic ocw3 0x%x\n",
|
||||
dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 ocw3 0x%x\n",
|
||||
vpic->vm, val);
|
||||
|
||||
if ((val & OCW3_ESMM) != 0U) {
|
||||
pic->smm = ((val & OCW3_SMM) != 0U) ? 1U : 0U;
|
||||
dev_dbg(ACRN_DBG_PIC, "%s pic special mask mode %s\n",
|
||||
master_pic(vpic, pic) ? "master" : "slave",
|
||||
(pic->smm != 0U) ? "enabled" : "disabled");
|
||||
i8259->smm = ((val & OCW3_SMM) != 0U) ? 1U : 0U;
|
||||
dev_dbg(ACRN_DBG_PIC, "%s i8259 special mask mode %s\n",
|
||||
master_pic(vpic, i8259) ? "master" : "slave",
|
||||
(i8259->smm != 0U) ? "enabled" : "disabled");
|
||||
}
|
||||
|
||||
if ((val & OCW3_RR) != 0U) {
|
||||
/* read register command */
|
||||
pic->rd_cmd_reg = val & OCW3_RIS;
|
||||
i8259->rd_cmd_reg = val & OCW3_RIS;
|
||||
|
||||
/* Polling mode */
|
||||
pic->poll = ((val & OCW3_P) != 0U);
|
||||
i8259->poll = ((val & OCW3_P) != 0U);
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -462,38 +462,38 @@ static int vpic_ocw3(struct acrn_vpic *vpic, struct pic *pic, uint8_t val)
|
||||
|
||||
static void vpic_set_pinstate(struct acrn_vpic *vpic, uint8_t pin, bool newstate)
|
||||
{
|
||||
struct pic *pic;
|
||||
struct i8259_reg_state *i8259;
|
||||
int oldcnt, newcnt;
|
||||
bool level;
|
||||
|
||||
ASSERT(pin < NR_VPIC_PINS_TOTAL,
|
||||
"vpic_set_pinstate: invalid pin number");
|
||||
|
||||
pic = &vpic->pic[pin >> 3U];
|
||||
i8259 = &vpic->i8259[pin >> 3U];
|
||||
|
||||
oldcnt = pic->acnt[pin & 0x7U];
|
||||
oldcnt = i8259->acnt[pin & 0x7U];
|
||||
if (newstate) {
|
||||
pic->acnt[pin & 0x7U]++;
|
||||
i8259->acnt[pin & 0x7U]++;
|
||||
} else {
|
||||
pic->acnt[pin & 0x7U]--;
|
||||
i8259->acnt[pin & 0x7U]--;
|
||||
}
|
||||
newcnt = pic->acnt[pin & 0x7U];
|
||||
newcnt = i8259->acnt[pin & 0x7U];
|
||||
|
||||
if (newcnt < 0) {
|
||||
pr_warn("pic pin%hhu: bad acnt %d\n", pin, newcnt);
|
||||
}
|
||||
|
||||
level = ((vpic->pic[pin >> 3U].elc & (1U << (pin & 0x7U))) != 0);
|
||||
level = ((vpic->i8259[pin >> 3U].elc & (1U << (pin & 0x7U))) != 0);
|
||||
|
||||
if ((oldcnt == 0 && newcnt == 1) || (newcnt > 0 && level == true)) {
|
||||
/* rising edge or level */
|
||||
dev_dbg(ACRN_DBG_PIC, "pic pin%hhu: asserted\n", pin);
|
||||
pic->request |= (uint8_t)(1U << (pin & 0x7U));
|
||||
i8259->request |= (uint8_t)(1U << (pin & 0x7U));
|
||||
} else if (oldcnt == 1 && newcnt == 0) {
|
||||
/* falling edge */
|
||||
dev_dbg(ACRN_DBG_PIC, "pic pin%hhu: deasserted\n", pin);
|
||||
if (level) {
|
||||
pic->request &= ~(uint8_t)(1U << (pin & 0x7U));
|
||||
i8259->request &= ~(uint8_t)(1U << (pin & 0x7U));
|
||||
}
|
||||
} else {
|
||||
dev_dbg(ACRN_DBG_PIC,
|
||||
@ -507,7 +507,7 @@ static void vpic_set_pinstate(struct acrn_vpic *vpic, uint8_t pin, bool newstate
|
||||
static int vpic_set_irqstate(struct vm *vm, uint32_t irq, enum irqstate irqstate)
|
||||
{
|
||||
struct acrn_vpic *vpic;
|
||||
struct pic *pic;
|
||||
struct i8259_reg_state *i8259;
|
||||
uint8_t pin;
|
||||
|
||||
if (irq >= NR_VPIC_PINS_TOTAL) {
|
||||
@ -515,10 +515,10 @@ static int vpic_set_irqstate(struct vm *vm, uint32_t irq, enum irqstate irqstate
|
||||
}
|
||||
|
||||
vpic = vm_pic(vm);
|
||||
pic = &vpic->pic[irq >> 3U];
|
||||
i8259 = &vpic->i8259[irq >> 3U];
|
||||
pin = (uint8_t)irq;
|
||||
|
||||
if (pic->ready == false) {
|
||||
if (i8259->ready == false) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -588,9 +588,9 @@ int vpic_set_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger trigger)
|
||||
VPIC_LOCK(vpic);
|
||||
|
||||
if (trigger == LEVEL_TRIGGER) {
|
||||
vpic->pic[irq >> 3U].elc |= pin_mask;
|
||||
vpic->i8259[irq >> 3U].elc |= pin_mask;
|
||||
} else {
|
||||
vpic->pic[irq >> 3U].elc &= ~pin_mask;
|
||||
vpic->i8259[irq >> 3U].elc &= ~pin_mask;
|
||||
}
|
||||
|
||||
VPIC_UNLOCK(vpic);
|
||||
@ -611,7 +611,7 @@ int vpic_get_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger *trigger
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ((vpic->pic[irq >> 3U].elc & (1U << (irq & 0x7U))) != 0U) {
|
||||
if ((vpic->i8259[irq >> 3U].elc & (1U << (irq & 0x7U))) != 0U) {
|
||||
*trigger = LEVEL_TRIGGER;
|
||||
} else {
|
||||
*trigger = EDGE_TRIGGER;
|
||||
@ -622,19 +622,19 @@ int vpic_get_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger *trigger
|
||||
void vpic_pending_intr(struct vm *vm, uint32_t *vecptr)
|
||||
{
|
||||
struct acrn_vpic *vpic;
|
||||
struct pic *pic;
|
||||
struct i8259_reg_state *i8259;
|
||||
uint8_t pin;
|
||||
|
||||
vpic = vm_pic(vm);
|
||||
|
||||
pic = &vpic->pic[0];
|
||||
i8259 = &vpic->i8259[0];
|
||||
|
||||
VPIC_LOCK(vpic);
|
||||
|
||||
pin = vpic_get_highest_irrpin(pic);
|
||||
pin = vpic_get_highest_irrpin(i8259);
|
||||
if (pin == 2U) {
|
||||
pic = &vpic->pic[1];
|
||||
pin = vpic_get_highest_irrpin(pic);
|
||||
i8259 = &vpic->i8259[1];
|
||||
pin = vpic_get_highest_irrpin(i8259);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -647,28 +647,28 @@ void vpic_pending_intr(struct vm *vm, uint32_t *vecptr)
|
||||
return;
|
||||
}
|
||||
|
||||
*vecptr = pic->irq_base + pin;
|
||||
*vecptr = i8259->irq_base + pin;
|
||||
|
||||
dev_dbg(ACRN_DBG_PIC, "Got pending vector 0x%x\n", *vecptr);
|
||||
|
||||
VPIC_UNLOCK(vpic);
|
||||
}
|
||||
|
||||
static void vpic_pin_accepted(struct pic *pic, uint8_t pin)
|
||||
static void vpic_pin_accepted(struct i8259_reg_state *i8259, uint8_t pin)
|
||||
{
|
||||
pic->intr_raised = false;
|
||||
i8259->intr_raised = false;
|
||||
|
||||
if ((pic->elc & (1U << pin)) == 0) {
|
||||
if ((i8259->elc & (1U << pin)) == 0) {
|
||||
/*only used edge trigger mode*/
|
||||
pic->request &= ~(uint8_t)(1U << pin);
|
||||
i8259->request &= ~(uint8_t)(1U << pin);
|
||||
}
|
||||
|
||||
if (pic->aeoi == true) {
|
||||
if (pic->rotate == true) {
|
||||
pic->lowprio = pin;
|
||||
if (i8259->aeoi == true) {
|
||||
if (i8259->rotate == true) {
|
||||
i8259->lowprio = pin;
|
||||
}
|
||||
} else {
|
||||
pic->service |= (uint8_t)(1U << pin);
|
||||
i8259->service |= (uint8_t)(1U << pin);
|
||||
}
|
||||
}
|
||||
|
||||
@ -683,15 +683,15 @@ void vpic_intr_accepted(struct vm *vm, uint32_t vector)
|
||||
|
||||
pin = (uint8_t)(vector & 0x7U);
|
||||
|
||||
if ((vector & ~0x7U) == vpic->pic[1].irq_base) {
|
||||
vpic_pin_accepted(&vpic->pic[1], pin);
|
||||
if ((vector & ~0x7U) == vpic->i8259[1].irq_base) {
|
||||
vpic_pin_accepted(&vpic->i8259[1], pin);
|
||||
/*
|
||||
* If this vector originated from the slave,
|
||||
* accept the cascaded interrupt too.
|
||||
*/
|
||||
vpic_pin_accepted(&vpic->pic[0], (uint8_t)2U);
|
||||
vpic_pin_accepted(&vpic->i8259[0], (uint8_t)2U);
|
||||
} else {
|
||||
vpic_pin_accepted(&vpic->pic[0], pin);
|
||||
vpic_pin_accepted(&vpic->i8259[0], pin);
|
||||
}
|
||||
|
||||
vpic_notify_intr(vpic);
|
||||
@ -699,18 +699,18 @@ void vpic_intr_accepted(struct vm *vm, uint32_t vector)
|
||||
VPIC_UNLOCK(vpic);
|
||||
}
|
||||
|
||||
static int vpic_read(struct acrn_vpic *vpic, struct pic *pic,
|
||||
static int vpic_read(struct acrn_vpic *vpic, struct i8259_reg_state *i8259,
|
||||
uint16_t port, uint32_t *eax)
|
||||
{
|
||||
uint8_t pin;
|
||||
|
||||
VPIC_LOCK(vpic);
|
||||
|
||||
if (pic->poll) {
|
||||
pic->poll = false;
|
||||
pin = vpic_get_highest_irrpin(pic);
|
||||
if (i8259->poll) {
|
||||
i8259->poll = false;
|
||||
pin = vpic_get_highest_irrpin(i8259);
|
||||
if (pin < NR_VPIC_PINS_PER_CHIP) {
|
||||
vpic_pin_accepted(pic, pin);
|
||||
vpic_pin_accepted(i8259, pin);
|
||||
*eax = 0x80U | pin;
|
||||
} else {
|
||||
*eax = 0U;
|
||||
@ -718,14 +718,14 @@ static int vpic_read(struct acrn_vpic *vpic, struct pic *pic,
|
||||
} else {
|
||||
if ((port & ICU_IMR_OFFSET) != 0U) {
|
||||
/* read interrupt mask register */
|
||||
*eax = pic->mask;
|
||||
*eax = i8259->mask;
|
||||
} else {
|
||||
if (pic->rd_cmd_reg == OCW3_RIS) {
|
||||
if (i8259->rd_cmd_reg == OCW3_RIS) {
|
||||
/* read interrupt service register */
|
||||
*eax = pic->service;
|
||||
*eax = i8259->service;
|
||||
} else {
|
||||
/* read interrupt request register */
|
||||
*eax = pic->request;
|
||||
*eax = i8259->request;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -735,7 +735,7 @@ static int vpic_read(struct acrn_vpic *vpic, struct pic *pic,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vpic_write(struct acrn_vpic *vpic, struct pic *pic,
|
||||
static int vpic_write(struct acrn_vpic *vpic, struct i8259_reg_state *i8259,
|
||||
uint16_t port, uint32_t *eax)
|
||||
{
|
||||
int error;
|
||||
@ -747,35 +747,35 @@ static int vpic_write(struct acrn_vpic *vpic, struct pic *pic,
|
||||
VPIC_LOCK(vpic);
|
||||
|
||||
if ((port & ICU_IMR_OFFSET) != 0U) {
|
||||
switch (pic->icw_num) {
|
||||
switch (i8259->icw_num) {
|
||||
case 2U:
|
||||
error = vpic_icw2(vpic, pic, val);
|
||||
error = vpic_icw2(vpic, i8259, val);
|
||||
break;
|
||||
case 3U:
|
||||
error = vpic_icw3(vpic, pic, val);
|
||||
error = vpic_icw3(vpic, i8259, val);
|
||||
break;
|
||||
case 4U:
|
||||
error = vpic_icw4(vpic, pic, val);
|
||||
error = vpic_icw4(vpic, i8259, val);
|
||||
break;
|
||||
default:
|
||||
error = vpic_ocw1(vpic, pic, val);
|
||||
error = vpic_ocw1(vpic, i8259, val);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
if ((val & (1U << 4U)) != 0U) {
|
||||
error = vpic_icw1(vpic, pic, val);
|
||||
error = vpic_icw1(vpic, i8259, val);
|
||||
}
|
||||
|
||||
if (pic->ready) {
|
||||
if (i8259->ready) {
|
||||
if ((val & (1U << 3U)) != 0U) {
|
||||
error = vpic_ocw3(vpic, pic, val);
|
||||
error = vpic_ocw3(vpic, i8259, val);
|
||||
} else {
|
||||
error = vpic_ocw2(vpic, pic, val);
|
||||
error = vpic_ocw2(vpic, i8259, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (pic->ready) {
|
||||
if (i8259->ready) {
|
||||
vpic_notify_intr(vpic);
|
||||
}
|
||||
|
||||
@ -788,20 +788,20 @@ static int vpic_master_handler(struct vm *vm, bool in, uint16_t port,
|
||||
size_t bytes, uint32_t *eax)
|
||||
{
|
||||
struct acrn_vpic *vpic;
|
||||
struct pic *pic;
|
||||
struct i8259_reg_state *i8259;
|
||||
|
||||
vpic = vm_pic(vm);
|
||||
pic = &vpic->pic[0];
|
||||
i8259 = &vpic->i8259[0];
|
||||
|
||||
if (bytes != 1U) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (in) {
|
||||
return vpic_read(vpic, pic, port, eax);
|
||||
return vpic_read(vpic, i8259, port, eax);
|
||||
}
|
||||
|
||||
return vpic_write(vpic, pic, port, eax);
|
||||
return vpic_write(vpic, i8259, port, eax);
|
||||
}
|
||||
|
||||
static uint32_t vpic_master_io_read(__unused struct vm_io_handler *hdlr,
|
||||
@ -831,20 +831,20 @@ static int vpic_slave_handler(struct vm *vm, bool in, uint16_t port,
|
||||
size_t bytes, uint32_t *eax)
|
||||
{
|
||||
struct acrn_vpic *vpic;
|
||||
struct pic *pic;
|
||||
struct i8259_reg_state *i8259;
|
||||
|
||||
vpic = vm_pic(vm);
|
||||
pic = &vpic->pic[1];
|
||||
i8259 = &vpic->i8259[1];
|
||||
|
||||
if (bytes != 1U) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (in) {
|
||||
return vpic_read(vpic, pic, port, eax);
|
||||
return vpic_read(vpic, i8259, port, eax);
|
||||
}
|
||||
|
||||
return vpic_write(vpic, pic, port, eax);
|
||||
return vpic_write(vpic, i8259, port, eax);
|
||||
}
|
||||
|
||||
static uint32_t vpic_slave_io_read(__unused struct vm_io_handler *hdlr,
|
||||
@ -887,9 +887,9 @@ static int vpic_elc_handler(struct vm *vm, bool in, uint16_t port, size_t bytes,
|
||||
|
||||
if (in) {
|
||||
if (is_master) {
|
||||
*eax = vpic->pic[0].elc;
|
||||
*eax = vpic->i8259[0].elc;
|
||||
} else {
|
||||
*eax = vpic->pic[1].elc;
|
||||
*eax = vpic->i8259[1].elc;
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
@ -903,9 +903,9 @@ static int vpic_elc_handler(struct vm *vm, bool in, uint16_t port, size_t bytes,
|
||||
* be programmed for level mode.
|
||||
*/
|
||||
if (is_master) {
|
||||
vpic->pic[0].elc = (uint8_t)(*eax & 0xf8U);
|
||||
vpic->i8259[0].elc = (uint8_t)(*eax & 0xf8U);
|
||||
} else {
|
||||
vpic->pic[1].elc = (uint8_t)(*eax & 0xdeU);
|
||||
vpic->i8259[1].elc = (uint8_t)(*eax & 0xdeU);
|
||||
}
|
||||
}
|
||||
|
||||
@ -971,8 +971,8 @@ void *vpic_init(struct vm *vm)
|
||||
vpic = calloc(1U, sizeof(struct acrn_vpic));
|
||||
ASSERT(vpic != NULL, "");
|
||||
vpic->vm = vm;
|
||||
vpic->pic[0].mask = 0xffU;
|
||||
vpic->pic[1].mask = 0xffU;
|
||||
vpic->i8259[0].mask = 0xffU;
|
||||
vpic->i8259[1].mask = 0xffU;
|
||||
|
||||
VPIC_LOCK_INIT(vpic);
|
||||
|
||||
|
||||
@ -662,21 +662,21 @@ int32_t hcall_assign_ptdev(struct vm *vm, uint16_t vmid, uint64_t param)
|
||||
}
|
||||
|
||||
/* create a iommu domain for target VM if not created */
|
||||
if (target_vm->iommu_domain == NULL) {
|
||||
if (target_vm->iommu == NULL) {
|
||||
if (target_vm->arch_vm.nworld_eptp == NULL) {
|
||||
pr_err("%s, EPT of VM not set!\n",
|
||||
__func__, target_vm->attr.id);
|
||||
return -EPERM;
|
||||
}
|
||||
/* TODO: how to get vm's address width? */
|
||||
target_vm->iommu_domain = create_iommu_domain(vmid,
|
||||
target_vm->iommu = create_iommu_domain(vmid,
|
||||
HVA2HPA(target_vm->arch_vm.nworld_eptp), 48U);
|
||||
if (target_vm->iommu_domain == NULL) {
|
||||
if (target_vm->iommu == NULL) {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
}
|
||||
ret = assign_iommu_device(target_vm->iommu_domain,
|
||||
ret = assign_iommu_device(target_vm->iommu,
|
||||
(uint8_t)(bdf >> 8), (uint8_t)(bdf & 0xffU));
|
||||
|
||||
return ret;
|
||||
@ -696,7 +696,7 @@ int32_t hcall_deassign_ptdev(struct vm *vm, uint16_t vmid, uint64_t param)
|
||||
pr_err("%s: Unable copy param to vm\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
ret = unassign_iommu_device(target_vm->iommu_domain,
|
||||
ret = unassign_iommu_device(target_vm->iommu,
|
||||
(uint8_t)(bdf >> 8), (uint8_t)(bdf & 0xffU));
|
||||
|
||||
return ret;
|
||||
|
||||
@ -135,7 +135,7 @@ struct vm {
|
||||
void *vuart; /* Virtual UART */
|
||||
struct acrn_vpic *vpic; /* Virtual PIC */
|
||||
enum vpic_wire_mode vpic_wire_mode;
|
||||
struct iommu_domain *iommu_domain; /* iommu domain of this VM */
|
||||
struct iommu_domain *iommu; /* iommu domain of this VM */
|
||||
struct list_head list; /* list of VM */
|
||||
spinlock_t spinlock; /* Spin-lock used to protect VM modifications */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user