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HV: Updated vm description table for partition mode

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This reference table defines USB/SATA/Ethernet passthru for MRB board.

Tracked-On: #1126
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
dongshen 2018-08-28 16:15:54 -07:00 committed by lijinxia
parent c9ea8901e6
commit 308910ebf7
1 changed files with 78 additions and 44 deletions
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122
hypervisor/partition/vm_description.c
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@ -37,85 +37,119 @@ static struct vpci_vdev_array vpci_vdev_array1 = {
.ops = &pci_ops_vdev_hostbridge,
.bar = {},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
}
.bdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
}
},
{/*vdev 1*/
{/*vdev 1: SATA controller*/
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x0U},
.ops = &pci_ops_vdev_pt,
.bar = {
[0] = {
.base = 0UL,
.size = 0x1000UL,
.type = PCIBAR_MEM32
},
[5] = {
.base = 0UL,
.size = 0x2000UL,
.type = PCIBAR_MEM32
},
[0] = {
.base = 0UL,
.size = 0x2000UL,
.type = PCIBAR_MEM32
},
[1] = {
.base = 0UL,
.size = 0x1000UL,
.type = PCIBAR_MEM32
},
[5] = {
.base = 0UL,
.size = 0x1000UL,
.type = PCIBAR_MEM32
},
},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x0U},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x12U, .f = 0x0U},
.bar = {
[0] = {
.base = 0xa9000000UL,
.base = 0xb3f10000UL,
.size = 0x2000UL,
.type = PCIBAR_MEM32
},
[1] = {
.base = 0xb3f53000UL,
.size = 0x100UL,
.type = PCIBAR_MEM32
},
[5] = {
.base = 0x1a0000000UL,
.size = 0x2000UL,
.type = PCIBAR_MEM64
.base = 0xb3f52000UL,
.size = 0x800UL,
.type = PCIBAR_MEM32
},
}
}
}
},
}
};
static struct vpci_vdev_array vpci_vdev_array2 = {
.num_pci_vdev = 2,
.num_pci_vdev = 3,
.vpci_vdev_list = {
{/*vdev 0: hostbridge*/
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
.ops = &pci_ops_vdev_hostbridge,
.bar = {}, /* don't care for hostbridge */
.pdev = {} /* don't care for hostbridge */
.bar = {},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
}
},
{/*vdev 1*/
{/*vdev 1: USB controller*/
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x0U},
.ops = &pci_ops_vdev_pt,
.bar = {
[0] = {
.base = 0UL,
.size = 0x1000UL,
.type = PCIBAR_MEM32
},
[5] = {
.base = 0UL,
.size = 0x2000UL,
.type = PCIBAR_MEM32
},
[0] = {
.base = 0UL,
.size = 0x10000UL,
.type = PCIBAR_MEM32
},
},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x0U},
.pdev = {
.bdf.bits = {.b = 0x00U, .d = 0x15U, .f = 0x0U},
.bar = {
[0] = {
.base = 0xa8000000UL,
.size = 0x100UL,
.type = PCIBAR_MEM32
},
[5] = {
.base = 0x1b0000000UL,
.size = 0x2000UL,
.base = 0xb3f00000UL,
.size = 0x10000UL,
.type = PCIBAR_MEM64
},
}
}
},
{/*vdev 2: Ethernet*/
.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x0U},
.ops = &pci_ops_vdev_pt,
.bar = {
[0] = {
.base = 0UL,
.size = 0x80000UL,
.type = PCIBAR_MEM32
},
[3] = {
.base = 0UL,
.size = 0x4000UL,
.type = PCIBAR_MEM32
},
},
.pdev = {
.bdf.bits = {.b = 0x02U, .d = 0x00U, .f = 0x0U},
.bar = {
[0] = {
.base = 0xb3c00000UL,
.size = 0x80000UL,
.type = PCIBAR_MEM32
},
[3] = {
.base = 0xb3c80000UL,
.size = 0x4000UL,
.type = PCIBAR_MEM32
},
}
}
}
},
}
};