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HV: fix misra violation on platform clos array

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MISRA C requires specified bounds for arrays declaration, previous declaration
of platform_clos_array in board.h does not meet the requirement.

Tracked-On: #3987

Signed-off-by: Victor Sun <victor.sun@intel.com>
This commit is contained in:
Victor Sun 2019-11-01 15:01:52 +08:00 committed by wenlingz
parent c77d275e9d
commit 3411f00b5b
17 changed files with 30 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
hypervisor/arch/x86/cat.c
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@ -18,6 +18,7 @@
struct cat_hw_info cat_cap_info; struct cat_hw_info cat_cap_info;
const uint16_t hv_clos = 0U; const uint16_t hv_clos = 0U;
static uint16_t platform_clos_num = MAX_PLATFORM_CLOS_NUM;
int32_t init_cat_cap_info(void) int32_t init_cat_cap_info(void)
{ {

3
hypervisor/arch/x86/configs/apl-mrb/board.c
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@ -13,6 +13,5 @@
#endif #endif
struct dmar_info plat_dmar_info; struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[0]; struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
uint16_t platform_clos_num = 0;
const struct cpu_state_table board_cpu_state_tbl; const struct cpu_state_table board_cpu_state_tbl;

2
hypervisor/arch/x86/configs/apl-mrb/misc_cfg.h
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@ -8,6 +8,8 @@
#define MISC_CFG_H #define MISC_CFG_H
#define CONFIG_MAX_PCPU_NUM 4U #define CONFIG_MAX_PCPU_NUM 4U
#define MAX_PLATFORM_CLOS_NUM 0U
#define ROOTFS_0 "root=/dev/sda3 " #define ROOTFS_0 "root=/dev/sda3 "
#define ROOTFS_1 "root=/dev/mmcblk1p1 " #define ROOTFS_1 "root=/dev/mmcblk1p1 "

12
hypervisor/arch/x86/configs/apl-up2/board.c
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@ -15,25 +15,23 @@
struct dmar_info plat_dmar_info; struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[4] = { struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM] = {
{ {
.clos_mask = 0xff, .clos_mask = 0xff,
.msr_index = MSR_IA32_L2_MASK_0, .msr_index = MSR_IA32_L2_MASK_BASE,
}, },
{ {
.clos_mask = 0xff, .clos_mask = 0xff,
.msr_index = MSR_IA32_L2_MASK_1, .msr_index = MSR_IA32_L2_MASK_BASE + 1U,
}, },
{ {
.clos_mask = 0xff, .clos_mask = 0xff,
.msr_index = MSR_IA32_L2_MASK_2, .msr_index = MSR_IA32_L2_MASK_BASE + 2U,
}, },
{ {
.clos_mask = 0xff, .clos_mask = 0xff,
.msr_index = MSR_IA32_L2_MASK_3, .msr_index = MSR_IA32_L2_MASK_BASE + 3U,
}, },
}; };
uint16_t platform_clos_num = (uint16_t)(sizeof(platform_clos_array)/sizeof(struct platform_clos_info));
const struct cpu_state_table board_cpu_state_tbl; const struct cpu_state_table board_cpu_state_tbl;

2
hypervisor/arch/x86/configs/apl-up2/misc_cfg.h
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@ -8,6 +8,8 @@
#define MISC_CFG_H #define MISC_CFG_H
#define CONFIG_MAX_PCPU_NUM 4U #define CONFIG_MAX_PCPU_NUM 4U
#define MAX_PLATFORM_CLOS_NUM 4U
#define ROOTFS_0 "root=/dev/sda3 " #define ROOTFS_0 "root=/dev/sda3 "
#define ROOTFS_1 "root=/dev/mmcblk0p3 " #define ROOTFS_1 "root=/dev/mmcblk0p3 "

3
hypervisor/arch/x86/configs/dnv-cb2/board.c
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@ -13,6 +13,5 @@
#endif #endif
struct dmar_info plat_dmar_info; struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[0]; struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
uint16_t platform_clos_num = 0;
const struct cpu_state_table board_cpu_state_tbl; const struct cpu_state_table board_cpu_state_tbl;

2
hypervisor/arch/x86/configs/dnv-cb2/misc_cfg.h
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@ -8,6 +8,8 @@
#define MISC_CFG_H #define MISC_CFG_H
#define CONFIG_MAX_PCPU_NUM 8U #define CONFIG_MAX_PCPU_NUM 8U
#define MAX_PLATFORM_CLOS_NUM 0U
#define ROOTFS_0 "root=/dev/sda3 " #define ROOTFS_0 "root=/dev/sda3 "
#define SOS_ROOTFS ROOTFS_0 #define SOS_ROOTFS ROOTFS_0

3
hypervisor/arch/x86/configs/generic/board.c
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@ -13,6 +13,5 @@
#endif #endif
struct dmar_info plat_dmar_info; struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[0]; struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
uint16_t platform_clos_num = 0;
const struct cpu_state_table board_cpu_state_tbl; const struct cpu_state_table board_cpu_state_tbl;

2
hypervisor/arch/x86/configs/generic/misc_cfg.h
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@ -8,6 +8,8 @@
#define MISC_CFG_H #define MISC_CFG_H
#define CONFIG_MAX_PCPU_NUM 4U #define CONFIG_MAX_PCPU_NUM 4U
#define MAX_PLATFORM_CLOS_NUM 0U
#define ROOTFS_0 "root=/dev/sda3 " #define ROOTFS_0 "root=/dev/sda3 "
#define ROOTFS_1 "root=/dev/mmcblk0p1 " #define ROOTFS_1 "root=/dev/mmcblk0p1 "

4
hypervisor/arch/x86/configs/icl-rvp/board.c
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@ -13,5 +13,5 @@
#endif #endif
struct dmar_info plat_dmar_info; struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[0]; struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
uint16_t platform_clos_num = 0; const struct cpu_state_table board_cpu_state_tbl;

3
hypervisor/arch/x86/configs/nuc6cayh/board.c
View File

@ -13,6 +13,5 @@
#endif #endif
struct dmar_info plat_dmar_info; struct dmar_info plat_dmar_info;
struct platform_clos_info platform_clos_array[0]; struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
uint16_t platform_clos_num = 0;
const struct cpu_state_table board_cpu_state_tbl; const struct cpu_state_table board_cpu_state_tbl;

2
hypervisor/arch/x86/configs/nuc6cayh/misc_cfg.h
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@ -8,6 +8,8 @@
#define MISC_CFG_H #define MISC_CFG_H
#define CONFIG_MAX_PCPU_NUM 4U #define CONFIG_MAX_PCPU_NUM 4U
#define MAX_PLATFORM_CLOS_NUM 0U
#define ROOTFS_0 "root=/dev/sda3 " #define ROOTFS_0 "root=/dev/sda3 "
#define SOS_ROOTFS ROOTFS_0 #define SOS_ROOTFS ROOTFS_0

3
hypervisor/arch/x86/configs/nuc7i7dnb/board.c
View File

@ -55,6 +55,5 @@ struct dmar_info plat_dmar_info = {
.drhd_units = drhd_info_array, .drhd_units = drhd_info_array,
}; };
struct platform_clos_info platform_clos_array[0]; struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
uint16_t platform_clos_num = 0;
const struct cpu_state_table board_cpu_state_tbl; const struct cpu_state_table board_cpu_state_tbl;

2
hypervisor/arch/x86/configs/nuc7i7dnb/misc_cfg.h
View File

@ -8,6 +8,8 @@
#define MISC_CFG_H #define MISC_CFG_H
#define CONFIG_MAX_PCPU_NUM 4U #define CONFIG_MAX_PCPU_NUM 4U
#define MAX_PLATFORM_CLOS_NUM 0U
#define ROOTFS_0 "root=/dev/sda3 " #define ROOTFS_0 "root=/dev/sda3 "
#define ROOTFS_1 "root=/dev/nvme0n1p3 " #define ROOTFS_1 "root=/dev/nvme0n1p3 "

2
hypervisor/arch/x86/guest/vmsr.c
View File

@ -337,7 +337,7 @@ void init_msr_emulation(struct acrn_vcpu *vcpu)
} }
/* RDT-A disabled: CPUID.07H.EBX[12], CPUID.10H */ /* RDT-A disabled: CPUID.07H.EBX[12], CPUID.10H */
for (msr = MSR_IA32_L3_MASK_0; msr < MSR_IA32_BNDCFGS; msr++) { for (msr = MSR_IA32_L3_MASK_BASE; msr < MSR_IA32_BNDCFGS; msr++) {
enable_msr_interception(msr_bitmap, msr, INTERCEPT_READ_WRITE); enable_msr_interception(msr_bitmap, msr, INTERCEPT_READ_WRITE);
} }

4
hypervisor/include/arch/x86/board.h
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@ -7,6 +7,7 @@
#define BOARD_H #define BOARD_H
#include <types.h> #include <types.h>
#include <misc_cfg.h>
#include <host_pm.h> #include <host_pm.h>
/* forward declarations */ /* forward declarations */
@ -18,8 +19,7 @@ struct platform_clos_info {
}; };
extern struct dmar_info plat_dmar_info; extern struct dmar_info plat_dmar_info;
extern struct platform_clos_info platform_clos_array[]; extern struct platform_clos_info platform_clos_array[MAX_PLATFORM_CLOS_NUM];
extern uint16_t platform_clos_num;
extern const struct cpu_state_table board_cpu_state_tbl; extern const struct cpu_state_table board_cpu_state_tbl;
/* board specific functions */ /* board specific functions */

7
hypervisor/include/arch/x86/msr.h
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@ -335,15 +335,12 @@
#define MSR_IA32_QM_EVTSEL 0x00000C8DU #define MSR_IA32_QM_EVTSEL 0x00000C8DU
#define MSR_IA32_QM_CTR 0x00000C8EU #define MSR_IA32_QM_CTR 0x00000C8EU
#define MSR_IA32_PQR_ASSOC 0x00000C8FU #define MSR_IA32_PQR_ASSOC 0x00000C8FU
#define MSR_IA32_L3_MASK_0 0x00000C90U #define MSR_IA32_L3_MASK_BASE 0x00000C90U
#define MSR_IA32_XSS 0x00000DA0U #define MSR_IA32_XSS 0x00000DA0U
#define MSR_IA32_PKG_HDC_CTL 0x00000DB0U #define MSR_IA32_PKG_HDC_CTL 0x00000DB0U
#define MSR_IA32_PM_CTL1 0x00000DB1U #define MSR_IA32_PM_CTL1 0x00000DB1U
#define MSR_IA32_THREAD_STALL 0x00000DB2U #define MSR_IA32_THREAD_STALL 0x00000DB2U
#define MSR_IA32_L2_MASK_0 0x00000D10U #define MSR_IA32_L2_MASK_BASE 0x00000D10U
#define MSR_IA32_L2_MASK_1 0x00000D11U
#define MSR_IA32_L2_MASK_2 0x00000D12U
#define MSR_IA32_L2_MASK_3 0x00000D13U
#define MSR_IA32_BNDCFGS 0x00000D90U #define MSR_IA32_BNDCFGS 0x00000D90U
#define MSR_IA32_EFER 0xC0000080U #define MSR_IA32_EFER 0xC0000080U
#define MSR_IA32_STAR 0xC0000081U #define MSR_IA32_STAR 0xC0000081U