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HV: cpuid: Disable Intel RDT for guest OS

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Now the Intel RDT emulation is working in progress. So disable it
for temporary solution to avoid guest OS running with incorrect RDT
configuration.

Signed-off-by: Shuo Liu <shuo.a.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Shuo Liu 2018-07-19 11:01:27 +08:00 committed by lijinxia
parent 9ac1be2c5e
commit 38b9b7d37c
2 changed files with 68 additions and 62 deletions
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4
hypervisor/arch/x86/cpuid.c
View File

@ -98,7 +98,9 @@ static void init_vcpuid_entry(__unused struct vm *vm,
&entry->eax, &entry->ebx,
&entry->ecx, &entry->edx);
/* mask invpcid */
entry->ebx &= ~CPUID_EBX_INVPCID;
entry->ebx &= ~(CPUID_EBX_INVPCID |
CPUID_EBX_PQM |
CPUID_EBX_PQE);
} else {
entry->eax = 0U;
entry->ebx = 0U;

126
hypervisor/include/arch/x86/cpuid.h
View File

@ -15,73 +15,77 @@
#define CPUID_H_
/* CPUID bit definitions */
#define CPUID_ECX_SSE3 (1U<<0)
#define CPUID_ECX_PCLMUL (1U<<1)
#define CPUID_ECX_DTES64 (1U<<2)
#define CPUID_ECX_MONITOR (1U<<3)
#define CPUID_ECX_DS_CPL (1U<<4)
#define CPUID_ECX_VMX (1U<<5)
#define CPUID_ECX_SMX (1U<<6)
#define CPUID_ECX_EST (1U<<7)
#define CPUID_ECX_TM2 (1U<<8)
#define CPUID_ECX_SSSE3 (1U<<9)
#define CPUID_ECX_CID (1U<<10)
#define CPUID_ECX_FMA (1U<<12)
#define CPUID_ECX_CX16 (1U<<13)
#define CPUID_ECX_ETPRD (1U<<14)
#define CPUID_ECX_PDCM (1U<<15)
#define CPUID_ECX_DCA (1U<<18)
#define CPUID_ECX_SSE4_1 (1U<<19)
#define CPUID_ECX_SSE4_2 (1U<<20)
#define CPUID_ECX_x2APIC (1U<<21)
#define CPUID_ECX_MOVBE (1U<<22)
#define CPUID_ECX_POPCNT (1U<<23)
#define CPUID_ECX_AES (1U<<25)
#define CPUID_ECX_XSAVE (1U<<26)
#define CPUID_ECX_OSXSAVE (1U<<27)
#define CPUID_ECX_AVX (1U<<28)
#define CPUID_EDX_FPU (1U<<0)
#define CPUID_EDX_VME (1U<<1)
#define CPUID_EDX_DE (1U<<2)
#define CPUID_EDX_PSE (1U<<3)
#define CPUID_EDX_TSC (1U<<4)
#define CPUID_EDX_MSR (1U<<5)
#define CPUID_EDX_PAE (1U<<6)
#define CPUID_EDX_MCE (1U<<7)
#define CPUID_EDX_CX8 (1U<<8)
#define CPUID_EDX_APIC (1U<<9)
#define CPUID_EDX_SEP (1U<<11)
#define CPUID_EDX_MTRR (1U<<12)
#define CPUID_EDX_PGE (1U<<13)
#define CPUID_EDX_MCA (1U<<14)
#define CPUID_EDX_CMOV (1U<<15)
#define CPUID_EDX_PAT (1U<<16)
#define CPUID_EDX_PSE36 (1U<<17)
#define CPUID_EDX_PSN (1U<<18)
#define CPUID_EDX_CLF (1U<<19)
#define CPUID_EDX_DTES (1U<<21)
#define CPUID_EDX_ACPI (1U<<22)
#define CPUID_EDX_MMX (1U<<23)
#define CPUID_EDX_FXSR (1U<<24)
#define CPUID_EDX_SSE (1U<<25)
#define CPUID_EDX_SSE2 (1U<<26)
#define CPUID_EDX_SS (1U<<27)
#define CPUID_EDX_HTT (1U<<28)
#define CPUID_EDX_TM1 (1U<<29)
#define CPUID_EDX_IA64 (1U<<30)
#define CPUID_EDX_PBE (1U<<31)
#define CPUID_ECX_SSE3 (1U<<0U)
#define CPUID_ECX_PCLMUL (1U<<1U)
#define CPUID_ECX_DTES64 (1U<<2U)
#define CPUID_ECX_MONITOR (1U<<3U)
#define CPUID_ECX_DS_CPL (1U<<4U)
#define CPUID_ECX_VMX (1U<<5U)
#define CPUID_ECX_SMX (1U<<6U)
#define CPUID_ECX_EST (1U<<7U)
#define CPUID_ECX_TM2 (1U<<8U)
#define CPUID_ECX_SSSE3 (1U<<9U)
#define CPUID_ECX_CID (1U<<10U)
#define CPUID_ECX_FMA (1U<<12U)
#define CPUID_ECX_CX16 (1U<<13U)
#define CPUID_ECX_ETPRD (1U<<14U)
#define CPUID_ECX_PDCM (1U<<15U)
#define CPUID_ECX_DCA (1U<<18U)
#define CPUID_ECX_SSE4_1 (1U<<19U)
#define CPUID_ECX_SSE4_2 (1U<<20U)
#define CPUID_ECX_x2APIC (1U<<21U)
#define CPUID_ECX_MOVBE (1U<<22U)
#define CPUID_ECX_POPCNT (1U<<23U)
#define CPUID_ECX_AES (1U<<25U)
#define CPUID_ECX_XSAVE (1U<<26U)
#define CPUID_ECX_OSXSAVE (1U<<27U)
#define CPUID_ECX_AVX (1U<<28U)
#define CPUID_EDX_FPU (1U<<0U)
#define CPUID_EDX_VME (1U<<1U)
#define CPUID_EDX_DE (1U<<2U)
#define CPUID_EDX_PSE (1U<<3U)
#define CPUID_EDX_TSC (1U<<4U)
#define CPUID_EDX_MSR (1U<<5U)
#define CPUID_EDX_PAE (1U<<6U)
#define CPUID_EDX_MCE (1U<<7U)
#define CPUID_EDX_CX8 (1U<<8U)
#define CPUID_EDX_APIC (1U<<9U)
#define CPUID_EDX_SEP (1U<<11U)
#define CPUID_EDX_MTRR (1U<<12U)
#define CPUID_EDX_PGE (1U<<13U)
#define CPUID_EDX_MCA (1U<<14U)
#define CPUID_EDX_CMOV (1U<<15U)
#define CPUID_EDX_PAT (1U<<16U)
#define CPUID_EDX_PSE36 (1U<<17U)
#define CPUID_EDX_PSN (1U<<18U)
#define CPUID_EDX_CLF (1U<<19U)
#define CPUID_EDX_DTES (1U<<21U)
#define CPUID_EDX_ACPI (1U<<22U)
#define CPUID_EDX_MMX (1U<<23U)
#define CPUID_EDX_FXSR (1U<<24U)
#define CPUID_EDX_SSE (1U<<25U)
#define CPUID_EDX_SSE2 (1U<<26U)
#define CPUID_EDX_SS (1U<<27U)
#define CPUID_EDX_HTT (1U<<28U)
#define CPUID_EDX_TM1 (1U<<29U)
#define CPUID_EDX_IA64 (1U<<30U)
#define CPUID_EDX_PBE (1U<<31U)
/* CPUID.07H:EBX.TSC_ADJUST*/
#define CPUID_EBX_TSC_ADJ (1U<<1)
#define CPUID_EBX_TSC_ADJ (1U<<1U)
/* CPUID.07H:EDX.IBRS_IBPB*/
#define CPUID_EDX_IBRS_IBPB (1U<<26)
#define CPUID_EDX_IBRS_IBPB (1U<<26U)
/* CPUID.07H:EDX.STIBP*/
#define CPUID_EDX_STIBP (1U<<27)
#define CPUID_EDX_STIBP (1U<<27U)
/* CPUID.80000001H:EDX.Page1GB*/
#define CPUID_EDX_PAGE1GB (1U<<26)
#define CPUID_EDX_PAGE1GB (1U<<26U)
/* CPUID.07H:EBX.INVPCID*/
#define CPUID_EBX_INVPCID (1U<<10)
#define CPUID_EBX_INVPCID (1U<<10U)
/* CPUID.07H:EBX.PQM */
#define CPUID_EBX_PQM (1U<<12U)
/* CPUID.07H:EBX.PQE */
#define CPUID_EBX_PQE (1U<<15U)
/* CPUID.01H:ECX.PCID*/
#define CPUID_ECX_PCID (1U<<17)
#define CPUID_ECX_PCID (1U<<17U)
/* CPUID source operands */
#define CPUID_VENDORSTRING 0U