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https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-24 14:33:38 +00:00
vioapic: add pin_state bitmap to set irq
a guest may use per-cpu vector allocation mechanism which may lead to same vector on different vcpu for different vioapic pins. when we broadcast EOI from vlapic to vioapic, it could trigger ptdev_intx_ack for incorrect vioapic pin which will lead to incorrect vioapic irq deassert. old implementation is recording assert & deassert by acnt, like: - assert -> acnt++ - deassert -> acnt-- which means an incorrect deassert may descrease acnt from 0 to -1, it leads to error. this patch change the recording method for a pin assert/deassert, it just use pin_state bit set/clear to indicate line state: - high -> pin_state bitmap set - low -> pin_state bitmap clear and the irq assert will be triggered based on polarity setting during line state changing. it can avoid the failure of incorrect deassert on old implementation, and for ptdev sharing irq, the dev hardware could re-trigger interrupt after deassert. but for emulated device, there is no mechanism to re-trigger interrupt if there is irq sharing - for DM, we already has constraint to restrict vGSI sharing, so there is no problem of it. Tracked-On: #1269 Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
This commit is contained in:
Jason Chen CJ
Xie, Nanlin
parent
ba68bd4190
commit
3b88d3c2ac
@ -42,11 +42,6 @@
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#define MASK_ALL_INTERRUPTS 0x0001000000010000UL
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#define IOAPIC_RTE_LOW_INTVEC ((uint32_t)IOAPIC_RTE_INTVEC)
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static inline const char *pinstate_str(bool asserted)
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{
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return (asserted) ? "asserted" : "deasserted";
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}
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/**
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* @pre pin < vioapic_pincount(vm)
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*/
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@ -87,36 +82,67 @@ vioapic_send_intr(struct acrn_vioapic *vioapic, uint32_t pin)
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* @pre pin < vioapic_pincount(vm)
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*/
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static void
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vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint32_t pin, bool newstate)
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vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint16_t pin, uint32_t level)
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{
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int oldcnt, newcnt;
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bool needintr;
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uint32_t old_lvl;
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union ioapic_rte rte = vioapic->rtbl[pin];
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oldcnt = vioapic->acnt[pin];
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if (newstate) {
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vioapic->acnt[pin]++;
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old_lvl = (uint32_t)bitmap_test(pin & 0x3FU, &vioapic->pin_state[pin >> 6U]);
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if (level == 0U) {
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/* clear pin_state and deliver interrupt according to polarity */
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bitmap_clear_nolock(pin & 0x3FU,
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&vioapic->pin_state[pin >> 6U]);
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if (((rte.full & IOAPIC_RTE_INTPOL) != 0UL)
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&& old_lvl != level) {
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vioapic_send_intr(vioapic, pin);
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}
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} else {
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vioapic->acnt[pin]--;
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/* set pin_state and deliver intrrupt according to polarity */
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bitmap_set_nolock(pin & 0x3FU, &vioapic->pin_state[pin >> 6U]);
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if (((rte.full & IOAPIC_RTE_INTPOL) == 0UL)
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&& old_lvl != level) {
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vioapic_send_intr(vioapic, pin);
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}
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}
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newcnt = vioapic->acnt[pin];
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}
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if (newcnt < 0) {
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pr_err("ioapic pin%hhu: bad acnt %d", pin, newcnt);
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}
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/**
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* @pre irq < vioapic_pincount(vm)
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* @pre operation value shall be one of the folllowing values:
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* GSI_SET_HIGH
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* GSI_SET_LOW
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* GSI_RAISING_PULSE
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* GSI_FALLING_PULSE
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* @pre call with vioapic lock
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*/
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void
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vioapic_set_irq_nolock(struct vm *vm, uint32_t irq, uint32_t operation)
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{
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struct acrn_vioapic *vioapic;
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uint16_t pin = (uint16_t)irq;
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needintr = false;
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if ((oldcnt == 0) && (newcnt == 1)) {
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needintr = true;
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dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: asserted", pin);
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} else if ((oldcnt == 1) && (newcnt == 0)) {
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dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: deasserted", pin);
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} else {
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dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: %s, ignored, acnt %d",
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pin, pinstate_str(newstate), newcnt);
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}
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vioapic = vm_ioapic(vm);
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if (needintr) {
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vioapic_send_intr(vioapic, pin);
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switch (operation) {
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case GSI_SET_HIGH:
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vioapic_set_pinstate(vioapic, pin, 1U);
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break;
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case GSI_SET_LOW:
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vioapic_set_pinstate(vioapic, pin, 0U);
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break;
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case GSI_RAISING_PULSE:
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vioapic_set_pinstate(vioapic, pin, 1U);
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vioapic_set_pinstate(vioapic, pin, 0U);
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break;
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case GSI_FALLING_PULSE:
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vioapic_set_pinstate(vioapic, pin, 0U);
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vioapic_set_pinstate(vioapic, pin, 1U);
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break;
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default:
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/*
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* The function caller could guarantee the pre condition.
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*/
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break;
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}
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}
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@ -131,33 +157,10 @@ vioapic_set_pinstate(struct acrn_vioapic *vioapic, uint32_t pin, bool newstate)
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void
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vioapic_set_irq(struct vm *vm, uint32_t irq, uint32_t operation)
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{
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struct acrn_vioapic *vioapic;
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uint32_t pin = irq;
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vioapic = vm_ioapic(vm);
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struct acrn_vioapic *vioapic = vm_ioapic(vm);
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spinlock_obtain(&(vioapic->mtx));
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switch (operation) {
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case GSI_SET_HIGH:
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vioapic_set_pinstate(vioapic, pin, true);
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break;
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case GSI_SET_LOW:
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vioapic_set_pinstate(vioapic, pin, false);
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break;
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case GSI_RAISING_PULSE:
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vioapic_set_pinstate(vioapic, pin, true);
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vioapic_set_pinstate(vioapic, pin, false);
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break;
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case GSI_FALLING_PULSE:
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vioapic_set_pinstate(vioapic, pin, false);
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vioapic_set_pinstate(vioapic, pin, true);
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break;
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default:
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/*
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* The function caller could guarantee the pre condition.
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*/
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break;
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}
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vioapic_set_irq_nolock(vm, irq, operation);
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spinlock_release(&(vioapic->mtx));
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}
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@ -240,6 +243,16 @@ vioapic_indirect_read(struct acrn_vioapic *vioapic, uint32_t addr)
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return 0;
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}
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static inline bool vioapic_need_intr(struct acrn_vioapic *vioapic, uint16_t pin)
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{
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uint32_t lvl =(uint32_t)bitmap_test(pin & 0x3FU,
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&vioapic->pin_state[pin >> 6U]);
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union ioapic_rte rte = vioapic->rtbl[pin];
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return !!((((rte.full & IOAPIC_RTE_INTPOL) != 0UL) && lvl == 0U) ||
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(((rte.full & IOAPIC_RTE_INTPOL) == 0UL) && lvl != 0U));
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}
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/*
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* Due to the race between vcpus, ensure to do spinlock_obtain(&(vioapic->mtx))
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* & spinlock_release(&(vioapic->mtx)) by caller.
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@ -356,11 +369,10 @@ vioapic_indirect_write(struct acrn_vioapic *vioapic, uint32_t addr,
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*/
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if (((vioapic->rtbl[pin].full & IOAPIC_RTE_INTMASK) ==
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IOAPIC_RTE_INTMCLR) &&
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((vioapic->rtbl[pin].full & IOAPIC_RTE_REM_IRR) == 0UL) &&
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(vioapic->acnt[pin] > 0)) {
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((vioapic->rtbl[pin].full & IOAPIC_RTE_REM_IRR) == 0UL)
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&& vioapic_need_intr(vioapic, (uint16_t)pin)) {
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dev_dbg(ACRN_DBG_IOAPIC,
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"ioapic pin%hhu: asserted at rtbl write, acnt %d",
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pin, vioapic->acnt[pin]);
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"ioapic pin%hhu: asserted at rtbl write", pin);
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vioapic_send_intr(vioapic, pin);
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}
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@ -453,10 +465,9 @@ vioapic_process_eoi(struct vm *vm, uint32_t vector)
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}
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vioapic->rtbl[pin].full &= (~IOAPIC_RTE_REM_IRR);
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if (vioapic->acnt[pin] > 0) {
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if (vioapic_need_intr(vioapic, (uint16_t)pin)) {
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dev_dbg(ACRN_DBG_IOAPIC,
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"ioapic pin%hhu: asserted at eoi, acnt %d",
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pin, vioapic->acnt[pin]);
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"ioapic pin%hhu: asserted at eoi", pin);
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vioapic_send_intr(vioapic, pin);
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}
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}
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@ -37,6 +37,7 @@
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#define VIOAPIC_SIZE 4096UL
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#define REDIR_ENTRIES_HW 120U /* SOS align with native ioapic */
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#define STATE_BITMAP_SIZE INT_DIV_ROUNDUP(REDIR_ENTRIES_HW, 64U)
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struct acrn_vioapic {
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struct vm *vm;
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@ -44,8 +45,8 @@ struct acrn_vioapic {
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uint32_t id;
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uint32_t ioregsel;
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union ioapic_rte rtbl[REDIR_ENTRIES_HW];
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/* sum of pin asserts (+1) and deasserts (-1) */
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int32_t acnt[REDIR_ENTRIES_HW];
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/* pin_state status bitmap: 1 - high, 0 - low */
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uint64_t pin_state[STATE_BITMAP_SIZE];
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};
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void vioapic_init(struct vm *vm);
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@ -53,6 +54,7 @@ void vioapic_cleanup(struct acrn_vioapic *vioapic);
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void vioapic_reset(struct acrn_vioapic *vioapic);
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void vioapic_set_irq(struct vm *vm, uint32_t irq, uint32_t operation);
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void vioapic_set_irq_nolock(struct vm *vm, uint32_t irq, uint32_t operation);
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void vioapic_update_tmr(struct vcpu *vcpu);
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uint32_t vioapic_pincount(struct vm *vm);
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