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hv: support CAT on hybrid platform

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On hybrid platform(e.g. ADL), there may be multiple instances of same level caches for different type of processors,
The current design only supports one global `rdt_info` for each RDT resource type.
In order to support hybrid platform, this patch introduce `rdt_ins` to represents the "instance".
Also, the number of `rdt_info` is dynamically generated by config-tool to match with physical board.

Tracked-On: projectacrn#6690
Signed-off-by: Tw <wei.tan@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
This commit is contained in:
Tw
2022-03-28 09:35:51 +08:00
committed by acrnsi-robot
parent 19da21c898
commit 3c384a489c
4 changed files with 89 additions and 82 deletions
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16
hypervisor/include/arch/x86/asm/board.h
View File

@@ -15,12 +15,10 @@
/* forward declarations */
struct acrn_vm;
struct platform_clos_info {
union {
uint16_t mba_delay;
uint32_t clos_mask;
}value;
uint32_t msr_index;
/* user configured mask and MSR info for each CLOS*/
union clos_config {
uint16_t mba_delay;
uint32_t clos_mask;
};
struct vmsix_on_msi_info {
@@ -31,9 +29,9 @@ struct vmsix_on_msi_info {
extern struct dmar_info plat_dmar_info;
#ifdef CONFIG_RDT_ENABLED
extern struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
extern struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
extern struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
extern union clos_config platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
extern union clos_config platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
extern union clos_config platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
#endif
extern const struct cpu_state_table board_cpu_state_tbl;

22
hypervisor/include/arch/x86/asm/rdt.h
View File

@@ -22,15 +22,14 @@ enum {
extern const uint16_t hv_clos;
/* The intel Resource Director Tech(RDT) based Allocation Tech support */
struct rdt_info {
/* The instance of one RES_ID */
struct rdt_ins {
union {
struct {
uint32_t bitmask; /* A bitmask where each set bit indicates the corresponding cache way
may be used by other entities in the platform (e.g. GPU) */
uint16_t cbm_len; /* Length of Cache mask in bits */
bool is_cdp_enabled; /* True if support CDP */
uint32_t msr_qos_cfg; /* MSR addr to IA32_L3/L2_QOS_CFG */
} cache;
struct rdt_membw {
uint16_t mba_max; /* Max MBA delay throttling value supported */
@@ -38,14 +37,25 @@ struct rdt_info {
} membw;
} res;
uint16_t num_closids; /* Number of CLOSIDs available, 0 indicates resource is not supported.*/
uint32_t res_id;
uint32_t num_clos_config; /* Number of element in clos_config_array */
union clos_config *clos_config_array;
uint64_t cpu_mask; /* the CPUs this RDT applies */
};
/* The intel Resource Director Tech(RDT) based Allocation Tech support */
struct rdt_type {
uint32_t res_id; /* RDT_RESID_L3/RDT_RESID_L2/RDT_RESID_MBA */
uint32_t msr_qos_cfg; /* MSR addr to IA32_L3/L2_QOS_CFG */
uint32_t msr_base; /* MSR base to program clos value */
struct platform_clos_info *platform_clos_array; /* user configured mask and MSR info for each CLOS*/
uint32_t num_ins; /* Number of element in ins_array */
struct rdt_ins *ins_array;
};
void setup_clos(uint16_t pcpu_id);
uint64_t clos2pqr_msr(uint16_t clos);
bool is_platform_rdt_capable(void);
const struct rdt_info *get_rdt_res_cap_info(int res);
const struct rdt_ins *get_rdt_res_ins(int res, uint16_t pcpu_id);
#endif /* RDT_H */