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hv: add "invariant TSC" cap detection

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ACRN HV is designed/implemented with "invariant TSC" capability, which wasn't checked at boot time.
This commit adds the "invairant TSC" detection, ACRN fails to boot if there wasn't "invariant TSC" capability.

Tracked-On: #3636
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Yan, Like
2019-09-02 13:58:59 +08:00
committed by ACRN System Integration
parent be0a4b692b
commit 3f84acda09
4 changed files with 16 additions and 2 deletions
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3
hypervisor/include/arch/x86/cpufeatures.h
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@@ -91,4 +91,7 @@
#define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5U) + 26U)
#define X86_FEATURE_LM ((FEAT_8000_0001_EDX << 5U) + 29U)
/* Intel-defined CPU features, CPUID level 0x80000007 (EDX)*/
#define X86_FEATURE_INVA_TSC ((FEAT_8000_0007_EDX << 5U) + 8U)
#endif /* CPUFEATURES_H */