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hv: add "invariant TSC" cap detection

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ACRN HV is designed/implemented with "invariant TSC" capability, which wasn't checked at boot time.
This commit adds the "invairant TSC" detection, ACRN fails to boot if there wasn't "invariant TSC" capability.

Tracked-On: #3636
Signed-off-by: Yan, Like <like.yan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Yan, Like 2019-09-02 13:58:59 +08:00 committed by ACRN System Integration
parent be0a4b692b
commit 3f84acda09
4 changed files with 16 additions and 2 deletions
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9
hypervisor/arch/x86/cpu_caps.c
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@ -241,6 +241,11 @@ void init_pcpu_capabilities(void)
&boot_cpu_data.cpuid_leaves[FEAT_8000_0001_EDX]); &boot_cpu_data.cpuid_leaves[FEAT_8000_0001_EDX]);
} }
if (boot_cpu_data.extended_cpuid_level >= CPUID_EXTEND_INVA_TSC) {
cpuid(CPUID_EXTEND_INVA_TSC, &eax, &unused, &unused,
&boot_cpu_data.cpuid_leaves[FEAT_8000_0007_EDX]);
}
if (boot_cpu_data.extended_cpuid_level >= CPUID_EXTEND_ADDRESS_SIZE) { if (boot_cpu_data.extended_cpuid_level >= CPUID_EXTEND_ADDRESS_SIZE) {
cpuid(CPUID_EXTEND_ADDRESS_SIZE, &eax, cpuid(CPUID_EXTEND_ADDRESS_SIZE, &eax,
&boot_cpu_data.cpuid_leaves[FEAT_8000_0008_EBX], &boot_cpu_data.cpuid_leaves[FEAT_8000_0008_EBX],
@ -366,6 +371,10 @@ int32_t detect_hardware_support(void)
(boot_cpu_data.virt_bits == 0U)) { (boot_cpu_data.virt_bits == 0U)) {
printf("%s, can't detect Linear/Physical Address size\n", __func__); printf("%s, can't detect Linear/Physical Address size\n", __func__);
ret = -ENODEV; ret = -ENODEV;
} else if (!pcpu_has_cap(X86_FEATURE_INVA_TSC)) {
/* check invariant TSC */
printf("%s, invariant TSC not supported\n", __func__);
ret = -ENODEV;
} else if (!pcpu_has_cap(X86_FEATURE_TSC_DEADLINE)) { } else if (!pcpu_has_cap(X86_FEATURE_TSC_DEADLINE)) {
/* lapic TSC deadline timer */ /* lapic TSC deadline timer */
printf("%s, TSC deadline not supported\n", __func__); printf("%s, TSC deadline not supported\n", __func__);

5
hypervisor/include/arch/x86/cpu_caps.h
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@ -22,8 +22,9 @@
#define FEAT_7_0_EDX 4U /* CPUID[EAX=7,ECX=0].EDX */ #define FEAT_7_0_EDX 4U /* CPUID[EAX=7,ECX=0].EDX */
#define FEAT_8000_0001_ECX 5U /* CPUID[8000_0001].ECX */ #define FEAT_8000_0001_ECX 5U /* CPUID[8000_0001].ECX */
#define FEAT_8000_0001_EDX 6U /* CPUID[8000_0001].EDX */ #define FEAT_8000_0001_EDX 6U /* CPUID[8000_0001].EDX */
#define FEAT_8000_0008_EBX 7U /* CPUID[8000_0008].EAX */ #define FEAT_8000_0007_EDX 7U /* CPUID[8000_0007].EDX */
#define FEATURE_WORDS 8U #define FEAT_8000_0008_EBX 8U /* CPUID[8000_0008].EBX */
#define FEATURE_WORDS 9U
struct cpuinfo_x86 { struct cpuinfo_x86 {
uint8_t family, model; uint8_t family, model;

3
hypervisor/include/arch/x86/cpufeatures.h
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@ -91,4 +91,7 @@
#define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5U) + 26U) #define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5U) + 26U)
#define X86_FEATURE_LM ((FEAT_8000_0001_EDX << 5U) + 29U) #define X86_FEATURE_LM ((FEAT_8000_0001_EDX << 5U) + 29U)
/* Intel-defined CPU features, CPUID level 0x80000007 (EDX)*/
#define X86_FEATURE_INVA_TSC ((FEAT_8000_0007_EDX << 5U) + 8U)
#endif /* CPUFEATURES_H */ #endif /* CPUFEATURES_H */

1
hypervisor/include/arch/x86/cpuid.h
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@ -119,6 +119,7 @@
#define CPUID_EXTEND_FUNCTION_2 0x80000002U #define CPUID_EXTEND_FUNCTION_2 0x80000002U
#define CPUID_EXTEND_FUNCTION_3 0x80000003U #define CPUID_EXTEND_FUNCTION_3 0x80000003U
#define CPUID_EXTEND_FUNCTION_4 0x80000004U #define CPUID_EXTEND_FUNCTION_4 0x80000004U
#define CPUID_EXTEND_INVA_TSC 0x80000007U
#define CPUID_EXTEND_ADDRESS_SIZE 0x80000008U #define CPUID_EXTEND_ADDRESS_SIZE 0x80000008U