HV: irq: convert hexadecimals used in bitops to unsigned

Signed-off-by: Junjie Mao <junjie.mao@intel.com>

hypervisor/arch/x86/guest/vioapic.c

@@ -223,15 +223,16 @@ vioapic_update_tmr(struct vcpu *vcpu)
 static uint32_t
 vioapic_read(struct vioapic *vioapic, uint32_t addr)
 {
-	int regnum, pin, rshift;
+	uint32_t regnum;
+	int pin, rshift;
 
-	regnum = addr & 0xff;
+	regnum = addr & 0xffU;
 	switch (regnum) {
 	case IOAPIC_ID:
 		return vioapic->id;
 	case IOAPIC_VER:
-		return ((vioapic_pincount(vioapic->vm) - 1) << MAX_RTE_SHIFT)
-		       | 0x11;
+		return ((vioapic_pincount(vioapic->vm) - 1U) << MAX_RTE_SHIFT)
+		       | 0x11U;
 	case IOAPIC_ARB:
 		return vioapic->id;
 	default:
@@ -290,9 +291,10 @@ vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
 {
 	uint64_t data64, mask64;
 	uint64_t last, new, changed;
-	int regnum, pin, lshift;
+	uint32_t regnum;
+	int pin, lshift;
 
-	regnum = addr & 0xff;
+	regnum = addr & 0xffUL;
 	switch (regnum) {
 	case IOAPIC_ID:
 		vioapic->id = data & APIC_ID_MASK;

hypervisor/arch/x86/guest/vlapic.c

@@ -41,10 +41,10 @@
 
 #define VLAPIC_VERSION		(16)
 
-#define	APICBASE_RESERVED	0x000002ff
-#define	APICBASE_BSP		0x00000100
-#define	APICBASE_X2APIC		0x00000400
-#define	APICBASE_ENABLED	0x00000800
+#define	APICBASE_RESERVED	0x000002ffU
+#define	APICBASE_BSP		0x00000100U
+#define	APICBASE_X2APIC		0x00000400U
+#define	APICBASE_ENABLED	0x00000800U
 
 #define ACRN_DBG_LAPIC	6
 
@@ -740,7 +740,7 @@ vlapic_update_ppr(struct vlapic *vlapic)
 		isrptr = &vlapic->apic_page->isr[0];
 		for (vector = 0; vector < 256; vector++) {
 			idx = vector / 32;
-			if ((isrptr[idx].val & (1 << (vector % 32))) != 0U) {
+			if ((isrptr[idx].val & (1U << (vector % 32))) != 0U) {
 				if ((i > vlapic->isrvec_stk_top) ||
 					((i < ISRVEC_STK_SIZE) &&
 					(vlapic->isrvec_stk[i] != vector))) {
@@ -755,7 +755,7 @@ vlapic_update_ppr(struct vlapic *vlapic)
 	if (PRIO(tpr) >= PRIO(isrvec))
 		ppr = tpr;
 	else
-		ppr = isrvec & 0xf0;
+		ppr = isrvec & 0xf0U;
 
 	vlapic->apic_page->ppr = ppr;
 	dev_dbg(ACRN_DBG_LAPIC, "%s 0x%02x", __func__, ppr);
@@ -901,14 +901,14 @@ vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
 		 * In the "Flat Model" the MDA is interpreted as an 8-bit wide
 		 * bitmask. This model is only available in the xAPIC mode.
 		 */
-		mda_flat_ldest = dest & 0xff;
+		mda_flat_ldest = dest & 0xffU;
 
 		/*
 		 * In the "Cluster Model" the MDA is used to identify a
 		 * specific cluster and a set of APICs in that cluster.
 		 */
-		mda_cluster_id = (dest >> 4) & 0xf;
-		mda_cluster_ldest = dest & 0xf;
+		mda_cluster_id = (dest >> 4) & 0xfU;
+		mda_cluster_ldest = dest & 0xfU;
 
 		/*
 		 * Logical mode: match each APIC that has a bit set
@@ -931,7 +931,7 @@ vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
 					APIC_DFR_MODEL_CLUSTER) {
 
 				cluster = ldr >> 28;
-				ldest = (ldr >> 24) & 0xf;
+				ldest = (ldr >> 24) & 0xfU;
 
 				if (cluster != mda_cluster_id)
 					continue;
@@ -998,7 +998,7 @@ vlapic_set_cr8(struct vlapic *vlapic, uint64_t val)
 {
 	uint8_t tpr;
 
-	if ((val & ~0xf) != 0U) {
+	if ((val & ~0xfUL) != 0U) {
 		vcpu_inject_gp(vlapic->vcpu, 0);
 		return;
 	}
@@ -1202,7 +1202,7 @@ vlapic_intr_accepted(struct vlapic *vlapic, uint32_t vector)
 	VLAPIC_CTR_IRR(vlapic, "vlapic_intr_accepted");
 
 	isrptr = &lapic->isr[0];
-	isrptr[idx].val |= 1 << (vector % 32);
+	isrptr[idx].val |= 1U << (vector % 32);
 	VLAPIC_CTR_ISR(vlapic, "vlapic_intr_accepted");
 
 	/*
@@ -1283,7 +1283,7 @@ vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
 		goto done;
 	}
 
-	offset &= ~3;
+	offset &= ~0x3UL;
 	switch (offset) {
 	case APIC_OFFSET_ID:
 		*data = lapic->id;
@@ -1407,7 +1407,7 @@ vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
 	uint32_t *regptr;
 	int retval;
 
-	ASSERT((offset & 0xf) == 0 && offset < CPU_PAGE_SIZE,
+	ASSERT((offset & 0xfUL) == 0 && offset < CPU_PAGE_SIZE,
 		"%s: invalid offset %#lx", __func__, offset);
 
 	dev_dbg(ACRN_DBG_LAPIC, "vlapic write offset %#lx, data %#lx",
@@ -1433,7 +1433,7 @@ vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
 		vlapic_id_write_handler(vlapic);
 		break;
 	case APIC_OFFSET_TPR:
-		vlapic_set_tpr(vlapic, data & 0xff);
+		vlapic_set_tpr(vlapic, data & 0xffUL);
 		break;
 	case APIC_OFFSET_EOI:
 		vlapic_process_eoi(vlapic);
@@ -1745,7 +1745,7 @@ vlapic_set_intr(struct vcpu *vcpu, uint32_t vector, bool level)
 	 * According to section "Maskable Hardware Interrupts" in Intel SDM
 	 * vectors 16 through 255 can be delivered through the local APIC.
 	 */
-	if (vector < 16 || vector > 255)
+	if (vector < 16U || vector > 255U)
 		return -EINVAL;
 
 	vlapic = vcpu->arch_vcpu.vlapic;
@@ -1808,11 +1808,11 @@ vlapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg)
 	 * the Redirection Hint and Destination Mode are '1' and
 	 * physical otherwise.
 	 */
-	dest = (addr >> 12) & 0xff;
+	dest = (addr >> 12) & 0xffU;
 	phys = ((addr & (MSI_ADDR_RH | MSI_ADDR_LOG)) !=
 			(MSI_ADDR_RH | MSI_ADDR_LOG));
 	delmode = msg & APIC_DELMODE_MASK;
-	vec = msg & 0xff;
+	vec = msg & 0xffUL;
 
 	dev_dbg(ACRN_DBG_LAPIC, "lapic MSI %s dest %#x, vec %d",
 		phys ? "physical" : "logical", dest, vec);
@@ -1937,7 +1937,7 @@ vlapic_mmio_write(struct vcpu *vcpu, uint64_t gpa, uint64_t wval, int size)
 	 * Memory mapped local apic accesses must be 4 bytes wide and
 	 * aligned on a 16-byte boundary.
 	 */
-	if (size != 4 || (off & 0xf) != 0U)
+	if (size != 4 || (off & 0xfUL) != 0U)
 		return -EINVAL;
 
 	vlapic = vcpu->arch_vcpu.vlapic;
@@ -1960,8 +1960,8 @@ vlapic_mmio_read(struct vcpu *vcpu, uint64_t gpa, uint64_t *rval,
 	 * 16-byte boundary. They are also suggested to be 4 bytes
 	 * wide, alas not all OSes follow suggestions.
 	 */
-	off &= ~3;
-	if ((off & 0xf) != 0U)
+	off &= ~0x3UL;
+	if ((off & 0xfUL) != 0UL)
 		return -EINVAL;
 
 	vlapic = vcpu->arch_vcpu.vlapic;
@@ -2116,7 +2116,7 @@ apicv_pending_intr(struct vlapic *vlapic, __unused uint32_t *vecptr)
 		return 0;
 
 	lapic = vlapic->apic_page;
-	ppr = lapic->ppr & 0xF0;
+	ppr = lapic->ppr & 0xF0U;
 
 	if (ppr == 0)
 		return 1;
@@ -2124,7 +2124,7 @@ apicv_pending_intr(struct vlapic *vlapic, __unused uint32_t *vecptr)
 	for (i = 3; i >= 0; i--) {
 		pirval = pir_desc->pir[i];
 		if (pirval != 0) {
-			vpr = (i * 64 + fls64(pirval)) & 0xF0;
+			vpr = (i * 64 + fls64(pirval)) & 0xF0U;
 			return (vpr > ppr);
 		}
 	}
@@ -2257,10 +2257,10 @@ apicv_inject_pir(struct vlapic *vlapic)
 		rvi = pirbase + fls64(pirval);
 
 		intr_status_old = (uint16_t)
-				(0xFFFF &
+				(0xFFFFUL &
 				exec_vmread(VMX_GUEST_INTR_STATUS));
 
-		intr_status_new = (intr_status_old & 0xFF00) | rvi;
+		intr_status_new = (intr_status_old & 0xFF00U) | rvi;
 		if (intr_status_new > intr_status_old)
 			exec_vmwrite(VMX_GUEST_INTR_STATUS,
 					intr_status_new);
@@ -2314,7 +2314,7 @@ int veoi_vmexit_handler(struct vcpu *vcpu)
 
 	vlapic = vcpu->arch_vcpu.vlapic;
 	lapic = vlapic->apic_page;
-	vector = (vcpu->arch_vcpu.exit_qualification) & 0xFF;
+	vector = (vcpu->arch_vcpu.exit_qualification) & 0xFFUL;
 
 	tmrptr = &lapic->tmr[0];
 	idx = vector / 32;
@@ -2337,7 +2337,7 @@ int apic_write_vmexit_handler(struct vcpu *vcpu)
 	struct vlapic *vlapic = NULL;
 
 	qual = vcpu->arch_vcpu.exit_qualification;
-	offset = (qual & 0xFFF);
+	offset = (qual & 0xFFFUL);
 
 	handled = 1;
 	VCPU_RETAIN_RIP(vcpu);

hypervisor/arch/x86/guest/vpic.c

@@ -81,9 +81,9 @@ struct vpic {
  * Loop over all the pins in priority order from highest to lowest.
  */
 #define	PIC_PIN_FOREACH(pinvar, pic, tmpvar)			\
-	for (tmpvar = 0, pinvar = (pic->lowprio + 1) & 0x7;	\
+	for (tmpvar = 0, pinvar = (pic->lowprio + 1) & 0x7U;	\
 	    tmpvar < 8;						\
-	    tmpvar++, pinvar = (pinvar + 1) & 0x7)
+	    tmpvar++, pinvar = (pinvar + 1) & 0x7U)
 
 static void vpic_set_pinstate(struct vpic *vpic, int pin, bool newstate);
 
@@ -102,7 +102,7 @@ static inline int vpic_get_highest_isrpin(struct pic *pic)
 	int i;
 
 	PIC_PIN_FOREACH(pin, pic, i) {
-		bit = (1 << pin);
+		bit = (1U << pin);
 
 		if ((pic->service & bit) != 0U) {
 			/*
@@ -131,7 +131,7 @@ static inline int vpic_get_highest_irrpin(struct pic *pic)
 	 */
 	serviced = pic->service;
 	if (pic->sfn)
-		serviced &= ~(1 << 2);
+		serviced &= ~(1U << 2);
 
 	/*
 	 * In 'Special Mask Mode', when a mask bit is set in OCW1 it inhibits
@@ -143,7 +143,7 @@ static inline int vpic_get_highest_irrpin(struct pic *pic)
 		serviced = 0;
 
 	PIC_PIN_FOREACH(pin, pic, tmp) {
-		bit = 1 << pin;
+		bit = 1U << pin;
 
 		/*
 		 * If there is already an interrupt in service at the same
@@ -282,7 +282,7 @@ static int vpic_icw2(struct vpic *vpic, struct pic *pic, uint8_t val)
 	dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic icw2 0x%x\n",
 		vpic->vm, val);
 
-	pic->irq_base = val & 0xf8;
+	pic->irq_base = val & 0xf8U;
 
 	pic->icw_num++;
 
@@ -355,7 +355,7 @@ static int vpic_ocw1(struct vpic *vpic, struct pic *pic, uint8_t val)
 	dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic ocw1 0x%x\n",
 		vpic->vm, val);
 
-	pic->mask = val & 0xff;
+	pic->mask = val & 0xffU;
 
 	/* query and setup if pin/irq is for passthrough device */
 	PIC_PIN_FOREACH(pin, pic, i) {
@@ -396,28 +396,28 @@ static int vpic_ocw2(struct vpic *vpic, struct pic *pic, uint8_t val)
 
 		if ((val & OCW2_SL) != 0) {
 			/* specific EOI */
-			isr_bit = val & 0x7;
+			isr_bit = val & 0x7U;
 		} else {
 			/* non-specific EOI */
 			isr_bit = vpic_get_highest_isrpin(pic);
 		}
 
 		if (isr_bit != -1) {
-			pic->service &= ~(1 << isr_bit);
+			pic->service &= ~(1U << isr_bit);
 
 			if (pic->rotate)
 				pic->lowprio = isr_bit;
 		}
 
 		/* if level ack PTDEV */
-		if ((pic->elc & (1 << (isr_bit & 0x7))) != 0U) {
+		if ((pic->elc & (1U << (isr_bit & 0x7U))) != 0U) {
 			ptdev_intx_ack(vpic->vm,
 				master_pic(vpic, pic) ? isr_bit : isr_bit + 8,
 				PTDEV_VPIN_PIC);
 		}
 	} else if ((val & OCW2_SL) != 0 && pic->rotate == true) {
 		/* specific priority */
-		pic->lowprio = val & 0x7;
+		pic->lowprio = val & 0x7U;
 	}
 
 	return 0;
@@ -457,28 +457,28 @@ static void vpic_set_pinstate(struct vpic *vpic, int pin, bool newstate)
 
 	pic = &vpic->pic[pin >> 3];
 
-	oldcnt = pic->acnt[pin & 0x7];
+	oldcnt = pic->acnt[pin & 0x7U];
 	if (newstate)
-		pic->acnt[pin & 0x7]++;
+		pic->acnt[pin & 0x7U]++;
 	else
-		pic->acnt[pin & 0x7]--;
-	newcnt = pic->acnt[pin & 0x7];
+		pic->acnt[pin & 0x7U]--;
+	newcnt = pic->acnt[pin & 0x7U];
 
 	if (newcnt < 0) {
 		pr_warn("pic pin%d: bad acnt %d\n", pin, newcnt);
 	}
 
-	level = ((vpic->pic[pin >> 3].elc & (1 << (pin & 0x7))) != 0);
+	level = ((vpic->pic[pin >> 3].elc & (1 << (pin & 0x7U))) != 0);
 
 	if ((oldcnt == 0 && newcnt == 1) || (newcnt > 0 && level == true)) {
 		/* rising edge or level */
 		dev_dbg(ACRN_DBG_PIC, "pic pin%d: asserted\n", pin);
-		pic->request |= (1 << (pin & 0x7));
+		pic->request |= (1 << (pin & 0x7U));
 	} else if (oldcnt == 1 && newcnt == 0) {
 		/* falling edge */
 		dev_dbg(ACRN_DBG_PIC, "pic pin%d: deasserted\n", pin);
 		if (level)
-			pic->request &= ~(1 << (pin & 0x7));
+			pic->request &= ~(1 << (pin & 0x7U));
 	} else {
 		dev_dbg(ACRN_DBG_PIC,
 			"pic pin%d: %s, ignored, acnt %d\n",
@@ -565,9 +565,9 @@ int vpic_set_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger trigger)
 	VPIC_LOCK(vpic);
 
 	if (trigger == LEVEL_TRIGGER)
-		vpic->pic[irq >> 3].elc |=  1 << (irq & 0x7);
+		vpic->pic[irq >> 3].elc |=  1U << (irq & 0x7U);
 	else
-		vpic->pic[irq >> 3].elc &=  ~(1 << (irq & 0x7));
+		vpic->pic[irq >> 3].elc &=  ~(1U << (irq & 0x7U));
 
 	VPIC_UNLOCK(vpic);
 
@@ -585,7 +585,7 @@ int vpic_get_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger *trigger
 	if (vpic == NULL)
 		return -EINVAL;
 
-	if ((vpic->pic[irq>>3].elc & (1 << (irq & 0x7))) != 0U)
+	if ((vpic->pic[irq>>3].elc & (1U << (irq & 0x7U))) != 0U)
 		*trigger = LEVEL_TRIGGER;
 	else
 		*trigger = EDGE_TRIGGER;
@@ -641,7 +641,7 @@ static void vpic_pin_accepted(struct pic *pic, int pin)
 		if (pic->rotate == true)
 			pic->lowprio = pin;
 	} else {
-		pic->service |= (1 << pin);
+		pic->service |= (1U << pin);
 	}
 }
 
@@ -654,9 +654,9 @@ void vpic_intr_accepted(struct vm *vm, uint32_t vector)
 
 	VPIC_LOCK(vpic);
 
-	pin = vector & 0x7;
+	pin = vector & 0x7U;
 
-	if ((vector & ~0x7) == vpic->pic[1].irq_base) {
+	if ((vector & ~0x7U) == vpic->pic[1].irq_base) {
 		vpic_pin_accepted(&vpic->pic[1], pin);
 		/*
 		 * If this vector originated from the slave,
@@ -684,9 +684,9 @@ static int vpic_read(struct vpic *vpic, struct pic *pic,
 		pin = vpic_get_highest_irrpin(pic);
 		if (pin >= 0) {
 			vpic_pin_accepted(pic, pin);
-			*eax = 0x80 | pin;
+			*eax = 0x80U | pin;
 		} else {
-			*eax = 0;
+			*eax = 0U;
 		}
 	} else {
 		if ((port & ICU_IMR_OFFSET) != 0) {
@@ -863,9 +863,9 @@ static int vpic_elc_handler(struct vm *vm, bool in, int port, int bytes,
 		 * be programmed for level mode.
 		 */
 		if (is_master)
-			vpic->pic[0].elc = (*eax & 0xf8);
+			vpic->pic[0].elc = (*eax & 0xf8U);
 		else
-			vpic->pic[1].elc = (*eax & 0xde);
+			vpic->pic[1].elc = (*eax & 0xdeU);
 	}
 
 	VPIC_UNLOCK(vpic);

hypervisor/arch/x86/ioapic.c

@@ -34,41 +34,41 @@ static struct ioapic_rte saved_rte[CONFIG_NR_IOAPICS][IOAPIC_MAX_PIN];
  * hardcoded here
  */
 uint16_t legacy_irq_to_pin[NR_LEGACY_IRQ] = {
-	2, /* IRQ0*/
-	1, /* IRQ1*/
-	0, /* IRQ2 connected to Pin0 (ExtInt source of PIC) if existing */
-	3, /* IRQ3*/
-	4, /* IRQ4*/
-	5, /* IRQ5*/
-	6, /* IRQ6*/
-	7, /* IRQ7*/
-	8, /* IRQ8*/
-	9 | IOAPIC_RTE_TRGRLVL, /* IRQ9*/
-	10, /* IRQ10*/
-	11, /* IRQ11*/
-	12, /* IRQ12*/
-	13, /* IRQ13*/
-	14, /* IRQ14*/
-	15, /* IRQ15*/
+	2U, /* IRQ0*/
+	1U, /* IRQ1*/
+	0U, /* IRQ2 connected to Pin0 (ExtInt source of PIC) if existing */
+	3U, /* IRQ3*/
+	4U, /* IRQ4*/
+	5U, /* IRQ5*/
+	6U, /* IRQ6*/
+	7U, /* IRQ7*/
+	8U, /* IRQ8*/
+	9U | IOAPIC_RTE_TRGRLVL, /* IRQ9*/
+	10U, /* IRQ10*/
+	11U, /* IRQ11*/
+	12U, /* IRQ12*/
+	13U, /* IRQ13*/
+	14U, /* IRQ14*/
+	15U, /* IRQ15*/
 };
 
 uint16_t pic_ioapic_pin_map[NR_LEGACY_PIN] = {
-	2, /* pin0*/
-	1, /* pin1*/
-	0, /* pin2*/
-	3, /* pin3*/
-	4, /* pin4*/
-	5, /* pin5*/
-	6, /* pin6*/
-	7, /* pin7*/
-	8, /* pin8*/
-	9, /* pin9*/
-	10, /* pin10*/
-	11, /* pin11*/
-	12, /* pin12*/
-	13, /* pin13*/
-	14, /* pin14*/
-	15, /* pin15*/
+	2U, /* pin0*/
+	1U, /* pin1*/
+	0U, /* pin2*/
+	3U, /* pin3*/
+	4U, /* pin4*/
+	5U, /* pin5*/
+	6U, /* pin6*/
+	7U, /* pin7*/
+	8U, /* pin8*/
+	9U, /* pin9*/
+	10U, /* pin10*/
+	11U, /* pin11*/
+	12U, /* pin12*/
+	13U, /* pin13*/
+	14U, /* pin14*/
+	15U, /* pin15*/
 };
 
 static void *map_ioapic(uint64_t ioapic_paddr)
@@ -167,7 +167,7 @@ create_rte_for_legacy_irq(uint32_t irq, uint32_t vr)
 	rte.lo_32 |= IOAPIC_RTE_INTALO;
 
 	/* Dest field: legacy irq fixed to CPU0 */
-	rte.hi_32 |= 1 << 24;
+	rte.hi_32 |= 1U << 24;
 
 	return rte;
 }
@@ -327,7 +327,7 @@ void setup_ioapic_irq(void)
 
 			if (gsi < NR_LEGACY_IRQ)
 				gsi_table[gsi].pin =
-					legacy_irq_to_pin[gsi] & 0xff;
+					legacy_irq_to_pin[gsi] & 0xffU;
 			else
 				gsi_table[gsi].pin = pin;
 

hypervisor/arch/x86/irq.c

@@ -41,10 +41,10 @@ spurious_handler_t spurious_handler;
 
 static void init_irq_desc(void)
 {
-	int i, page_num = 0;
-	int desc_size = NR_MAX_IRQS * sizeof(struct irq_desc);
+	uint32_t i, page_num = 0;
+	uint32_t desc_size = NR_MAX_IRQS * sizeof(struct irq_desc);
 
-	page_num = (desc_size + CPU_PAGE_SIZE-1) >> CPU_PAGE_SHIFT;
+	page_num = (desc_size + CPU_PAGE_SIZE - 1U) >> CPU_PAGE_SHIFT;
 
 	irq_desc_base = alloc_pages(page_num);