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https://github.com/projectacrn/acrn-hypervisor.git
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HV: mmu: convert hexadecimals used in bitops to unsigned
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao
lijinxia
parent
7b548e87db
commit
f4bd0798e0
@ -11,14 +11,14 @@ static void set_tss_desc(union tss_64_descriptor *desc,
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{
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uint32_t u1, u2, u3;
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u1 = ((uint64_t)tss << 16) & 0xFFFFFFFF;
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u2 = (uint64_t)tss & 0xFF000000;
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u3 = ((uint64_t)tss & 0x00FF0000) >> 16;
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u1 = (uint32_t)(((uint64_t)tss << 16U) & 0xFFFFFFFFU);
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u2 = (uint32_t)((uint64_t)tss & 0xFF000000U);
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u3 = (uint32_t)(((uint64_t)tss & 0x00FF0000U) >> 16U);
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desc->fields.low32.value = u1 | (tss_limit & 0xFFFF);
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desc->fields.base_addr_63_32 = (uint32_t)((uint64_t)tss >> 32);
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desc->fields.high32.value = (u2 | ((uint32_t)type << 8) | 0x8000 | u3);
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desc->fields.low32.value = u1 | (tss_limit & 0xFFFFU);
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desc->fields.base_addr_63_32 = (uint32_t)((uint64_t)tss >> 32U);
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desc->fields.high32.value = (u2 | ((uint32_t)type << 8U) | 0x8000U | u3);
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}
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void load_gdtr_and_tr(void)
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@ -28,11 +28,11 @@ void load_gdtr_and_tr(void)
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struct tss_64 *tss = &get_cpu_var(tss);
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/* first entry is not used */
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gdt->rsvd = 0xAAAAAAAAAAAAAAAA;
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gdt->rsvd = 0xAAAAAAAAAAAAAAAAUL;
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/* ring 0 code sel descriptor */
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gdt->host_gdt_code_descriptor.value = 0x00Af9b000000ffff;
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gdt->host_gdt_code_descriptor.value = 0x00Af9b000000ffffUL;
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/* ring 0 data sel descriptor */
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gdt->host_gdt_data_descriptor.value = 0x00cf93000000ffff;
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gdt->host_gdt_data_descriptor.value = 0x00cf93000000ffffUL;
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tss->ist1 = (uint64_t)get_cpu_var(mc_stack) + CONFIG_STACK_SIZE;
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tss->ist2 = (uint64_t)get_cpu_var(df_stack) + CONFIG_STACK_SIZE;
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@ -178,12 +178,12 @@ void invept(struct vcpu *vcpu)
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struct invept_desc desc = {0};
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if (cpu_has_vmx_ept_cap(VMX_EPT_INVEPT_SINGLE_CONTEXT)) {
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desc.eptp = vcpu->vm->arch_vm.nworld_eptp | (3 << 3) | 6;
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desc.eptp = vcpu->vm->arch_vm.nworld_eptp | (3UL << 3U) | 6UL;
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_invept(INVEPT_TYPE_SINGLE_CONTEXT, desc);
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if (vcpu->vm->sworld_control.sworld_enabled &&
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vcpu->vm->arch_vm.sworld_eptp) {
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desc.eptp = vcpu->vm->arch_vm.sworld_eptp
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| (3 << 3) | 6;
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| (3UL << 3U) | 6UL;
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_invept(INVEPT_TYPE_SINGLE_CONTEXT, desc);
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}
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} else if (cpu_has_vmx_ept_cap(VMX_EPT_INVEPT_GLOBAL_CONTEXT))
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@ -990,10 +990,10 @@ static uint64_t break_page_table(struct map_params *map_params, void *paddr,
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/* Keep original attribute(here &0x3f)
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* bit 0(R) bit1(W) bit2(X) bit3~5 MT
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*/
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attr |= (entry.entry_val & 0x3f);
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attr |= (entry.entry_val & 0x3fUL);
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} else {
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/* Keep original attribute(here &0x7f) */
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attr |= (entry.entry_val & 0x7f);
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attr |= (entry.entry_val & 0x7fUL);
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}
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/* write all entries and keep original attr*/
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for (i = 0; i < IA32E_NUM_ENTRIES; i++) {
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@ -1007,7 +1007,7 @@ static uint64_t break_page_table(struct map_params *map_params, void *paddr,
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* (here &0x07)
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*/
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MEM_WRITE64(entry.entry_base + entry.entry_off,
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(entry.entry_val & 0x07) |
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(entry.entry_val & 0x07UL) |
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HVA2HPA(sub_tab_addr));
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} else {
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/* Write the table entry to map this memory,
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@ -1016,7 +1016,7 @@ static uint64_t break_page_table(struct map_params *map_params, void *paddr,
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* bit5(A) bit6(D or Ignore)
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*/
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MEM_WRITE64(entry.entry_base + entry.entry_off,
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(entry.entry_val & 0x7f) |
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(entry.entry_val & 0x7fUL) |
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HVA2HPA(sub_tab_addr));
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}
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}
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@ -1060,9 +1060,9 @@ static int modify_paging(struct map_params *map_params, void *paddr,
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* here attr & 0x7, rwx bit0:2
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*/
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ASSERT(!((map_params->page_table_type == PTT_EPT) &&
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(((attr & 0x7) == IA32E_EPT_W_BIT) ||
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((attr & 0x7) == (IA32E_EPT_W_BIT | IA32E_EPT_X_BIT)) ||
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(((attr & 0x7) == IA32E_EPT_X_BIT) &&
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(((attr & 0x7UL) == IA32E_EPT_W_BIT) ||
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((attr & 0x7UL) == (IA32E_EPT_W_BIT | IA32E_EPT_X_BIT)) ||
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(((attr & 0x7UL) == IA32E_EPT_X_BIT) &&
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!cpu_has_vmx_ept_cap(VMX_EPT_EXECUTE_ONLY)))),
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"incorrect memory attribute set!\n");
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/* Loop until the entire block of memory is appropriately
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@ -11,126 +11,126 @@
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#define IA32E_COMM_ENTRY_SIZE 8
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/* Definitions common for all IA-32e related paging entries */
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#define IA32E_COMM_P_BIT 0x0000000000000001
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#define IA32E_COMM_RW_BIT 0x0000000000000002
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#define IA32E_COMM_US_BIT 0x0000000000000004
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#define IA32E_COMM_PWT_BIT 0x0000000000000008
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#define IA32E_COMM_PCD_BIT 0x0000000000000010
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#define IA32E_COMM_A_BIT 0x0000000000000020
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#define IA32E_COMM_XD_BIT 0x8000000000000000
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#define IA32E_COMM_P_BIT 0x0000000000000001UL
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#define IA32E_COMM_RW_BIT 0x0000000000000002UL
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#define IA32E_COMM_US_BIT 0x0000000000000004UL
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#define IA32E_COMM_PWT_BIT 0x0000000000000008UL
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#define IA32E_COMM_PCD_BIT 0x0000000000000010UL
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#define IA32E_COMM_A_BIT 0x0000000000000020UL
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#define IA32E_COMM_XD_BIT 0x8000000000000000UL
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/* Defines for EPT paging entries */
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#define IA32E_EPT_R_BIT 0x0000000000000001
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#define IA32E_EPT_W_BIT 0x0000000000000002
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#define IA32E_EPT_X_BIT 0x0000000000000004
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#define IA32E_EPT_UNCACHED (0<<3)
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#define IA32E_EPT_WC (1<<3)
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#define IA32E_EPT_WT (4<<3)
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#define IA32E_EPT_WP (5<<3)
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#define IA32E_EPT_WB (6<<3)
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#define IA32E_EPT_MT_MASK (7<<3)
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#define IA32E_EPT_PAT_IGNORE 0x0000000000000040
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#define IA32E_EPT_ACCESS_FLAG 0x0000000000000100
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#define IA32E_EPT_DIRTY_FLAG 0x0000000000000200
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#define IA32E_EPT_SNOOP_CTRL 0x0000000000000800
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#define IA32E_EPT_SUPPRESS_VE 0x8000000000000000
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#define IA32E_EPT_R_BIT 0x0000000000000001UL
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#define IA32E_EPT_W_BIT 0x0000000000000002UL
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#define IA32E_EPT_X_BIT 0x0000000000000004UL
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#define IA32E_EPT_UNCACHED (0UL<<3)
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#define IA32E_EPT_WC (1UL<<3)
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#define IA32E_EPT_WT (4UL<<3)
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#define IA32E_EPT_WP (5UL<<3)
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#define IA32E_EPT_WB (6UL<<3)
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#define IA32E_EPT_MT_MASK (7UL<<3)
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#define IA32E_EPT_PAT_IGNORE 0x0000000000000040UL
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#define IA32E_EPT_ACCESS_FLAG 0x0000000000000100UL
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#define IA32E_EPT_DIRTY_FLAG 0x0000000000000200UL
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#define IA32E_EPT_SNOOP_CTRL 0x0000000000000800UL
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#define IA32E_EPT_SUPPRESS_VE 0x8000000000000000UL
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/* Definitions common or ignored for all IA-32e related paging entries */
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#define IA32E_COMM_D_BIT 0x0000000000000040
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#define IA32E_COMM_G_BIT 0x0000000000000100
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#define IA32E_COMM_D_BIT 0x0000000000000040UL
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#define IA32E_COMM_G_BIT 0x0000000000000100UL
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/* Definitions exclusive to a Page Map Level 4 Entry (PML4E) */
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#define IA32E_PML4E_INDEX_MASK_START 39
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#define IA32E_PML4E_ADDR_MASK 0x0000FF8000000000
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#define IA32E_PML4E_ADDR_MASK 0x0000FF8000000000UL
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/* Definitions exclusive to a Page Directory Pointer Table Entry (PDPTE) */
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#define IA32E_PDPTE_D_BIT 0x0000000000000040
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#define IA32E_PDPTE_PS_BIT 0x0000000000000080
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#define IA32E_PDPTE_PAT_BIT 0x0000000000001000
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#define IA32E_PDPTE_ADDR_MASK 0x0000FFFFC0000000
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#define IA32E_PDPTE_D_BIT 0x0000000000000040UL
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#define IA32E_PDPTE_PS_BIT 0x0000000000000080UL
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#define IA32E_PDPTE_PAT_BIT 0x0000000000001000UL
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#define IA32E_PDPTE_ADDR_MASK 0x0000FFFFC0000000UL
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#define IA32E_PDPTE_INDEX_MASK_START \
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(IA32E_PML4E_INDEX_MASK_START - IA32E_INDEX_MASK_BITS)
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/* Definitions exclusive to a Page Directory Entry (PDE) 1G or 2M */
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#define IA32E_PDE_D_BIT 0x0000000000000040
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#define IA32E_PDE_PS_BIT 0x0000000000000080
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#define IA32E_PDE_PAT_BIT 0x0000000000001000
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#define IA32E_PDE_ADDR_MASK 0x0000FFFFFFE00000
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#define IA32E_PDE_D_BIT 0x0000000000000040UL
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#define IA32E_PDE_PS_BIT 0x0000000000000080UL
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#define IA32E_PDE_PAT_BIT 0x0000000000001000UL
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#define IA32E_PDE_ADDR_MASK 0x0000FFFFFFE00000UL
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#define IA32E_PDE_INDEX_MASK_START \
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(IA32E_PDPTE_INDEX_MASK_START - IA32E_INDEX_MASK_BITS)
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/* Definitions exclusive to Page Table Entries (PTE) */
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#define IA32E_PTE_D_BIT 0x0000000000000040
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#define IA32E_PTE_PAT_BIT 0x0000000000000080
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#define IA32E_PTE_G_BIT 0x0000000000000100
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#define IA32E_PTE_ADDR_MASK 0x0000FFFFFFFFF000
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#define IA32E_PTE_D_BIT 0x0000000000000040UL
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#define IA32E_PTE_PAT_BIT 0x0000000000000080UL
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#define IA32E_PTE_G_BIT 0x0000000000000100UL
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#define IA32E_PTE_ADDR_MASK 0x0000FFFFFFFFF000UL
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#define IA32E_PTE_INDEX_MASK_START \
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(IA32E_PDE_INDEX_MASK_START - IA32E_INDEX_MASK_BITS)
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/** The 'Present' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_P 0x00000001
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#define MMU_32BIT_PDE_P 0x00000001U
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/** The 'Read/Write' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_RW 0x00000002
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#define MMU_32BIT_PDE_RW 0x00000002U
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/** The 'User/Supervisor' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_US 0x00000004
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#define MMU_32BIT_PDE_US 0x00000004U
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/** The 'Page Write Through' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_PWT 0x00000008
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#define MMU_32BIT_PDE_PWT 0x00000008U
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/** The 'Page Cache Disable' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_PCD 0x00000010
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#define MMU_32BIT_PDE_PCD 0x00000010U
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/** The 'Accessed' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_A 0x00000020
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#define MMU_32BIT_PDE_A 0x00000020U
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/** The 'Dirty' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_D 0x00000040
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#define MMU_32BIT_PDE_D 0x00000040U
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/** The 'Page Size' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_PS 0x00000080
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#define MMU_32BIT_PDE_PS 0x00000080U
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/** The 'Global' bit in a 32 bit paging page directory entry */
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#define MMU_32BIT_PDE_G 0x00000100
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#define MMU_32BIT_PDE_G 0x00000100U
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/** The 'PAT' bit in a page 32 bit paging directory entry */
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#define MMU_32BIT_PDE_PAT 0x00001000
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#define MMU_32BIT_PDE_PAT 0x00001000U
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/** The flag that indicates that the page fault was caused by a non present
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* page.
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*/
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#define PAGE_FAULT_P_FLAG 0x00000001
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#define PAGE_FAULT_P_FLAG 0x00000001U
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/** The flag that indicates that the page fault was caused by a write access. */
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#define PAGE_FAULT_WR_FLAG 0x00000002
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#define PAGE_FAULT_WR_FLAG 0x00000002U
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/** The flag that indicates that the page fault was caused in user mode. */
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#define PAGE_FAULT_US_FLAG 0x00000004
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#define PAGE_FAULT_US_FLAG 0x00000004U
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/** The flag that indicates that the page fault was caused by a reserved bit
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* violation.
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*/
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#define PAGE_FAULT_RSVD_FLAG 0x00000008
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#define PAGE_FAULT_RSVD_FLAG 0x00000008U
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/** The flag that indicates that the page fault was caused by an instruction
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* fetch.
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*/
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#define PAGE_FAULT_ID_FLAG 0x00000010
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#define PAGE_FAULT_ID_FLAG 0x00000010U
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/* Defines used for common memory sizes */
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#define MEM_1K 1024UL
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#define MEM_2K (MEM_1K * 2UL)
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#define MEM_4K (MEM_1K * 4UL)
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#define MEM_8K (MEM_1K * 8UL)
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#define MEM_16K (MEM_1K * 16UL)
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#define MEM_32K (MEM_1K * 32UL)
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#define MEM_64K (MEM_1K * 64UL)
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#define MEM_128K (MEM_1K * 128UL)
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#define MEM_256K (MEM_1K * 256UL)
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#define MEM_512K (MEM_1K * 512UL)
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#define MEM_1M (MEM_1K * 1024UL)
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#define MEM_2M (MEM_1M * 2UL)
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#define MEM_4M (MEM_1M * 4UL)
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#define MEM_8M (MEM_1M * 8UL)
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#define MEM_16M (MEM_1M * 16UL)
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#define MEM_32M (MEM_1M * 32UL)
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#define MEM_64M (MEM_1M * 64UL)
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#define MEM_128M (MEM_1M * 128UL)
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#define MEM_256M (MEM_1M * 256UL)
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#define MEM_512M (MEM_1M * 512UL)
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#define MEM_1G (MEM_1M * 1024UL)
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#define MEM_2G (MEM_1G * 2UL)
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#define MEM_3G (MEM_1G * 3UL)
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#define MEM_4G (MEM_1G * 4UL)
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#define MEM_5G (MEM_1G * 5UL)
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#define MEM_6G (MEM_1G * 6UL)
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#define MEM_1K 1024U
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#define MEM_2K (MEM_1K * 2U)
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#define MEM_4K (MEM_1K * 4U)
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#define MEM_8K (MEM_1K * 8U)
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#define MEM_16K (MEM_1K * 16U)
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#define MEM_32K (MEM_1K * 32U)
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#define MEM_64K (MEM_1K * 64U)
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#define MEM_128K (MEM_1K * 128U)
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#define MEM_256K (MEM_1K * 256U)
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#define MEM_512K (MEM_1K * 512U)
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#define MEM_1M (MEM_1K * 1024U)
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#define MEM_2M (MEM_1M * 2U)
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#define MEM_4M (MEM_1M * 4U)
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#define MEM_8M (MEM_1M * 8U)
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#define MEM_16M (MEM_1M * 16U)
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#define MEM_32M (MEM_1M * 32U)
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#define MEM_64M (MEM_1M * 64U)
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#define MEM_128M (MEM_1M * 128U)
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#define MEM_256M (MEM_1M * 256U)
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#define MEM_512M (MEM_1M * 512U)
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#define MEM_1G (MEM_1M * 1024U)
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#define MEM_2G (MEM_1G * 2U)
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#define MEM_3G (MEM_1G * 3U)
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#define MEM_4G (MEM_1G * 4U)
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#define MEM_5G (MEM_1G * 5U)
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#define MEM_6G (MEM_1G * 6U)
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#ifndef ASSEMBLER
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@ -184,15 +184,15 @@
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*/
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/* Generic memory attributes */
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#define MMU_MEM_ATTR_READ 0x00000001
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#define MMU_MEM_ATTR_WRITE 0x00000002
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#define MMU_MEM_ATTR_EXECUTE 0x00000004
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#define MMU_MEM_ATTR_USER 0x00000008
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#define MMU_MEM_ATTR_WB_CACHE 0x00000040
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#define MMU_MEM_ATTR_WT_CACHE 0x00000080
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#define MMU_MEM_ATTR_UNCACHED 0x00000100
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#define MMU_MEM_ATTR_WC 0x00000200
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#define MMU_MEM_ATTR_WP 0x00000400
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#define MMU_MEM_ATTR_READ 0x00000001U
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#define MMU_MEM_ATTR_WRITE 0x00000002U
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#define MMU_MEM_ATTR_EXECUTE 0x00000004U
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#define MMU_MEM_ATTR_USER 0x00000008U
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#define MMU_MEM_ATTR_WB_CACHE 0x00000040U
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#define MMU_MEM_ATTR_WT_CACHE 0x00000080U
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#define MMU_MEM_ATTR_UNCACHED 0x00000100U
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#define MMU_MEM_ATTR_WC 0x00000200U
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#define MMU_MEM_ATTR_WP 0x00000400U
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/* Definitions for memory types related to x64 */
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#define MMU_MEM_ATTR_BIT_READ_WRITE IA32E_COMM_RW_BIT
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@ -203,7 +203,7 @@
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* encoding. See also pat.h
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*/
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/* Selects PAT0 WB */
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#define MMU_MEM_ATTR_TYPE_CACHED_WB (0x0000000000000000)
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#define MMU_MEM_ATTR_TYPE_CACHED_WB (0x0000000000000000UL)
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/* Selects PAT1 WT */
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#define MMU_MEM_ATTR_TYPE_CACHED_WT (IA32E_COMM_PWT_BIT)
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/* Selects PAT2 UCM */
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