mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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HV: irq: convert hexadecimals used in bitops to unsigned
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao
lijinxia
@@ -268,161 +268,161 @@ struct ioapic {
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*/
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/* default physical locations of LOCAL (CPU) APICs */
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#define DEFAULT_APIC_BASE 0xfee00000
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#define DEFAULT_APIC_BASE 0xfee00000U
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/* constants relating to APIC ID registers */
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#define APIC_ID_MASK 0xff000000
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#define APIC_ID_MASK 0xff000000U
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#define APIC_ID_SHIFT 24
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#define APIC_ID_CLUSTER 0xf0
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#define APIC_ID_CLUSTER_ID 0x0f
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#define APIC_MAX_CLUSTER 0xe
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#define APIC_ID_CLUSTER 0xf0U
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#define APIC_ID_CLUSTER_ID 0x0fU
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#define APIC_MAX_CLUSTER 0xeU
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#define APIC_MAX_INTRACLUSTER_ID 3
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#define APIC_ID_CLUSTER_SHIFT 4
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/* fields in VER */
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#define APIC_VER_VERSION 0x000000ff
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#define APIC_VER_MAXLVT 0x00ff0000
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#define APIC_VER_VERSION 0x000000ffU
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#define APIC_VER_MAXLVT 0x00ff0000U
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#define MAXLVTSHIFT 16
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#define APIC_VER_EOI_SUPPRESSION 0x01000000
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#define APIC_VER_AMD_EXT_SPACE 0x80000000
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#define APIC_VER_EOI_SUPPRESSION 0x01000000U
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#define APIC_VER_AMD_EXT_SPACE 0x80000000U
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/* fields in LDR */
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#define APIC_LDR_RESERVED 0x00ffffff
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#define APIC_LDR_RESERVED 0x00ffffffU
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/* fields in DFR */
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#define APIC_DFR_RESERVED 0x0fffffff
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#define APIC_DFR_MODEL_MASK 0xf0000000
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#define APIC_DFR_MODEL_FLAT 0xf0000000
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#define APIC_DFR_MODEL_CLUSTER 0x00000000
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#define APIC_DFR_RESERVED 0x0fffffffU
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#define APIC_DFR_MODEL_MASK 0xf0000000U
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#define APIC_DFR_MODEL_FLAT 0xf0000000U
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#define APIC_DFR_MODEL_CLUSTER 0x00000000U
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/* fields in SVR */
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#define APIC_SVR_VECTOR 0x000000ff
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#define APIC_SVR_VEC_PROG 0x000000f0
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#define APIC_SVR_VEC_FIX 0x0000000f
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#define APIC_SVR_ENABLE 0x00000100
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#define APIC_SVR_SWDIS 0x00000000
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#define APIC_SVR_SWEN 0x00000100
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#define APIC_SVR_FOCUS 0x00000200
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#define APIC_SVR_FEN 0x00000000
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#define APIC_SVR_FDIS 0x00000200
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#define APIC_SVR_EOI_SUPPRESSION 0x00001000
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#define APIC_SVR_VECTOR 0x000000ffU
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#define APIC_SVR_VEC_PROG 0x000000f0U
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#define APIC_SVR_VEC_FIX 0x0000000fU
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#define APIC_SVR_ENABLE 0x00000100U
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#define APIC_SVR_SWDIS 0x00000000U
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#define APIC_SVR_SWEN 0x00000100U
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#define APIC_SVR_FOCUS 0x00000200U
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#define APIC_SVR_FEN 0x00000000U
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#define APIC_SVR_FDIS 0x00000200U
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#define APIC_SVR_EOI_SUPPRESSION 0x00001000U
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/* fields in TPR */
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#define APIC_TPR_PRIO 0x000000ff
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#define APIC_TPR_INT 0x000000f0
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#define APIC_TPR_SUB 0x0000000f
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#define APIC_TPR_PRIO 0x000000ffU
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#define APIC_TPR_INT 0x000000f0U
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#define APIC_TPR_SUB 0x0000000fU
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/* fields in ESR */
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#define APIC_ESR_SEND_CS_ERROR 0x00000001
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#define APIC_ESR_RECEIVE_CS_ERROR 0x00000002
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#define APIC_ESR_SEND_ACCEPT 0x00000004
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#define APIC_ESR_RECEIVE_ACCEPT 0x00000008
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#define APIC_ESR_SEND_ILLEGAL_VECTOR 0x00000020
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#define APIC_ESR_RECEIVE_ILLEGAL_VECTOR 0x00000040
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#define APIC_ESR_ILLEGAL_REGISTER 0x00000080
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#define APIC_ESR_SEND_CS_ERROR 0x00000001U
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#define APIC_ESR_RECEIVE_CS_ERROR 0x00000002U
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#define APIC_ESR_SEND_ACCEPT 0x00000004U
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#define APIC_ESR_RECEIVE_ACCEPT 0x00000008U
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#define APIC_ESR_SEND_ILLEGAL_VECTOR 0x00000020U
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#define APIC_ESR_RECEIVE_ILLEGAL_VECTOR 0x00000040U
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#define APIC_ESR_ILLEGAL_REGISTER 0x00000080U
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/* fields in ICR_LOW */
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#define APIC_VECTOR_MASK 0x000000ff
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#define APIC_VECTOR_MASK 0x000000ffU
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#define APIC_DELMODE_MASK 0x00000700
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#define APIC_DELMODE_FIXED 0x00000000
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#define APIC_DELMODE_LOWPRIO 0x00000100
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#define APIC_DELMODE_SMI 0x00000200
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#define APIC_DELMODE_RR 0x00000300
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#define APIC_DELMODE_NMI 0x00000400
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#define APIC_DELMODE_INIT 0x00000500
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#define APIC_DELMODE_STARTUP 0x00000600
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#define APIC_DELMODE_RESV 0x00000700
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#define APIC_DELMODE_MASK 0x00000700U
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#define APIC_DELMODE_FIXED 0x00000000U
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#define APIC_DELMODE_LOWPRIO 0x00000100U
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#define APIC_DELMODE_SMI 0x00000200U
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#define APIC_DELMODE_RR 0x00000300U
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#define APIC_DELMODE_NMI 0x00000400U
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#define APIC_DELMODE_INIT 0x00000500U
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#define APIC_DELMODE_STARTUP 0x00000600U
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#define APIC_DELMODE_RESV 0x00000700U
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#define APIC_DESTMODE_MASK 0x00000800
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#define APIC_DESTMODE_PHY 0x00000000
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#define APIC_DESTMODE_LOG 0x00000800
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#define APIC_DESTMODE_MASK 0x00000800U
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#define APIC_DESTMODE_PHY 0x00000000U
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#define APIC_DESTMODE_LOG 0x00000800U
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#define APIC_DELSTAT_MASK 0x00001000
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#define APIC_DELSTAT_IDLE 0x00000000
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#define APIC_DELSTAT_PEND 0x00001000
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#define APIC_DELSTAT_MASK 0x00001000U
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#define APIC_DELSTAT_IDLE 0x00000000U
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#define APIC_DELSTAT_PEND 0x00001000U
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#define APIC_RESV1_MASK 0x00002000
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#define APIC_RESV1_MASK 0x00002000U
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#define APIC_LEVEL_MASK 0x00004000
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#define APIC_LEVEL_DEASSERT 0x00000000
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#define APIC_LEVEL_ASSERT 0x00004000
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#define APIC_LEVEL_MASK 0x00004000U
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#define APIC_LEVEL_DEASSERT 0x00000000U
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#define APIC_LEVEL_ASSERT 0x00004000U
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#define APIC_TRIGMOD_MASK 0x00008000
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#define APIC_TRIGMOD_EDGE 0x00000000
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#define APIC_TRIGMOD_LEVEL 0x00008000
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#define APIC_TRIGMOD_MASK 0x00008000U
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#define APIC_TRIGMOD_EDGE 0x00000000U
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#define APIC_TRIGMOD_LEVEL 0x00008000U
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#define APIC_RRSTAT_MASK 0x00030000
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#define APIC_RRSTAT_INVALID 0x00000000
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#define APIC_RRSTAT_INPROG 0x00010000
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#define APIC_RRSTAT_VALID 0x00020000
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#define APIC_RRSTAT_RESV 0x00030000
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#define APIC_RRSTAT_MASK 0x00030000U
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#define APIC_RRSTAT_INVALID 0x00000000U
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#define APIC_RRSTAT_INPROG 0x00010000U
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#define APIC_RRSTAT_VALID 0x00020000U
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#define APIC_RRSTAT_RESV 0x00030000U
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#define APIC_DEST_MASK 0x000c0000
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#define APIC_DEST_DESTFLD 0x00000000
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#define APIC_DEST_SELF 0x00040000
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#define APIC_DEST_ALLISELF 0x00080000
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#define APIC_DEST_ALLESELF 0x000c0000
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#define APIC_DEST_MASK 0x000c0000U
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#define APIC_DEST_DESTFLD 0x00000000U
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#define APIC_DEST_SELF 0x00040000U
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#define APIC_DEST_ALLISELF 0x00080000U
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#define APIC_DEST_ALLESELF 0x000c0000U
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#define APIC_RESV2_MASK 0xfff00000
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#define APIC_RESV2_MASK 0xfff00000U
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#define APIC_ICRLO_RESV_MASK (APIC_RESV1_MASK | APIC_RESV2_MASK)
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/* fields in LVT1/2 */
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#define APIC_LVT_VECTOR 0x000000ff
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#define APIC_LVT_DM 0x00000700
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#define APIC_LVT_DM_FIXED 0x00000000
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#define APIC_LVT_DM_SMI 0x00000200
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#define APIC_LVT_DM_NMI 0x00000400
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#define APIC_LVT_DM_INIT 0x00000500
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#define APIC_LVT_DM_EXTINT 0x00000700
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#define APIC_LVT_DS 0x00001000
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#define APIC_LVT_IIPP 0x00002000
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#define APIC_LVT_IIPP_INTALO 0x00002000
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#define APIC_LVT_IIPP_INTAHI 0x00000000
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#define APIC_LVT_RIRR 0x00004000
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#define APIC_LVT_TM 0x00008000
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#define APIC_LVT_M 0x00010000
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#define APIC_LVT_VECTOR 0x000000ffU
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#define APIC_LVT_DM 0x00000700U
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#define APIC_LVT_DM_FIXED 0x00000000U
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#define APIC_LVT_DM_SMI 0x00000200U
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#define APIC_LVT_DM_NMI 0x00000400U
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#define APIC_LVT_DM_INIT 0x00000500U
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#define APIC_LVT_DM_EXTINT 0x00000700U
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#define APIC_LVT_DS 0x00001000U
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#define APIC_LVT_IIPP 0x00002000U
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#define APIC_LVT_IIPP_INTALO 0x00002000U
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#define APIC_LVT_IIPP_INTAHI 0x00000000U
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#define APIC_LVT_RIRR 0x00004000U
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#define APIC_LVT_TM 0x00008000U
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#define APIC_LVT_M 0x00010000U
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/* fields in LVT Timer */
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#define APIC_LVTT_VECTOR 0x000000ff
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#define APIC_LVTT_DS 0x00001000
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#define APIC_LVTT_M 0x00010000
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#define APIC_LVTT_TM 0x00060000
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#define APIC_LVTT_TM_ONE_SHOT 0x00000000
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#define APIC_LVTT_TM_PERIODIC 0x00020000
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#define APIC_LVTT_TM_TSCDLT 0x00040000
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#define APIC_LVTT_TM_RSRV 0x00060000
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#define APIC_LVTT_VECTOR 0x000000ffU
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#define APIC_LVTT_DS 0x00001000U
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#define APIC_LVTT_M 0x00010000U
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#define APIC_LVTT_TM 0x00060000U
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#define APIC_LVTT_TM_ONE_SHOT 0x00000000U
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#define APIC_LVTT_TM_PERIODIC 0x00020000U
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#define APIC_LVTT_TM_TSCDLT 0x00040000U
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#define APIC_LVTT_TM_RSRV 0x00060000U
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/* APIC timer current count */
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#define APIC_TIMER_MAX_COUNT 0xffffffff
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#define APIC_TIMER_MAX_COUNT 0xffffffffU
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/* fields in TDCR */
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#define APIC_TDCR_2 0x00
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#define APIC_TDCR_4 0x01
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#define APIC_TDCR_8 0x02
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#define APIC_TDCR_16 0x03
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#define APIC_TDCR_32 0x08
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#define APIC_TDCR_64 0x09
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#define APIC_TDCR_128 0x0a
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#define APIC_TDCR_1 0x0b
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#define APIC_TDCR_2 0x00U
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#define APIC_TDCR_4 0x01U
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#define APIC_TDCR_8 0x02U
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#define APIC_TDCR_16 0x03U
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#define APIC_TDCR_32 0x08U
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#define APIC_TDCR_64 0x09U
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#define APIC_TDCR_128 0x0aU
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#define APIC_TDCR_1 0x0bU
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/* Constants related to AMD Extended APIC Features Register */
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#define APIC_EXTF_ELVT_MASK 0x00ff0000
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#define APIC_EXTF_ELVT_MASK 0x00ff0000U
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#define APIC_EXTF_ELVT_SHIFT 16
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#define APIC_EXTF_EXTID_CAP 0x00000004
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#define APIC_EXTF_SEIO_CAP 0x00000002
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#define APIC_EXTF_IER_CAP 0x00000001
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#define APIC_EXTF_EXTID_CAP 0x00000004U
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#define APIC_EXTF_SEIO_CAP 0x00000002U
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#define APIC_EXTF_IER_CAP 0x00000001U
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/* LVT table indices */
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#define APIC_LVT_TIMER 0
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#define APIC_LVT_THERMAL 1
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#define APIC_LVT_PMC 2
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#define APIC_LVT_LINT0 3
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#define APIC_LVT_LINT1 4
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#define APIC_LVT_ERROR 5
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#define APIC_LVT_CMCI 6
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#define APIC_LVT_TIMER 0U
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#define APIC_LVT_THERMAL 1U
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#define APIC_LVT_PMC 2U
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#define APIC_LVT_LINT0 3U
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#define APIC_LVT_LINT1 4U
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#define APIC_LVT_ERROR 5U
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#define APIC_LVT_CMCI 6U
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#define APIC_LVT_MAX APIC_LVT_CMCI
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/* AMD extended LVT constants, seem to be assigned by fiat */
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@@ -437,83 +437,83 @@ struct ioapic {
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*/
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/* default physical locations of an IO APIC */
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#define DEFAULT_IO_APIC_BASE 0xfec00000
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#define DEFAULT_IO_APIC_BASE 0xfec00000U
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/* window register offset */
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#define IOAPIC_WINDOW 0x10
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#define IOAPIC_EOIR 0x40
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#define IOAPIC_WINDOW 0x10U
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#define IOAPIC_EOIR 0x40U
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/* indexes into IO APIC */
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#define IOAPIC_ID 0x00
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#define IOAPIC_VER 0x01
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#define IOAPIC_ARB 0x02
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#define IOAPIC_REDTBL 0x10
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#define IOAPIC_ID 0x00U
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#define IOAPIC_VER 0x01U
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#define IOAPIC_ARB 0x02U
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#define IOAPIC_REDTBL 0x10U
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#define IOAPIC_REDTBL0 IOAPIC_REDTBL
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#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02)
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#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04)
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#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06)
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#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08)
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#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a)
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#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c)
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#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e)
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#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10)
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#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12)
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#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14)
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#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16)
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#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18)
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#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a)
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#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c)
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#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e)
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#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20)
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#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22)
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#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24)
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#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26)
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#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28)
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#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a)
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#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c)
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#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e)
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#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02U)
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#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04U)
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#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06U)
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#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08U)
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#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0aU)
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#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0cU)
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#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0eU)
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#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10U)
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#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12U)
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#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14U)
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#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16U)
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#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18U)
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#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1aU)
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#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1cU)
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#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1eU)
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#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20U)
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#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22U)
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#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24U)
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#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26U)
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#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28U)
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#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2aU)
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#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2cU)
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#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2eU)
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/* fields in VER, for redirection entry */
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#define IOAPIC_MAX_RTE_MASK 0x00ff0000
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#define MAX_RTE_SHIFT 16
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#define IOAPIC_MAX_RTE_MASK 0x00ff0000U
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#define MAX_RTE_SHIFT 16U
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/*
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* fields in the IO APIC's redirection table entries
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*/
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#define IOAPIC_RTE_DEST APIC_ID_MASK /* broadcast addr: all APICs */
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#define IOAPIC_RTE_RESV 0x00fe0000 /* reserved */
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||||
#define IOAPIC_RTE_RESV 0x00fe0000UL /* reserved */
|
||||
|
||||
#define IOAPIC_RTE_INTMASK 0x00010000 /* R/W: INTerrupt mask */
|
||||
#define IOAPIC_RTE_INTMCLR 0x00000000 /* clear, allow INTs */
|
||||
#define IOAPIC_RTE_INTMSET 0x00010000 /* set, inhibit INTs */
|
||||
#define IOAPIC_RTE_INTMASK 0x00010000UL /* R/W: INTerrupt mask */
|
||||
#define IOAPIC_RTE_INTMCLR 0x00000000UL /* clear, allow INTs */
|
||||
#define IOAPIC_RTE_INTMSET 0x00010000UL /* set, inhibit INTs */
|
||||
|
||||
#define IOAPIC_RTE_TRGRMOD 0x00008000 /* R/W: trigger mode */
|
||||
#define IOAPIC_RTE_TRGREDG 0x00000000 /* edge */
|
||||
#define IOAPIC_RTE_TRGRLVL 0x00008000 /* level */
|
||||
#define IOAPIC_RTE_TRGRMOD 0x00008000UL /* R/W: trigger mode */
|
||||
#define IOAPIC_RTE_TRGREDG 0x00000000UL /* edge */
|
||||
#define IOAPIC_RTE_TRGRLVL 0x00008000UL /* level */
|
||||
|
||||
#define IOAPIC_RTE_REM_IRR 0x00004000 /* RO: remote IRR */
|
||||
#define IOAPIC_RTE_REM_IRR 0x00004000UL /* RO: remote IRR */
|
||||
|
||||
#define IOAPIC_RTE_INTPOL 0x00002000 /*R/W:INT input pin polarity*/
|
||||
#define IOAPIC_RTE_INTAHI 0x00000000 /* active high */
|
||||
#define IOAPIC_RTE_INTALO 0x00002000 /* active low */
|
||||
#define IOAPIC_RTE_INTPOL 0x00002000UL /*R/W:INT input pin polarity*/
|
||||
#define IOAPIC_RTE_INTAHI 0x00000000UL /* active high */
|
||||
#define IOAPIC_RTE_INTALO 0x00002000UL /* active low */
|
||||
|
||||
#define IOAPIC_RTE_DELIVS 0x00001000 /* RO: delivery status */
|
||||
#define IOAPIC_RTE_DELIVS 0x00001000UL /* RO: delivery status */
|
||||
|
||||
#define IOAPIC_RTE_DESTMOD 0x00000800 /*R/W:destination mode*/
|
||||
#define IOAPIC_RTE_DESTPHY 0x00000000 /* physical */
|
||||
#define IOAPIC_RTE_DESTLOG 0x00000800 /* logical */
|
||||
#define IOAPIC_RTE_DESTMOD 0x00000800UL /*R/W:destination mode*/
|
||||
#define IOAPIC_RTE_DESTPHY 0x00000000UL /* physical */
|
||||
#define IOAPIC_RTE_DESTLOG 0x00000800UL /* logical */
|
||||
|
||||
#define IOAPIC_RTE_DELMOD 0x00000700 /* R/W: delivery mode */
|
||||
#define IOAPIC_RTE_DELFIXED 0x00000000 /* fixed */
|
||||
#define IOAPIC_RTE_DELLOPRI 0x00000100 /* lowest priority */
|
||||
#define IOAPIC_RTE_DELSMI 0x00000200 /*System Management INT*/
|
||||
#define IOAPIC_RTE_DELRSV1 0x00000300 /* reserved */
|
||||
#define IOAPIC_RTE_DELNMI 0x00000400 /* NMI signal */
|
||||
#define IOAPIC_RTE_DELINIT 0x00000500 /* INIT signal */
|
||||
#define IOAPIC_RTE_DELRSV2 0x00000600 /* reserved */
|
||||
#define IOAPIC_RTE_DELEXINT 0x00000700 /* External INTerrupt */
|
||||
#define IOAPIC_RTE_DELMOD 0x00000700UL /* R/W: delivery mode */
|
||||
#define IOAPIC_RTE_DELFIXED 0x00000000UL /* fixed */
|
||||
#define IOAPIC_RTE_DELLOPRI 0x00000100UL /* lowest priority */
|
||||
#define IOAPIC_RTE_DELSMI 0x00000200UL /*System Management INT*/
|
||||
#define IOAPIC_RTE_DELRSV1 0x00000300UL /* reserved */
|
||||
#define IOAPIC_RTE_DELNMI 0x00000400UL /* NMI signal */
|
||||
#define IOAPIC_RTE_DELINIT 0x00000500UL /* INIT signal */
|
||||
#define IOAPIC_RTE_DELRSV2 0x00000600UL /* reserved */
|
||||
#define IOAPIC_RTE_DELEXINT 0x00000700UL /* External INTerrupt */
|
||||
|
||||
#define IOAPIC_RTE_INTVEC 0x000000ff /*R/W: INT vector field*/
|
||||
#define IOAPIC_RTE_INTVEC 0x000000ffUL /*R/W: INT vector field*/
|
||||
|
||||
#endif /* _APICREG_H_ */
|
||||
|
||||
Reference in New Issue
Block a user