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HV: irq: convert hexadecimals used in bitops to unsigned

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Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao
2018-06-19 18:31:41 +08:00
committed by lijinxia
parent f4bd0798e0
commit 41a1035f9b
9 changed files with 372 additions and 370 deletions
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116
hypervisor/include/arch/x86/lapic.h
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@@ -41,75 +41,75 @@ enum intr_lapic_icr_shorthand {
};
/* Default LAPIC base */
#define LAPIC_BASE 0xFEE00000
#define LAPIC_BASE 0xFEE00000U
/* LAPIC register offset for memory mapped IO access */
#define LAPIC_ID_REGISTER 0x00000020
#define LAPIC_VERSION_REGISTER 0x00000030
#define LAPIC_TASK_PRIORITY_REGISTER 0x00000080
#define LAPIC_ARBITRATION_PRIORITY_REGISTER 0x00000090
#define LAPIC_PROCESSOR_PRIORITY_REGISTER 0x000000A0
#define LAPIC_EOI_REGISTER 0x000000B0
#define LAPIC_REMOTE_READ_REGISTER 0x000000C0
#define LAPIC_LOGICAL_DESTINATION_REGISTER 0x000000D0
#define LAPIC_DESTINATION_FORMAT_REGISTER 0x000000E0
#define LAPIC_SPURIOUS_VECTOR_REGISTER 0x000000F0
#define LAPIC_IN_SERVICE_REGISTER_0 0x00000100
#define LAPIC_IN_SERVICE_REGISTER_1 0x00000110
#define LAPIC_IN_SERVICE_REGISTER_2 0x00000120
#define LAPIC_IN_SERVICE_REGISTER_3 0x00000130
#define LAPIC_IN_SERVICE_REGISTER_4 0x00000140
#define LAPIC_IN_SERVICE_REGISTER_5 0x00000150
#define LAPIC_IN_SERVICE_REGISTER_6 0x00000160
#define LAPIC_IN_SERVICE_REGISTER_7 0x00000170
#define LAPIC_TRIGGER_MODE_REGISTER_0 0x00000180
#define LAPIC_TRIGGER_MODE_REGISTER_1 0x00000190
#define LAPIC_TRIGGER_MODE_REGISTER_2 0x000001A0
#define LAPIC_TRIGGER_MODE_REGISTER_3 0x000001B0
#define LAPIC_TRIGGER_MODE_REGISTER_4 0x000001C0
#define LAPIC_TRIGGER_MODE_REGISTER_5 0x000001D0
#define LAPIC_TRIGGER_MODE_REGISTER_6 0x000001E0
#define LAPIC_TRIGGER_MODE_REGISTER_7 0x000001F0
#define LAPIC_INT_REQUEST_REGISTER_0 0x00000200
#define LAPIC_INT_REQUEST_REGISTER_1 0x00000210
#define LAPIC_INT_REQUEST_REGISTER_2 0x00000220
#define LAPIC_INT_REQUEST_REGISTER_3 0x00000230
#define LAPIC_INT_REQUEST_REGISTER_4 0x00000240
#define LAPIC_INT_REQUEST_REGISTER_5 0x00000250
#define LAPIC_INT_REQUEST_REGISTER_6 0x00000260
#define LAPIC_INT_REQUEST_REGISTER_7 0x00000270
#define LAPIC_ERROR_STATUS_REGISTER 0x00000280
#define LAPIC_LVT_CMCI_REGISTER 0x000002F0
#define LAPIC_INT_COMMAND_REGISTER_0 0x00000300
#define LAPIC_INT_COMMAND_REGISTER_1 0x00000310
#define LAPIC_LVT_TIMER_REGISTER 0x00000320
#define LAPIC_LVT_THERMAL_SENSOR_REGISTER 0x00000330
#define LAPIC_LVT_PMC_REGISTER 0x00000340
#define LAPIC_LVT_LINT0_REGISTER 0x00000350
#define LAPIC_LVT_LINT1_REGISTER 0x00000360
#define LAPIC_LVT_ERROR_REGISTER 0x00000370
#define LAPIC_INITIAL_COUNT_REGISTER 0x00000380
#define LAPIC_CURRENT_COUNT_REGISTER 0x00000390
#define LAPIC_DIVIDE_CONFIGURATION_REGISTER 0x000003E0
#define LAPIC_ID_REGISTER 0x00000020U
#define LAPIC_VERSION_REGISTER 0x00000030U
#define LAPIC_TASK_PRIORITY_REGISTER 0x00000080U
#define LAPIC_ARBITRATION_PRIORITY_REGISTER 0x00000090U
#define LAPIC_PROCESSOR_PRIORITY_REGISTER 0x000000A0U
#define LAPIC_EOI_REGISTER 0x000000B0U
#define LAPIC_REMOTE_READ_REGISTER 0x000000C0U
#define LAPIC_LOGICAL_DESTINATION_REGISTER 0x000000D0U
#define LAPIC_DESTINATION_FORMAT_REGISTER 0x000000E0U
#define LAPIC_SPURIOUS_VECTOR_REGISTER 0x000000F0U
#define LAPIC_IN_SERVICE_REGISTER_0 0x00000100U
#define LAPIC_IN_SERVICE_REGISTER_1 0x00000110U
#define LAPIC_IN_SERVICE_REGISTER_2 0x00000120U
#define LAPIC_IN_SERVICE_REGISTER_3 0x00000130U
#define LAPIC_IN_SERVICE_REGISTER_4 0x00000140U
#define LAPIC_IN_SERVICE_REGISTER_5 0x00000150U
#define LAPIC_IN_SERVICE_REGISTER_6 0x00000160U
#define LAPIC_IN_SERVICE_REGISTER_7 0x00000170U
#define LAPIC_TRIGGER_MODE_REGISTER_0 0x00000180U
#define LAPIC_TRIGGER_MODE_REGISTER_1 0x00000190U
#define LAPIC_TRIGGER_MODE_REGISTER_2 0x000001A0U
#define LAPIC_TRIGGER_MODE_REGISTER_3 0x000001B0U
#define LAPIC_TRIGGER_MODE_REGISTER_4 0x000001C0U
#define LAPIC_TRIGGER_MODE_REGISTER_5 0x000001D0U
#define LAPIC_TRIGGER_MODE_REGISTER_6 0x000001E0U
#define LAPIC_TRIGGER_MODE_REGISTER_7 0x000001F0U
#define LAPIC_INT_REQUEST_REGISTER_0 0x00000200U
#define LAPIC_INT_REQUEST_REGISTER_1 0x00000210U
#define LAPIC_INT_REQUEST_REGISTER_2 0x00000220U
#define LAPIC_INT_REQUEST_REGISTER_3 0x00000230U
#define LAPIC_INT_REQUEST_REGISTER_4 0x00000240U
#define LAPIC_INT_REQUEST_REGISTER_5 0x00000250U
#define LAPIC_INT_REQUEST_REGISTER_6 0x00000260U
#define LAPIC_INT_REQUEST_REGISTER_7 0x00000270U
#define LAPIC_ERROR_STATUS_REGISTER 0x00000280U
#define LAPIC_LVT_CMCI_REGISTER 0x000002F0U
#define LAPIC_INT_COMMAND_REGISTER_0 0x00000300U
#define LAPIC_INT_COMMAND_REGISTER_1 0x00000310U
#define LAPIC_LVT_TIMER_REGISTER 0x00000320U
#define LAPIC_LVT_THERMAL_SENSOR_REGISTER 0x00000330U
#define LAPIC_LVT_PMC_REGISTER 0x00000340U
#define LAPIC_LVT_LINT0_REGISTER 0x00000350U
#define LAPIC_LVT_LINT1_REGISTER 0x00000360U
#define LAPIC_LVT_ERROR_REGISTER 0x00000370U
#define LAPIC_INITIAL_COUNT_REGISTER 0x00000380U
#define LAPIC_CURRENT_COUNT_REGISTER 0x00000390U
#define LAPIC_DIVIDE_CONFIGURATION_REGISTER 0x000003E0U
/* LAPIC CPUID bit and bitmask definitions */
#define CPUID_OUT_RDX_APIC_PRESENT ((uint64_t) 1 << 9)
#define CPUID_OUT_RCX_X2APIC_PRESENT ((uint64_t) 1 << 21)
#define CPUID_OUT_RDX_APIC_PRESENT ((uint64_t) 1UL << 9)
#define CPUID_OUT_RCX_X2APIC_PRESENT ((uint64_t) 1UL << 21)
/* LAPIC MSR bit and bitmask definitions */
#define MSR_01B_XAPIC_GLOBAL_ENABLE ((uint64_t) 1 << 11)
#define MSR_01B_XAPIC_GLOBAL_ENABLE ((uint64_t) 1UL << 11)
/* LAPIC register bit and bitmask definitions */
#define LAPIC_SVR_VECTOR 0x000000FF
#define LAPIC_SVR_APIC_ENABLE_MASK 0x00000100
#define LAPIC_SVR_VECTOR 0x000000FFU
#define LAPIC_SVR_APIC_ENABLE_MASK 0x00000100U
#define LAPIC_LVT_MASK 0x00010000
#define LAPIC_DELIVERY_MODE_EXTINT_MASK 0x00000700
#define LAPIC_LVT_MASK 0x00010000U
#define LAPIC_DELIVERY_MODE_EXTINT_MASK 0x00000700U
/* LAPIC Timer bit and bitmask definitions */
#define LAPIC_TMR_ONESHOT ((uint32_t) 0x0 << 17)
#define LAPIC_TMR_PERIODIC ((uint32_t) 0x1 << 17)
#define LAPIC_TMR_TSC_DEADLINE ((uint32_t) 0x2 << 17)
#define LAPIC_TMR_ONESHOT ((uint32_t) 0x0U << 17)
#define LAPIC_TMR_PERIODIC ((uint32_t) 0x1U << 17)
#define LAPIC_TMR_TSC_DEADLINE ((uint32_t) 0x2U << 17)
enum intr_cpu_startup_shorthand {
INTR_CPU_STARTUP_USE_DEST,