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HV: irq: convert hexadecimals used in bitops to unsigned

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Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao 2018-06-19 18:31:41 +08:00 committed by lijinxia
parent f4bd0798e0
commit 41a1035f9b
9 changed files with 372 additions and 370 deletions
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14
hypervisor/arch/x86/guest/vioapic.c
View File

@ -223,15 +223,16 @@ vioapic_update_tmr(struct vcpu *vcpu)
static uint32_t static uint32_t
vioapic_read(struct vioapic *vioapic, uint32_t addr) vioapic_read(struct vioapic *vioapic, uint32_t addr)
{ {
int regnum, pin, rshift; uint32_t regnum;
int pin, rshift;
regnum = addr & 0xff; regnum = addr & 0xffU;
switch (regnum) { switch (regnum) {
case IOAPIC_ID: case IOAPIC_ID:
return vioapic->id; return vioapic->id;
case IOAPIC_VER: case IOAPIC_VER:
return ((vioapic_pincount(vioapic->vm) - 1) << MAX_RTE_SHIFT) return ((vioapic_pincount(vioapic->vm) - 1U) << MAX_RTE_SHIFT)
| 0x11; | 0x11U;
case IOAPIC_ARB: case IOAPIC_ARB:
return vioapic->id; return vioapic->id;
default: default:
@ -290,9 +291,10 @@ vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
{ {
uint64_t data64, mask64; uint64_t data64, mask64;
uint64_t last, new, changed; uint64_t last, new, changed;
int regnum, pin, lshift; uint32_t regnum;
int pin, lshift;
regnum = addr & 0xff; regnum = addr & 0xffUL;
switch (regnum) { switch (regnum) {
case IOAPIC_ID: case IOAPIC_ID:
vioapic->id = data & APIC_ID_MASK; vioapic->id = data & APIC_ID_MASK;

54
hypervisor/arch/x86/guest/vlapic.c
View File

@ -41,10 +41,10 @@
#define VLAPIC_VERSION (16) #define VLAPIC_VERSION (16)
#define APICBASE_RESERVED 0x000002ff #define APICBASE_RESERVED 0x000002ffU
#define APICBASE_BSP 0x00000100 #define APICBASE_BSP 0x00000100U
#define APICBASE_X2APIC 0x00000400 #define APICBASE_X2APIC 0x00000400U
#define APICBASE_ENABLED 0x00000800 #define APICBASE_ENABLED 0x00000800U
#define ACRN_DBG_LAPIC 6 #define ACRN_DBG_LAPIC 6
@ -740,7 +740,7 @@ vlapic_update_ppr(struct vlapic *vlapic)
isrptr = &vlapic->apic_page->isr[0]; isrptr = &vlapic->apic_page->isr[0];
for (vector = 0; vector < 256; vector++) { for (vector = 0; vector < 256; vector++) {
idx = vector / 32; idx = vector / 32;
if ((isrptr[idx].val & (1 << (vector % 32))) != 0U) { if ((isrptr[idx].val & (1U << (vector % 32))) != 0U) {
if ((i > vlapic->isrvec_stk_top) || if ((i > vlapic->isrvec_stk_top) ||
((i < ISRVEC_STK_SIZE) && ((i < ISRVEC_STK_SIZE) &&
(vlapic->isrvec_stk[i] != vector))) { (vlapic->isrvec_stk[i] != vector))) {
@ -755,7 +755,7 @@ vlapic_update_ppr(struct vlapic *vlapic)
if (PRIO(tpr) >= PRIO(isrvec)) if (PRIO(tpr) >= PRIO(isrvec))
ppr = tpr; ppr = tpr;
else else
ppr = isrvec & 0xf0; ppr = isrvec & 0xf0U;
vlapic->apic_page->ppr = ppr; vlapic->apic_page->ppr = ppr;
dev_dbg(ACRN_DBG_LAPIC, "%s 0x%02x", __func__, ppr); dev_dbg(ACRN_DBG_LAPIC, "%s 0x%02x", __func__, ppr);
@ -901,14 +901,14 @@ vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
* In the "Flat Model" the MDA is interpreted as an 8-bit wide * In the "Flat Model" the MDA is interpreted as an 8-bit wide
* bitmask. This model is only available in the xAPIC mode. * bitmask. This model is only available in the xAPIC mode.
*/ */
mda_flat_ldest = dest & 0xff; mda_flat_ldest = dest & 0xffU;
/* /*
* In the "Cluster Model" the MDA is used to identify a * In the "Cluster Model" the MDA is used to identify a
* specific cluster and a set of APICs in that cluster. * specific cluster and a set of APICs in that cluster.
*/ */
mda_cluster_id = (dest >> 4) & 0xf; mda_cluster_id = (dest >> 4) & 0xfU;
mda_cluster_ldest = dest & 0xf; mda_cluster_ldest = dest & 0xfU;
/* /*
* Logical mode: match each APIC that has a bit set * Logical mode: match each APIC that has a bit set
@ -931,7 +931,7 @@ vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
APIC_DFR_MODEL_CLUSTER) { APIC_DFR_MODEL_CLUSTER) {
cluster = ldr >> 28; cluster = ldr >> 28;
ldest = (ldr >> 24) & 0xf; ldest = (ldr >> 24) & 0xfU;
if (cluster != mda_cluster_id) if (cluster != mda_cluster_id)
continue; continue;
@ -998,7 +998,7 @@ vlapic_set_cr8(struct vlapic *vlapic, uint64_t val)
{ {
uint8_t tpr; uint8_t tpr;
if ((val & ~0xf) != 0U) { if ((val & ~0xfUL) != 0U) {
vcpu_inject_gp(vlapic->vcpu, 0); vcpu_inject_gp(vlapic->vcpu, 0);
return; return;
} }
@ -1202,7 +1202,7 @@ vlapic_intr_accepted(struct vlapic *vlapic, uint32_t vector)
VLAPIC_CTR_IRR(vlapic, "vlapic_intr_accepted"); VLAPIC_CTR_IRR(vlapic, "vlapic_intr_accepted");
isrptr = &lapic->isr[0]; isrptr = &lapic->isr[0];
isrptr[idx].val |= 1 << (vector % 32); isrptr[idx].val |= 1U << (vector % 32);
VLAPIC_CTR_ISR(vlapic, "vlapic_intr_accepted"); VLAPIC_CTR_ISR(vlapic, "vlapic_intr_accepted");
/* /*
@ -1283,7 +1283,7 @@ vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
goto done; goto done;
} }
offset &= ~3; offset &= ~0x3UL;
switch (offset) { switch (offset) {
case APIC_OFFSET_ID: case APIC_OFFSET_ID:
*data = lapic->id; *data = lapic->id;
@ -1407,7 +1407,7 @@ vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
uint32_t *regptr; uint32_t *regptr;
int retval; int retval;
ASSERT((offset & 0xf) == 0 && offset < CPU_PAGE_SIZE, ASSERT((offset & 0xfUL) == 0 && offset < CPU_PAGE_SIZE,
"%s: invalid offset %#lx", __func__, offset); "%s: invalid offset %#lx", __func__, offset);
dev_dbg(ACRN_DBG_LAPIC, "vlapic write offset %#lx, data %#lx", dev_dbg(ACRN_DBG_LAPIC, "vlapic write offset %#lx, data %#lx",
@ -1433,7 +1433,7 @@ vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
vlapic_id_write_handler(vlapic); vlapic_id_write_handler(vlapic);
break; break;
case APIC_OFFSET_TPR: case APIC_OFFSET_TPR:
vlapic_set_tpr(vlapic, data & 0xff); vlapic_set_tpr(vlapic, data & 0xffUL);
break; break;
case APIC_OFFSET_EOI: case APIC_OFFSET_EOI:
vlapic_process_eoi(vlapic); vlapic_process_eoi(vlapic);
@ -1745,7 +1745,7 @@ vlapic_set_intr(struct vcpu *vcpu, uint32_t vector, bool level)
* According to section "Maskable Hardware Interrupts" in Intel SDM * According to section "Maskable Hardware Interrupts" in Intel SDM
* vectors 16 through 255 can be delivered through the local APIC. * vectors 16 through 255 can be delivered through the local APIC.
*/ */
if (vector < 16 || vector > 255) if (vector < 16U || vector > 255U)
return -EINVAL; return -EINVAL;
vlapic = vcpu->arch_vcpu.vlapic; vlapic = vcpu->arch_vcpu.vlapic;
@ -1808,11 +1808,11 @@ vlapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg)
* the Redirection Hint and Destination Mode are '1' and * the Redirection Hint and Destination Mode are '1' and
* physical otherwise. * physical otherwise.
*/ */
dest = (addr >> 12) & 0xff; dest = (addr >> 12) & 0xffU;
phys = ((addr & (MSI_ADDR_RH | MSI_ADDR_LOG)) != phys = ((addr & (MSI_ADDR_RH | MSI_ADDR_LOG)) !=
(MSI_ADDR_RH | MSI_ADDR_LOG)); (MSI_ADDR_RH | MSI_ADDR_LOG));
delmode = msg & APIC_DELMODE_MASK; delmode = msg & APIC_DELMODE_MASK;
vec = msg & 0xff; vec = msg & 0xffUL;
dev_dbg(ACRN_DBG_LAPIC, "lapic MSI %s dest %#x, vec %d", dev_dbg(ACRN_DBG_LAPIC, "lapic MSI %s dest %#x, vec %d",
phys ? "physical" : "logical", dest, vec); phys ? "physical" : "logical", dest, vec);
@ -1937,7 +1937,7 @@ vlapic_mmio_write(struct vcpu *vcpu, uint64_t gpa, uint64_t wval, int size)
* Memory mapped local apic accesses must be 4 bytes wide and * Memory mapped local apic accesses must be 4 bytes wide and
* aligned on a 16-byte boundary. * aligned on a 16-byte boundary.
*/ */
if (size != 4 || (off & 0xf) != 0U) if (size != 4 || (off & 0xfUL) != 0U)
return -EINVAL; return -EINVAL;
vlapic = vcpu->arch_vcpu.vlapic; vlapic = vcpu->arch_vcpu.vlapic;
@ -1960,8 +1960,8 @@ vlapic_mmio_read(struct vcpu *vcpu, uint64_t gpa, uint64_t *rval,
* 16-byte boundary. They are also suggested to be 4 bytes * 16-byte boundary. They are also suggested to be 4 bytes
* wide, alas not all OSes follow suggestions. * wide, alas not all OSes follow suggestions.
*/ */
off &= ~3; off &= ~0x3UL;
if ((off & 0xf) != 0U) if ((off & 0xfUL) != 0UL)
return -EINVAL; return -EINVAL;
vlapic = vcpu->arch_vcpu.vlapic; vlapic = vcpu->arch_vcpu.vlapic;
@ -2116,7 +2116,7 @@ apicv_pending_intr(struct vlapic *vlapic, __unused uint32_t *vecptr)
return 0; return 0;
lapic = vlapic->apic_page; lapic = vlapic->apic_page;
ppr = lapic->ppr & 0xF0; ppr = lapic->ppr & 0xF0U;
if (ppr == 0) if (ppr == 0)
return 1; return 1;
@ -2124,7 +2124,7 @@ apicv_pending_intr(struct vlapic *vlapic, __unused uint32_t *vecptr)
for (i = 3; i >= 0; i--) { for (i = 3; i >= 0; i--) {
pirval = pir_desc->pir[i]; pirval = pir_desc->pir[i];
if (pirval != 0) { if (pirval != 0) {
vpr = (i * 64 + fls64(pirval)) & 0xF0; vpr = (i * 64 + fls64(pirval)) & 0xF0U;
return (vpr > ppr); return (vpr > ppr);
} }
} }
@ -2257,10 +2257,10 @@ apicv_inject_pir(struct vlapic *vlapic)
rvi = pirbase + fls64(pirval); rvi = pirbase + fls64(pirval);
intr_status_old = (uint16_t) intr_status_old = (uint16_t)
(0xFFFF & (0xFFFFUL &
exec_vmread(VMX_GUEST_INTR_STATUS)); exec_vmread(VMX_GUEST_INTR_STATUS));
intr_status_new = (intr_status_old & 0xFF00) | rvi; intr_status_new = (intr_status_old & 0xFF00U) | rvi;
if (intr_status_new > intr_status_old) if (intr_status_new > intr_status_old)
exec_vmwrite(VMX_GUEST_INTR_STATUS, exec_vmwrite(VMX_GUEST_INTR_STATUS,
intr_status_new); intr_status_new);
@ -2314,7 +2314,7 @@ int veoi_vmexit_handler(struct vcpu *vcpu)
vlapic = vcpu->arch_vcpu.vlapic; vlapic = vcpu->arch_vcpu.vlapic;
lapic = vlapic->apic_page; lapic = vlapic->apic_page;
vector = (vcpu->arch_vcpu.exit_qualification) & 0xFF; vector = (vcpu->arch_vcpu.exit_qualification) & 0xFFUL;
tmrptr = &lapic->tmr[0]; tmrptr = &lapic->tmr[0];
idx = vector / 32; idx = vector / 32;
@ -2337,7 +2337,7 @@ int apic_write_vmexit_handler(struct vcpu *vcpu)
struct vlapic *vlapic = NULL; struct vlapic *vlapic = NULL;
qual = vcpu->arch_vcpu.exit_qualification; qual = vcpu->arch_vcpu.exit_qualification;
offset = (qual & 0xFFF); offset = (qual & 0xFFFUL);
handled = 1; handled = 1;
VCPU_RETAIN_RIP(vcpu); VCPU_RETAIN_RIP(vcpu);

56
hypervisor/arch/x86/guest/vpic.c
View File

@ -81,9 +81,9 @@ struct vpic {
* Loop over all the pins in priority order from highest to lowest. * Loop over all the pins in priority order from highest to lowest.
*/ */
#define PIC_PIN_FOREACH(pinvar, pic, tmpvar) \ #define PIC_PIN_FOREACH(pinvar, pic, tmpvar) \
for (tmpvar = 0, pinvar = (pic->lowprio + 1) & 0x7; \ for (tmpvar = 0, pinvar = (pic->lowprio + 1) & 0x7U; \
tmpvar < 8; \ tmpvar < 8; \
tmpvar++, pinvar = (pinvar + 1) & 0x7) tmpvar++, pinvar = (pinvar + 1) & 0x7U)
static void vpic_set_pinstate(struct vpic *vpic, int pin, bool newstate); static void vpic_set_pinstate(struct vpic *vpic, int pin, bool newstate);
@ -102,7 +102,7 @@ static inline int vpic_get_highest_isrpin(struct pic *pic)
int i; int i;
PIC_PIN_FOREACH(pin, pic, i) { PIC_PIN_FOREACH(pin, pic, i) {
bit = (1 << pin); bit = (1U << pin);
if ((pic->service & bit) != 0U) { if ((pic->service & bit) != 0U) {
/* /*
@ -131,7 +131,7 @@ static inline int vpic_get_highest_irrpin(struct pic *pic)
*/ */
serviced = pic->service; serviced = pic->service;
if (pic->sfn) if (pic->sfn)
serviced &= ~(1 << 2); serviced &= ~(1U << 2);
/* /*
* In 'Special Mask Mode', when a mask bit is set in OCW1 it inhibits * In 'Special Mask Mode', when a mask bit is set in OCW1 it inhibits
@ -143,7 +143,7 @@ static inline int vpic_get_highest_irrpin(struct pic *pic)
serviced = 0; serviced = 0;
PIC_PIN_FOREACH(pin, pic, tmp) { PIC_PIN_FOREACH(pin, pic, tmp) {
bit = 1 << pin; bit = 1U << pin;
/* /*
* If there is already an interrupt in service at the same * If there is already an interrupt in service at the same
@ -282,7 +282,7 @@ static int vpic_icw2(struct vpic *vpic, struct pic *pic, uint8_t val)
dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic icw2 0x%x\n", dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic icw2 0x%x\n",
vpic->vm, val); vpic->vm, val);
pic->irq_base = val & 0xf8; pic->irq_base = val & 0xf8U;
pic->icw_num++; pic->icw_num++;
@ -355,7 +355,7 @@ static int vpic_ocw1(struct vpic *vpic, struct pic *pic, uint8_t val)
dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic ocw1 0x%x\n", dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic ocw1 0x%x\n",
vpic->vm, val); vpic->vm, val);
pic->mask = val & 0xff; pic->mask = val & 0xffU;
/* query and setup if pin/irq is for passthrough device */ /* query and setup if pin/irq is for passthrough device */
PIC_PIN_FOREACH(pin, pic, i) { PIC_PIN_FOREACH(pin, pic, i) {
@ -396,28 +396,28 @@ static int vpic_ocw2(struct vpic *vpic, struct pic *pic, uint8_t val)
if ((val & OCW2_SL) != 0) { if ((val & OCW2_SL) != 0) {
/* specific EOI */ /* specific EOI */
isr_bit = val & 0x7; isr_bit = val & 0x7U;
} else { } else {
/* non-specific EOI */ /* non-specific EOI */
isr_bit = vpic_get_highest_isrpin(pic); isr_bit = vpic_get_highest_isrpin(pic);
} }
if (isr_bit != -1) { if (isr_bit != -1) {
pic->service &= ~(1 << isr_bit); pic->service &= ~(1U << isr_bit);
if (pic->rotate) if (pic->rotate)
pic->lowprio = isr_bit; pic->lowprio = isr_bit;
} }
/* if level ack PTDEV */ /* if level ack PTDEV */
if ((pic->elc & (1 << (isr_bit & 0x7))) != 0U) { if ((pic->elc & (1U << (isr_bit & 0x7U))) != 0U) {
ptdev_intx_ack(vpic->vm, ptdev_intx_ack(vpic->vm,
master_pic(vpic, pic) ? isr_bit : isr_bit + 8, master_pic(vpic, pic) ? isr_bit : isr_bit + 8,
PTDEV_VPIN_PIC); PTDEV_VPIN_PIC);
} }
} else if ((val & OCW2_SL) != 0 && pic->rotate == true) { } else if ((val & OCW2_SL) != 0 && pic->rotate == true) {
/* specific priority */ /* specific priority */
pic->lowprio = val & 0x7; pic->lowprio = val & 0x7U;
} }
return 0; return 0;
@ -457,28 +457,28 @@ static void vpic_set_pinstate(struct vpic *vpic, int pin, bool newstate)
pic = &vpic->pic[pin >> 3]; pic = &vpic->pic[pin >> 3];
oldcnt = pic->acnt[pin & 0x7]; oldcnt = pic->acnt[pin & 0x7U];
if (newstate) if (newstate)
pic->acnt[pin & 0x7]++; pic->acnt[pin & 0x7U]++;
else else
pic->acnt[pin & 0x7]--; pic->acnt[pin & 0x7U]--;
newcnt = pic->acnt[pin & 0x7]; newcnt = pic->acnt[pin & 0x7U];
if (newcnt < 0) { if (newcnt < 0) {
pr_warn("pic pin%d: bad acnt %d\n", pin, newcnt); pr_warn("pic pin%d: bad acnt %d\n", pin, newcnt);
} }
level = ((vpic->pic[pin >> 3].elc & (1 << (pin & 0x7))) != 0); level = ((vpic->pic[pin >> 3].elc & (1 << (pin & 0x7U))) != 0);
if ((oldcnt == 0 && newcnt == 1) || (newcnt > 0 && level == true)) { if ((oldcnt == 0 && newcnt == 1) || (newcnt > 0 && level == true)) {
/* rising edge or level */ /* rising edge or level */
dev_dbg(ACRN_DBG_PIC, "pic pin%d: asserted\n", pin); dev_dbg(ACRN_DBG_PIC, "pic pin%d: asserted\n", pin);
pic->request |= (1 << (pin & 0x7)); pic->request |= (1 << (pin & 0x7U));
} else if (oldcnt == 1 && newcnt == 0) { } else if (oldcnt == 1 && newcnt == 0) {
/* falling edge */ /* falling edge */
dev_dbg(ACRN_DBG_PIC, "pic pin%d: deasserted\n", pin); dev_dbg(ACRN_DBG_PIC, "pic pin%d: deasserted\n", pin);
if (level) if (level)
pic->request &= ~(1 << (pin & 0x7)); pic->request &= ~(1 << (pin & 0x7U));
} else { } else {
dev_dbg(ACRN_DBG_PIC, dev_dbg(ACRN_DBG_PIC,
"pic pin%d: %s, ignored, acnt %d\n", "pic pin%d: %s, ignored, acnt %d\n",
@ -565,9 +565,9 @@ int vpic_set_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger trigger)
VPIC_LOCK(vpic); VPIC_LOCK(vpic);
if (trigger == LEVEL_TRIGGER) if (trigger == LEVEL_TRIGGER)
vpic->pic[irq >> 3].elc |= 1 << (irq & 0x7); vpic->pic[irq >> 3].elc |= 1U << (irq & 0x7U);
else else
vpic->pic[irq >> 3].elc &= ~(1 << (irq & 0x7)); vpic->pic[irq >> 3].elc &= ~(1U << (irq & 0x7U));
VPIC_UNLOCK(vpic); VPIC_UNLOCK(vpic);
@ -585,7 +585,7 @@ int vpic_get_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger *trigger
if (vpic == NULL) if (vpic == NULL)
return -EINVAL; return -EINVAL;
if ((vpic->pic[irq>>3].elc & (1 << (irq & 0x7))) != 0U) if ((vpic->pic[irq>>3].elc & (1U << (irq & 0x7U))) != 0U)
*trigger = LEVEL_TRIGGER; *trigger = LEVEL_TRIGGER;
else else
*trigger = EDGE_TRIGGER; *trigger = EDGE_TRIGGER;
@ -641,7 +641,7 @@ static void vpic_pin_accepted(struct pic *pic, int pin)
if (pic->rotate == true) if (pic->rotate == true)
pic->lowprio = pin; pic->lowprio = pin;
} else { } else {
pic->service |= (1 << pin); pic->service |= (1U << pin);
} }
} }
@ -654,9 +654,9 @@ void vpic_intr_accepted(struct vm *vm, uint32_t vector)
VPIC_LOCK(vpic); VPIC_LOCK(vpic);
pin = vector & 0x7; pin = vector & 0x7U;
if ((vector & ~0x7) == vpic->pic[1].irq_base) { if ((vector & ~0x7U) == vpic->pic[1].irq_base) {
vpic_pin_accepted(&vpic->pic[1], pin); vpic_pin_accepted(&vpic->pic[1], pin);
/* /*
* If this vector originated from the slave, * If this vector originated from the slave,
@ -684,9 +684,9 @@ static int vpic_read(struct vpic *vpic, struct pic *pic,
pin = vpic_get_highest_irrpin(pic); pin = vpic_get_highest_irrpin(pic);
if (pin >= 0) { if (pin >= 0) {
vpic_pin_accepted(pic, pin); vpic_pin_accepted(pic, pin);
*eax = 0x80 | pin; *eax = 0x80U | pin;
} else { } else {
*eax = 0; *eax = 0U;
} }
} else { } else {
if ((port & ICU_IMR_OFFSET) != 0) { if ((port & ICU_IMR_OFFSET) != 0) {
@ -863,9 +863,9 @@ static int vpic_elc_handler(struct vm *vm, bool in, int port, int bytes,
* be programmed for level mode. * be programmed for level mode.
*/ */
if (is_master) if (is_master)
vpic->pic[0].elc = (*eax & 0xf8); vpic->pic[0].elc = (*eax & 0xf8U);
else else
vpic->pic[1].elc = (*eax & 0xde); vpic->pic[1].elc = (*eax & 0xdeU);
} }
VPIC_UNLOCK(vpic); VPIC_UNLOCK(vpic);

68
hypervisor/arch/x86/ioapic.c
View File

@ -34,41 +34,41 @@ static struct ioapic_rte saved_rte[CONFIG_NR_IOAPICS][IOAPIC_MAX_PIN];
* hardcoded here * hardcoded here
*/ */
uint16_t legacy_irq_to_pin[NR_LEGACY_IRQ] = { uint16_t legacy_irq_to_pin[NR_LEGACY_IRQ] = {
2, /* IRQ0*/ 2U, /* IRQ0*/
1, /* IRQ1*/ 1U, /* IRQ1*/
0, /* IRQ2 connected to Pin0 (ExtInt source of PIC) if existing */ 0U, /* IRQ2 connected to Pin0 (ExtInt source of PIC) if existing */
3, /* IRQ3*/ 3U, /* IRQ3*/
4, /* IRQ4*/ 4U, /* IRQ4*/
5, /* IRQ5*/ 5U, /* IRQ5*/
6, /* IRQ6*/ 6U, /* IRQ6*/
7, /* IRQ7*/ 7U, /* IRQ7*/
8, /* IRQ8*/ 8U, /* IRQ8*/
9 | IOAPIC_RTE_TRGRLVL, /* IRQ9*/ 9U | IOAPIC_RTE_TRGRLVL, /* IRQ9*/
10, /* IRQ10*/ 10U, /* IRQ10*/
11, /* IRQ11*/ 11U, /* IRQ11*/
12, /* IRQ12*/ 12U, /* IRQ12*/
13, /* IRQ13*/ 13U, /* IRQ13*/
14, /* IRQ14*/ 14U, /* IRQ14*/
15, /* IRQ15*/ 15U, /* IRQ15*/
}; };
uint16_t pic_ioapic_pin_map[NR_LEGACY_PIN] = { uint16_t pic_ioapic_pin_map[NR_LEGACY_PIN] = {
2, /* pin0*/ 2U, /* pin0*/
1, /* pin1*/ 1U, /* pin1*/
0, /* pin2*/ 0U, /* pin2*/
3, /* pin3*/ 3U, /* pin3*/
4, /* pin4*/ 4U, /* pin4*/
5, /* pin5*/ 5U, /* pin5*/
6, /* pin6*/ 6U, /* pin6*/
7, /* pin7*/ 7U, /* pin7*/
8, /* pin8*/ 8U, /* pin8*/
9, /* pin9*/ 9U, /* pin9*/
10, /* pin10*/ 10U, /* pin10*/
11, /* pin11*/ 11U, /* pin11*/
12, /* pin12*/ 12U, /* pin12*/
13, /* pin13*/ 13U, /* pin13*/
14, /* pin14*/ 14U, /* pin14*/
15, /* pin15*/ 15U, /* pin15*/
}; };
static void *map_ioapic(uint64_t ioapic_paddr) static void *map_ioapic(uint64_t ioapic_paddr)
@ -167,7 +167,7 @@ create_rte_for_legacy_irq(uint32_t irq, uint32_t vr)
rte.lo_32 |= IOAPIC_RTE_INTALO; rte.lo_32 |= IOAPIC_RTE_INTALO;
/* Dest field: legacy irq fixed to CPU0 */ /* Dest field: legacy irq fixed to CPU0 */
rte.hi_32 |= 1 << 24; rte.hi_32 |= 1U << 24;
return rte; return rte;
} }
@ -327,7 +327,7 @@ void setup_ioapic_irq(void)
if (gsi < NR_LEGACY_IRQ) if (gsi < NR_LEGACY_IRQ)
gsi_table[gsi].pin = gsi_table[gsi].pin =
legacy_irq_to_pin[gsi] & 0xff; legacy_irq_to_pin[gsi] & 0xffU;
else else
gsi_table[gsi].pin = pin; gsi_table[gsi].pin = pin;

6
hypervisor/arch/x86/irq.c
View File

@ -41,10 +41,10 @@ spurious_handler_t spurious_handler;
static void init_irq_desc(void) static void init_irq_desc(void)
{ {
int i, page_num = 0; uint32_t i, page_num = 0;
int desc_size = NR_MAX_IRQS * sizeof(struct irq_desc); uint32_t desc_size = NR_MAX_IRQS * sizeof(struct irq_desc);
page_num = (desc_size + CPU_PAGE_SIZE-1) >> CPU_PAGE_SHIFT; page_num = (desc_size + CPU_PAGE_SIZE - 1U) >> CPU_PAGE_SHIFT;
irq_desc_base = alloc_pages(page_num); irq_desc_base = alloc_pages(page_num);

334
hypervisor/include/arch/x86/apicreg.h
View File

@ -268,161 +268,161 @@ struct ioapic {
*/ */
/* default physical locations of LOCAL (CPU) APICs */ /* default physical locations of LOCAL (CPU) APICs */
#define DEFAULT_APIC_BASE 0xfee00000 #define DEFAULT_APIC_BASE 0xfee00000U
/* constants relating to APIC ID registers */ /* constants relating to APIC ID registers */
#define APIC_ID_MASK 0xff000000 #define APIC_ID_MASK 0xff000000U
#define APIC_ID_SHIFT 24 #define APIC_ID_SHIFT 24
#define APIC_ID_CLUSTER 0xf0 #define APIC_ID_CLUSTER 0xf0U
#define APIC_ID_CLUSTER_ID 0x0f #define APIC_ID_CLUSTER_ID 0x0fU
#define APIC_MAX_CLUSTER 0xe #define APIC_MAX_CLUSTER 0xeU
#define APIC_MAX_INTRACLUSTER_ID 3 #define APIC_MAX_INTRACLUSTER_ID 3
#define APIC_ID_CLUSTER_SHIFT 4 #define APIC_ID_CLUSTER_SHIFT 4
/* fields in VER */ /* fields in VER */
#define APIC_VER_VERSION 0x000000ff #define APIC_VER_VERSION 0x000000ffU
#define APIC_VER_MAXLVT 0x00ff0000 #define APIC_VER_MAXLVT 0x00ff0000U
#define MAXLVTSHIFT 16 #define MAXLVTSHIFT 16
#define APIC_VER_EOI_SUPPRESSION 0x01000000 #define APIC_VER_EOI_SUPPRESSION 0x01000000U
#define APIC_VER_AMD_EXT_SPACE 0x80000000 #define APIC_VER_AMD_EXT_SPACE 0x80000000U
/* fields in LDR */ /* fields in LDR */
#define APIC_LDR_RESERVED 0x00ffffff #define APIC_LDR_RESERVED 0x00ffffffU
/* fields in DFR */ /* fields in DFR */
#define APIC_DFR_RESERVED 0x0fffffff #define APIC_DFR_RESERVED 0x0fffffffU
#define APIC_DFR_MODEL_MASK 0xf0000000 #define APIC_DFR_MODEL_MASK 0xf0000000U
#define APIC_DFR_MODEL_FLAT 0xf0000000 #define APIC_DFR_MODEL_FLAT 0xf0000000U
#define APIC_DFR_MODEL_CLUSTER 0x00000000 #define APIC_DFR_MODEL_CLUSTER 0x00000000U
/* fields in SVR */ /* fields in SVR */
#define APIC_SVR_VECTOR 0x000000ff #define APIC_SVR_VECTOR 0x000000ffU
#define APIC_SVR_VEC_PROG 0x000000f0 #define APIC_SVR_VEC_PROG 0x000000f0U
#define APIC_SVR_VEC_FIX 0x0000000f #define APIC_SVR_VEC_FIX 0x0000000fU
#define APIC_SVR_ENABLE 0x00000100 #define APIC_SVR_ENABLE 0x00000100U
#define APIC_SVR_SWDIS 0x00000000 #define APIC_SVR_SWDIS 0x00000000U
#define APIC_SVR_SWEN 0x00000100 #define APIC_SVR_SWEN 0x00000100U
#define APIC_SVR_FOCUS 0x00000200 #define APIC_SVR_FOCUS 0x00000200U
#define APIC_SVR_FEN 0x00000000 #define APIC_SVR_FEN 0x00000000U
#define APIC_SVR_FDIS 0x00000200 #define APIC_SVR_FDIS 0x00000200U
#define APIC_SVR_EOI_SUPPRESSION 0x00001000 #define APIC_SVR_EOI_SUPPRESSION 0x00001000U
/* fields in TPR */ /* fields in TPR */
#define APIC_TPR_PRIO 0x000000ff #define APIC_TPR_PRIO 0x000000ffU
#define APIC_TPR_INT 0x000000f0 #define APIC_TPR_INT 0x000000f0U
#define APIC_TPR_SUB 0x0000000f #define APIC_TPR_SUB 0x0000000fU
/* fields in ESR */ /* fields in ESR */
#define APIC_ESR_SEND_CS_ERROR 0x00000001 #define APIC_ESR_SEND_CS_ERROR 0x00000001U
#define APIC_ESR_RECEIVE_CS_ERROR 0x00000002 #define APIC_ESR_RECEIVE_CS_ERROR 0x00000002U
#define APIC_ESR_SEND_ACCEPT 0x00000004 #define APIC_ESR_SEND_ACCEPT 0x00000004U
#define APIC_ESR_RECEIVE_ACCEPT 0x00000008 #define APIC_ESR_RECEIVE_ACCEPT 0x00000008U
#define APIC_ESR_SEND_ILLEGAL_VECTOR 0x00000020 #define APIC_ESR_SEND_ILLEGAL_VECTOR 0x00000020U
#define APIC_ESR_RECEIVE_ILLEGAL_VECTOR 0x00000040 #define APIC_ESR_RECEIVE_ILLEGAL_VECTOR 0x00000040U
#define APIC_ESR_ILLEGAL_REGISTER 0x00000080 #define APIC_ESR_ILLEGAL_REGISTER 0x00000080U
/* fields in ICR_LOW */ /* fields in ICR_LOW */
#define APIC_VECTOR_MASK 0x000000ff #define APIC_VECTOR_MASK 0x000000ffU
#define APIC_DELMODE_MASK 0x00000700 #define APIC_DELMODE_MASK 0x00000700U
#define APIC_DELMODE_FIXED 0x00000000 #define APIC_DELMODE_FIXED 0x00000000U
#define APIC_DELMODE_LOWPRIO 0x00000100 #define APIC_DELMODE_LOWPRIO 0x00000100U
#define APIC_DELMODE_SMI 0x00000200 #define APIC_DELMODE_SMI 0x00000200U
#define APIC_DELMODE_RR 0x00000300 #define APIC_DELMODE_RR 0x00000300U
#define APIC_DELMODE_NMI 0x00000400 #define APIC_DELMODE_NMI 0x00000400U
#define APIC_DELMODE_INIT 0x00000500 #define APIC_DELMODE_INIT 0x00000500U
#define APIC_DELMODE_STARTUP 0x00000600 #define APIC_DELMODE_STARTUP 0x00000600U
#define APIC_DELMODE_RESV 0x00000700 #define APIC_DELMODE_RESV 0x00000700U
#define APIC_DESTMODE_MASK 0x00000800 #define APIC_DESTMODE_MASK 0x00000800U
#define APIC_DESTMODE_PHY 0x00000000 #define APIC_DESTMODE_PHY 0x00000000U
#define APIC_DESTMODE_LOG 0x00000800 #define APIC_DESTMODE_LOG 0x00000800U
#define APIC_DELSTAT_MASK 0x00001000 #define APIC_DELSTAT_MASK 0x00001000U
#define APIC_DELSTAT_IDLE 0x00000000 #define APIC_DELSTAT_IDLE 0x00000000U
#define APIC_DELSTAT_PEND 0x00001000 #define APIC_DELSTAT_PEND 0x00001000U
#define APIC_RESV1_MASK 0x00002000 #define APIC_RESV1_MASK 0x00002000U
#define APIC_LEVEL_MASK 0x00004000 #define APIC_LEVEL_MASK 0x00004000U
#define APIC_LEVEL_DEASSERT 0x00000000 #define APIC_LEVEL_DEASSERT 0x00000000U
#define APIC_LEVEL_ASSERT 0x00004000 #define APIC_LEVEL_ASSERT 0x00004000U
#define APIC_TRIGMOD_MASK 0x00008000 #define APIC_TRIGMOD_MASK 0x00008000U
#define APIC_TRIGMOD_EDGE 0x00000000 #define APIC_TRIGMOD_EDGE 0x00000000U
#define APIC_TRIGMOD_LEVEL 0x00008000 #define APIC_TRIGMOD_LEVEL 0x00008000U
#define APIC_RRSTAT_MASK 0x00030000 #define APIC_RRSTAT_MASK 0x00030000U
#define APIC_RRSTAT_INVALID 0x00000000 #define APIC_RRSTAT_INVALID 0x00000000U
#define APIC_RRSTAT_INPROG 0x00010000 #define APIC_RRSTAT_INPROG 0x00010000U
#define APIC_RRSTAT_VALID 0x00020000 #define APIC_RRSTAT_VALID 0x00020000U
#define APIC_RRSTAT_RESV 0x00030000 #define APIC_RRSTAT_RESV 0x00030000U
#define APIC_DEST_MASK 0x000c0000 #define APIC_DEST_MASK 0x000c0000U
#define APIC_DEST_DESTFLD 0x00000000 #define APIC_DEST_DESTFLD 0x00000000U
#define APIC_DEST_SELF 0x00040000 #define APIC_DEST_SELF 0x00040000U
#define APIC_DEST_ALLISELF 0x00080000 #define APIC_DEST_ALLISELF 0x00080000U
#define APIC_DEST_ALLESELF 0x000c0000 #define APIC_DEST_ALLESELF 0x000c0000U
#define APIC_RESV2_MASK 0xfff00000 #define APIC_RESV2_MASK 0xfff00000U
#define APIC_ICRLO_RESV_MASK (APIC_RESV1_MASK | APIC_RESV2_MASK) #define APIC_ICRLO_RESV_MASK (APIC_RESV1_MASK | APIC_RESV2_MASK)
/* fields in LVT1/2 */ /* fields in LVT1/2 */
#define APIC_LVT_VECTOR 0x000000ff #define APIC_LVT_VECTOR 0x000000ffU
#define APIC_LVT_DM 0x00000700 #define APIC_LVT_DM 0x00000700U
#define APIC_LVT_DM_FIXED 0x00000000 #define APIC_LVT_DM_FIXED 0x00000000U
#define APIC_LVT_DM_SMI 0x00000200 #define APIC_LVT_DM_SMI 0x00000200U
#define APIC_LVT_DM_NMI 0x00000400 #define APIC_LVT_DM_NMI 0x00000400U
#define APIC_LVT_DM_INIT 0x00000500 #define APIC_LVT_DM_INIT 0x00000500U
#define APIC_LVT_DM_EXTINT 0x00000700 #define APIC_LVT_DM_EXTINT 0x00000700U
#define APIC_LVT_DS 0x00001000 #define APIC_LVT_DS 0x00001000U
#define APIC_LVT_IIPP 0x00002000 #define APIC_LVT_IIPP 0x00002000U
#define APIC_LVT_IIPP_INTALO 0x00002000 #define APIC_LVT_IIPP_INTALO 0x00002000U
#define APIC_LVT_IIPP_INTAHI 0x00000000 #define APIC_LVT_IIPP_INTAHI 0x00000000U
#define APIC_LVT_RIRR 0x00004000 #define APIC_LVT_RIRR 0x00004000U
#define APIC_LVT_TM 0x00008000 #define APIC_LVT_TM 0x00008000U
#define APIC_LVT_M 0x00010000 #define APIC_LVT_M 0x00010000U
/* fields in LVT Timer */ /* fields in LVT Timer */
#define APIC_LVTT_VECTOR 0x000000ff #define APIC_LVTT_VECTOR 0x000000ffU
#define APIC_LVTT_DS 0x00001000 #define APIC_LVTT_DS 0x00001000U
#define APIC_LVTT_M 0x00010000 #define APIC_LVTT_M 0x00010000U
#define APIC_LVTT_TM 0x00060000 #define APIC_LVTT_TM 0x00060000U
#define APIC_LVTT_TM_ONE_SHOT 0x00000000 #define APIC_LVTT_TM_ONE_SHOT 0x00000000U
#define APIC_LVTT_TM_PERIODIC 0x00020000 #define APIC_LVTT_TM_PERIODIC 0x00020000U
#define APIC_LVTT_TM_TSCDLT 0x00040000 #define APIC_LVTT_TM_TSCDLT 0x00040000U
#define APIC_LVTT_TM_RSRV 0x00060000 #define APIC_LVTT_TM_RSRV 0x00060000U
/* APIC timer current count */ /* APIC timer current count */
#define APIC_TIMER_MAX_COUNT 0xffffffff #define APIC_TIMER_MAX_COUNT 0xffffffffU
/* fields in TDCR */ /* fields in TDCR */
#define APIC_TDCR_2 0x00 #define APIC_TDCR_2 0x00U
#define APIC_TDCR_4 0x01 #define APIC_TDCR_4 0x01U
#define APIC_TDCR_8 0x02 #define APIC_TDCR_8 0x02U
#define APIC_TDCR_16 0x03 #define APIC_TDCR_16 0x03U
#define APIC_TDCR_32 0x08 #define APIC_TDCR_32 0x08U
#define APIC_TDCR_64 0x09 #define APIC_TDCR_64 0x09U
#define APIC_TDCR_128 0x0a #define APIC_TDCR_128 0x0aU
#define APIC_TDCR_1 0x0b #define APIC_TDCR_1 0x0bU
/* Constants related to AMD Extended APIC Features Register */ /* Constants related to AMD Extended APIC Features Register */
#define APIC_EXTF_ELVT_MASK 0x00ff0000 #define APIC_EXTF_ELVT_MASK 0x00ff0000U
#define APIC_EXTF_ELVT_SHIFT 16 #define APIC_EXTF_ELVT_SHIFT 16
#define APIC_EXTF_EXTID_CAP 0x00000004 #define APIC_EXTF_EXTID_CAP 0x00000004U
#define APIC_EXTF_SEIO_CAP 0x00000002 #define APIC_EXTF_SEIO_CAP 0x00000002U
#define APIC_EXTF_IER_CAP 0x00000001 #define APIC_EXTF_IER_CAP 0x00000001U
/* LVT table indices */ /* LVT table indices */
#define APIC_LVT_TIMER 0 #define APIC_LVT_TIMER 0U
#define APIC_LVT_THERMAL 1 #define APIC_LVT_THERMAL 1U
#define APIC_LVT_PMC 2 #define APIC_LVT_PMC 2U
#define APIC_LVT_LINT0 3 #define APIC_LVT_LINT0 3U
#define APIC_LVT_LINT1 4 #define APIC_LVT_LINT1 4U
#define APIC_LVT_ERROR 5 #define APIC_LVT_ERROR 5U
#define APIC_LVT_CMCI 6 #define APIC_LVT_CMCI 6U
#define APIC_LVT_MAX APIC_LVT_CMCI #define APIC_LVT_MAX APIC_LVT_CMCI
/* AMD extended LVT constants, seem to be assigned by fiat */ /* AMD extended LVT constants, seem to be assigned by fiat */
@ -437,83 +437,83 @@ struct ioapic {
*/ */
/* default physical locations of an IO APIC */ /* default physical locations of an IO APIC */
#define DEFAULT_IO_APIC_BASE 0xfec00000 #define DEFAULT_IO_APIC_BASE 0xfec00000U
/* window register offset */ /* window register offset */
#define IOAPIC_WINDOW 0x10 #define IOAPIC_WINDOW 0x10U
#define IOAPIC_EOIR 0x40 #define IOAPIC_EOIR 0x40U
/* indexes into IO APIC */ /* indexes into IO APIC */
#define IOAPIC_ID 0x00 #define IOAPIC_ID 0x00U
#define IOAPIC_VER 0x01 #define IOAPIC_VER 0x01U
#define IOAPIC_ARB 0x02 #define IOAPIC_ARB 0x02U
#define IOAPIC_REDTBL 0x10 #define IOAPIC_REDTBL 0x10U
#define IOAPIC_REDTBL0 IOAPIC_REDTBL #define IOAPIC_REDTBL0 IOAPIC_REDTBL
#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02) #define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02U)
#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04) #define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04U)
#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06) #define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06U)
#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08) #define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08U)
#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a) #define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0aU)
#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c) #define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0cU)
#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e) #define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0eU)
#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10) #define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10U)
#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12) #define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12U)
#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14) #define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14U)
#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16) #define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16U)
#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18) #define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18U)
#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a) #define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1aU)
#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c) #define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1cU)
#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e) #define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1eU)
#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20) #define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20U)
#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22) #define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22U)
#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24) #define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24U)
#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26) #define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26U)
#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28) #define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28U)
#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a) #define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2aU)
#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c) #define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2cU)
#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e) #define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2eU)
/* fields in VER, for redirection entry */ /* fields in VER, for redirection entry */
#define IOAPIC_MAX_RTE_MASK 0x00ff0000 #define IOAPIC_MAX_RTE_MASK 0x00ff0000U
#define MAX_RTE_SHIFT 16 #define MAX_RTE_SHIFT 16U
/* /*
* fields in the IO APIC's redirection table entries * fields in the IO APIC's redirection table entries
*/ */
#define IOAPIC_RTE_DEST APIC_ID_MASK /* broadcast addr: all APICs */ #define IOAPIC_RTE_DEST APIC_ID_MASK /* broadcast addr: all APICs */
#define IOAPIC_RTE_RESV 0x00fe0000 /* reserved */ #define IOAPIC_RTE_RESV 0x00fe0000UL /* reserved */
#define IOAPIC_RTE_INTMASK 0x00010000 /* R/W: INTerrupt mask */ #define IOAPIC_RTE_INTMASK 0x00010000UL /* R/W: INTerrupt mask */
#define IOAPIC_RTE_INTMCLR 0x00000000 /* clear, allow INTs */ #define IOAPIC_RTE_INTMCLR 0x00000000UL /* clear, allow INTs */
#define IOAPIC_RTE_INTMSET 0x00010000 /* set, inhibit INTs */ #define IOAPIC_RTE_INTMSET 0x00010000UL /* set, inhibit INTs */
#define IOAPIC_RTE_TRGRMOD 0x00008000 /* R/W: trigger mode */ #define IOAPIC_RTE_TRGRMOD 0x00008000UL /* R/W: trigger mode */
#define IOAPIC_RTE_TRGREDG 0x00000000 /* edge */ #define IOAPIC_RTE_TRGREDG 0x00000000UL /* edge */
#define IOAPIC_RTE_TRGRLVL 0x00008000 /* level */ #define IOAPIC_RTE_TRGRLVL 0x00008000UL /* level */
#define IOAPIC_RTE_REM_IRR 0x00004000 /* RO: remote IRR */ #define IOAPIC_RTE_REM_IRR 0x00004000UL /* RO: remote IRR */
#define IOAPIC_RTE_INTPOL 0x00002000 /*R/W:INT input pin polarity*/ #define IOAPIC_RTE_INTPOL 0x00002000UL /*R/W:INT input pin polarity*/
#define IOAPIC_RTE_INTAHI 0x00000000 /* active high */ #define IOAPIC_RTE_INTAHI 0x00000000UL /* active high */
#define IOAPIC_RTE_INTALO 0x00002000 /* active low */ #define IOAPIC_RTE_INTALO 0x00002000UL /* active low */
#define IOAPIC_RTE_DELIVS 0x00001000 /* RO: delivery status */ #define IOAPIC_RTE_DELIVS 0x00001000UL /* RO: delivery status */
#define IOAPIC_RTE_DESTMOD 0x00000800 /*R/W:destination mode*/ #define IOAPIC_RTE_DESTMOD 0x00000800UL /*R/W:destination mode*/
#define IOAPIC_RTE_DESTPHY 0x00000000 /* physical */ #define IOAPIC_RTE_DESTPHY 0x00000000UL /* physical */
#define IOAPIC_RTE_DESTLOG 0x00000800 /* logical */ #define IOAPIC_RTE_DESTLOG 0x00000800UL /* logical */
#define IOAPIC_RTE_DELMOD 0x00000700 /* R/W: delivery mode */ #define IOAPIC_RTE_DELMOD 0x00000700UL /* R/W: delivery mode */
#define IOAPIC_RTE_DELFIXED 0x00000000 /* fixed */ #define IOAPIC_RTE_DELFIXED 0x00000000UL /* fixed */
#define IOAPIC_RTE_DELLOPRI 0x00000100 /* lowest priority */ #define IOAPIC_RTE_DELLOPRI 0x00000100UL /* lowest priority */
#define IOAPIC_RTE_DELSMI 0x00000200 /*System Management INT*/ #define IOAPIC_RTE_DELSMI 0x00000200UL /*System Management INT*/
#define IOAPIC_RTE_DELRSV1 0x00000300 /* reserved */ #define IOAPIC_RTE_DELRSV1 0x00000300UL /* reserved */
#define IOAPIC_RTE_DELNMI 0x00000400 /* NMI signal */ #define IOAPIC_RTE_DELNMI 0x00000400UL /* NMI signal */
#define IOAPIC_RTE_DELINIT 0x00000500 /* INIT signal */ #define IOAPIC_RTE_DELINIT 0x00000500UL /* INIT signal */
#define IOAPIC_RTE_DELRSV2 0x00000600 /* reserved */ #define IOAPIC_RTE_DELRSV2 0x00000600UL /* reserved */
#define IOAPIC_RTE_DELEXINT 0x00000700 /* External INTerrupt */ #define IOAPIC_RTE_DELEXINT 0x00000700UL /* External INTerrupt */
#define IOAPIC_RTE_INTVEC 0x000000ff /*R/W: INT vector field*/ #define IOAPIC_RTE_INTVEC 0x000000ffUL /*R/W: INT vector field*/
#endif /* _APICREG_H_ */ #endif /* _APICREG_H_ */

50
hypervisor/include/arch/x86/guest/vpic.h
View File

@ -30,14 +30,14 @@
#ifndef _VPIC_H_ #ifndef _VPIC_H_
#define _VPIC_H_ #define _VPIC_H_
#define ICU_IMR_OFFSET 1 #define ICU_IMR_OFFSET 1U
/* Initialization control word 1. Written to even address. */ /* Initialization control word 1. Written to even address. */
#define ICW1_IC4 0x01 /* ICW4 present */ #define ICW1_IC4 0x01U /* ICW4 present */
#define ICW1_SNGL 0x02 /* 1 = single, 0 = cascaded */ #define ICW1_SNGL 0x02U /* 1 = single, 0 = cascaded */
#define ICW1_ADI 0x04 /* 1 = 4, 0 = 8 byte vectors */ #define ICW1_ADI 0x04U /* 1 = 4, 0 = 8 byte vectors */
#define ICW1_LTIM 0x08 /* 1 = level trigger, 0 = edge */ #define ICW1_LTIM 0x08U /* 1 = level trigger, 0 = edge */
#define ICW1_RESET 0x10 /* must be 1 */ #define ICW1_RESET 0x10U /* must be 1 */
/* 0x20 - 0x80 - in 8080/8085 mode only */ /* 0x20 - 0x80 - in 8080/8085 mode only */
/* Initialization control word 2. Written to the odd address. */ /* Initialization control word 2. Written to the odd address. */
@ -48,11 +48,11 @@
/* For slave, lower 3 bits are the slave's ID binary id on master */ /* For slave, lower 3 bits are the slave's ID binary id on master */
/* Initialization control word 4. Written to the odd address. */ /* Initialization control word 4. Written to the odd address. */
#define ICW4_8086 0x01 /* 1 = 8086, 0 = 8080 */ #define ICW4_8086 0x01U /* 1 = 8086, 0 = 8080 */
#define ICW4_AEOI 0x02 /* 1 = Auto EOI */ #define ICW4_AEOI 0x02U /* 1 = Auto EOI */
#define ICW4_MS 0x04 /* 1 = buffered master, 0 = slave */ #define ICW4_MS 0x04U /* 1 = buffered master, 0 = slave */
#define ICW4_BUF 0x08 /* 1 = enable buffer mode */ #define ICW4_BUF 0x08U /* 1 = enable buffer mode */
#define ICW4_SFNM 0x10 /* 1 = special fully nested mode */ #define ICW4_SFNM 0x10U /* 1 = special fully nested mode */
/* Operation control words. Written after initialization. */ /* Operation control words. Written after initialization. */
@ -63,27 +63,27 @@
*/ */
/* Operation control word type 2. Bit 3 (0x08) must be zero. Even address. */ /* Operation control word type 2. Bit 3 (0x08) must be zero. Even address. */
#define OCW2_L0 0x01 /* Level */ #define OCW2_L0 0x01U /* Level */
#define OCW2_L1 0x02 #define OCW2_L1 0x02U
#define OCW2_L2 0x04 #define OCW2_L2 0x04U
/* 0x08 must be 0 to select OCW2 vs OCW3 */ /* 0x08 must be 0 to select OCW2 vs OCW3 */
/* 0x10 must be 0 to select OCW2 vs ICW1 */ /* 0x10 must be 0 to select OCW2 vs ICW1 */
#define OCW2_EOI 0x20 /* 1 = EOI */ #define OCW2_EOI 0x20U /* 1 = EOI */
#define OCW2_SL 0x40 /* EOI mode */ #define OCW2_SL 0x40U /* EOI mode */
#define OCW2_R 0x80 /* EOI mode */ #define OCW2_R 0x80U /* EOI mode */
/* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */ /* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */
#define OCW3_RIS 0x01 /* 1 = read IS, 0 = read IR */ #define OCW3_RIS 0x01U /* 1 = read IS, 0 = read IR */
#define OCW3_RR 0x02 /* register read */ #define OCW3_RR 0x02U /* register read */
#define OCW3_P 0x04 /* poll mode command */ #define OCW3_P 0x04U /* poll mode command */
/* 0x08 must be 1 to select OCW3 vs OCW2 */ /* 0x08 must be 1 to select OCW3 vs OCW2 */
#define OCW3_SEL 0x08 /* must be 1 */ #define OCW3_SEL 0x08U /* must be 1 */
/* 0x10 must be 0 to select OCW3 vs ICW1 */ /* 0x10 must be 0 to select OCW3 vs ICW1 */
#define OCW3_SMM 0x20 /* special mode mask */ #define OCW3_SMM 0x20U /* special mode mask */
#define OCW3_ESMM 0x40 /* enable SMM */ #define OCW3_ESMM 0x40U /* enable SMM */
#define IO_ELCR1 0x4d0 #define IO_ELCR1 0x4d0U
#define IO_ELCR2 0x4d1 #define IO_ELCR2 0x4d1U
enum vpic_trigger { enum vpic_trigger {
EDGE_TRIGGER, EDGE_TRIGGER,

44
hypervisor/include/arch/x86/irq.h
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@ -8,30 +8,30 @@
#define IRQ_H #define IRQ_H
/* vectors for normal, usually for devices */ /* vectors for normal, usually for devices */
#define VECTOR_FOR_NOR_LOWPRI_START 0x20 #define VECTOR_FOR_NOR_LOWPRI_START 0x20U
#define VECTOR_FOR_NOR_LOWPRI_END 0x7F #define VECTOR_FOR_NOR_LOWPRI_END 0x7FU
#define VECTOR_FOR_NOR_HIGHPRI_START 0x80 #define VECTOR_FOR_NOR_HIGHPRI_START 0x80U
#define VECTOR_FOR_NOR_HIGHPRI_END 0xDF #define VECTOR_FOR_NOR_HIGHPRI_END 0xDFU
#define VECTOR_FOR_NOR_END VECTOR_FOR_NOR_HIGHPRI_END #define VECTOR_FOR_NOR_END VECTOR_FOR_NOR_HIGHPRI_END
#define VECTOR_FOR_INTR_START VECTOR_FOR_NOR_LOWPRI_START #define VECTOR_FOR_INTR_START VECTOR_FOR_NOR_LOWPRI_START
/* vectors for priority, usually for HV service */ /* vectors for priority, usually for HV service */
#define VECTOR_FOR_PRI_START 0xE0 #define VECTOR_FOR_PRI_START 0xE0U
#define VECTOR_FOR_PRI_END 0xFF #define VECTOR_FOR_PRI_END 0xFFU
#define VECTOR_TIMER 0xEF #define VECTOR_TIMER 0xEFU
#define VECTOR_NOTIFY_VCPU 0xF0 #define VECTOR_NOTIFY_VCPU 0xF0U
#define VECTOR_VIRT_IRQ_VHM 0xF7 #define VECTOR_VIRT_IRQ_VHM 0xF7U
#define VECTOR_SPURIOUS 0xFF #define VECTOR_SPURIOUS 0xFFU
#define NR_MAX_VECTOR 0xFF #define NR_MAX_VECTOR 0xFFU
#define VECTOR_INVALID (NR_MAX_VECTOR + 1) #define VECTOR_INVALID (NR_MAX_VECTOR + 1U)
#define NR_MAX_IRQS (256+16) #define NR_MAX_IRQS (256U + 16U)
#define IRQ_INVALID (NR_MAX_IRQS+1) #define IRQ_INVALID (NR_MAX_IRQS + 1U)
#define DEFAULT_DEST_MODE IOAPIC_RTE_DESTLOG #define DEFAULT_DEST_MODE IOAPIC_RTE_DESTLOG
#define DEFAULT_DELIVERY_MODE IOAPIC_RTE_DELLOPRI #define DEFAULT_DELIVERY_MODE IOAPIC_RTE_DELLOPRI
#define ALL_CPUS_MASK ((1 << phy_cpu_num) - 1) #define ALL_CPUS_MASK ((1U << phy_cpu_num) - 1U)
struct irq_desc; struct irq_desc;
@ -145,17 +145,17 @@ extern spurious_handler_t spurious_handler;
/* /*
* Some MSI message definitions * Some MSI message definitions
*/ */
#define MSI_ADDR_MASK 0xfff00000 #define MSI_ADDR_MASK 0xfff00000U
#define MSI_ADDR_BASE 0xfee00000 #define MSI_ADDR_BASE 0xfee00000U
#define MSI_ADDR_RH 0x00000008 /* Redirection Hint */ #define MSI_ADDR_RH 0x00000008U /* Redirection Hint */
#define MSI_ADDR_LOG 0x00000004 /* Destination Mode */ #define MSI_ADDR_LOG 0x00000004U /* Destination Mode */
/* RFLAGS */ /* RFLAGS */
#define HV_ARCH_VCPU_RFLAGS_IF (1<<9) #define HV_ARCH_VCPU_RFLAGS_IF (1U<<9)
/* Interruptability State info */ /* Interruptability State info */
#define HV_ARCH_VCPU_BLOCKED_BY_MOVSS (1<<1) #define HV_ARCH_VCPU_BLOCKED_BY_MOVSS (1U<<1)
#define HV_ARCH_VCPU_BLOCKED_BY_STI (1<<0) #define HV_ARCH_VCPU_BLOCKED_BY_STI (1U<<0)
void vcpu_inject_extint(struct vcpu *vcpu); void vcpu_inject_extint(struct vcpu *vcpu);
void vcpu_inject_nmi(struct vcpu *vcpu); void vcpu_inject_nmi(struct vcpu *vcpu);

116
hypervisor/include/arch/x86/lapic.h
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@ -41,75 +41,75 @@ enum intr_lapic_icr_shorthand {
}; };
/* Default LAPIC base */ /* Default LAPIC base */
#define LAPIC_BASE 0xFEE00000 #define LAPIC_BASE 0xFEE00000U
/* LAPIC register offset for memory mapped IO access */ /* LAPIC register offset for memory mapped IO access */
#define LAPIC_ID_REGISTER 0x00000020 #define LAPIC_ID_REGISTER 0x00000020U
#define LAPIC_VERSION_REGISTER 0x00000030 #define LAPIC_VERSION_REGISTER 0x00000030U
#define LAPIC_TASK_PRIORITY_REGISTER 0x00000080 #define LAPIC_TASK_PRIORITY_REGISTER 0x00000080U
#define LAPIC_ARBITRATION_PRIORITY_REGISTER 0x00000090 #define LAPIC_ARBITRATION_PRIORITY_REGISTER 0x00000090U
#define LAPIC_PROCESSOR_PRIORITY_REGISTER 0x000000A0 #define LAPIC_PROCESSOR_PRIORITY_REGISTER 0x000000A0U
#define LAPIC_EOI_REGISTER 0x000000B0 #define LAPIC_EOI_REGISTER 0x000000B0U
#define LAPIC_REMOTE_READ_REGISTER 0x000000C0 #define LAPIC_REMOTE_READ_REGISTER 0x000000C0U
#define LAPIC_LOGICAL_DESTINATION_REGISTER 0x000000D0 #define LAPIC_LOGICAL_DESTINATION_REGISTER 0x000000D0U
#define LAPIC_DESTINATION_FORMAT_REGISTER 0x000000E0 #define LAPIC_DESTINATION_FORMAT_REGISTER 0x000000E0U
#define LAPIC_SPURIOUS_VECTOR_REGISTER 0x000000F0 #define LAPIC_SPURIOUS_VECTOR_REGISTER 0x000000F0U
#define LAPIC_IN_SERVICE_REGISTER_0 0x00000100 #define LAPIC_IN_SERVICE_REGISTER_0 0x00000100U
#define LAPIC_IN_SERVICE_REGISTER_1 0x00000110 #define LAPIC_IN_SERVICE_REGISTER_1 0x00000110U
#define LAPIC_IN_SERVICE_REGISTER_2 0x00000120 #define LAPIC_IN_SERVICE_REGISTER_2 0x00000120U
#define LAPIC_IN_SERVICE_REGISTER_3 0x00000130 #define LAPIC_IN_SERVICE_REGISTER_3 0x00000130U
#define LAPIC_IN_SERVICE_REGISTER_4 0x00000140 #define LAPIC_IN_SERVICE_REGISTER_4 0x00000140U
#define LAPIC_IN_SERVICE_REGISTER_5 0x00000150 #define LAPIC_IN_SERVICE_REGISTER_5 0x00000150U
#define LAPIC_IN_SERVICE_REGISTER_6 0x00000160 #define LAPIC_IN_SERVICE_REGISTER_6 0x00000160U
#define LAPIC_IN_SERVICE_REGISTER_7 0x00000170 #define LAPIC_IN_SERVICE_REGISTER_7 0x00000170U
#define LAPIC_TRIGGER_MODE_REGISTER_0 0x00000180 #define LAPIC_TRIGGER_MODE_REGISTER_0 0x00000180U
#define LAPIC_TRIGGER_MODE_REGISTER_1 0x00000190 #define LAPIC_TRIGGER_MODE_REGISTER_1 0x00000190U
#define LAPIC_TRIGGER_MODE_REGISTER_2 0x000001A0 #define LAPIC_TRIGGER_MODE_REGISTER_2 0x000001A0U
#define LAPIC_TRIGGER_MODE_REGISTER_3 0x000001B0 #define LAPIC_TRIGGER_MODE_REGISTER_3 0x000001B0U
#define LAPIC_TRIGGER_MODE_REGISTER_4 0x000001C0 #define LAPIC_TRIGGER_MODE_REGISTER_4 0x000001C0U
#define LAPIC_TRIGGER_MODE_REGISTER_5 0x000001D0 #define LAPIC_TRIGGER_MODE_REGISTER_5 0x000001D0U
#define LAPIC_TRIGGER_MODE_REGISTER_6 0x000001E0 #define LAPIC_TRIGGER_MODE_REGISTER_6 0x000001E0U
#define LAPIC_TRIGGER_MODE_REGISTER_7 0x000001F0 #define LAPIC_TRIGGER_MODE_REGISTER_7 0x000001F0U
#define LAPIC_INT_REQUEST_REGISTER_0 0x00000200 #define LAPIC_INT_REQUEST_REGISTER_0 0x00000200U
#define LAPIC_INT_REQUEST_REGISTER_1 0x00000210 #define LAPIC_INT_REQUEST_REGISTER_1 0x00000210U
#define LAPIC_INT_REQUEST_REGISTER_2 0x00000220 #define LAPIC_INT_REQUEST_REGISTER_2 0x00000220U
#define LAPIC_INT_REQUEST_REGISTER_3 0x00000230 #define LAPIC_INT_REQUEST_REGISTER_3 0x00000230U
#define LAPIC_INT_REQUEST_REGISTER_4 0x00000240 #define LAPIC_INT_REQUEST_REGISTER_4 0x00000240U
#define LAPIC_INT_REQUEST_REGISTER_5 0x00000250 #define LAPIC_INT_REQUEST_REGISTER_5 0x00000250U
#define LAPIC_INT_REQUEST_REGISTER_6 0x00000260 #define LAPIC_INT_REQUEST_REGISTER_6 0x00000260U
#define LAPIC_INT_REQUEST_REGISTER_7 0x00000270 #define LAPIC_INT_REQUEST_REGISTER_7 0x00000270U
#define LAPIC_ERROR_STATUS_REGISTER 0x00000280 #define LAPIC_ERROR_STATUS_REGISTER 0x00000280U
#define LAPIC_LVT_CMCI_REGISTER 0x000002F0 #define LAPIC_LVT_CMCI_REGISTER 0x000002F0U
#define LAPIC_INT_COMMAND_REGISTER_0 0x00000300 #define LAPIC_INT_COMMAND_REGISTER_0 0x00000300U
#define LAPIC_INT_COMMAND_REGISTER_1 0x00000310 #define LAPIC_INT_COMMAND_REGISTER_1 0x00000310U
#define LAPIC_LVT_TIMER_REGISTER 0x00000320 #define LAPIC_LVT_TIMER_REGISTER 0x00000320U
#define LAPIC_LVT_THERMAL_SENSOR_REGISTER 0x00000330 #define LAPIC_LVT_THERMAL_SENSOR_REGISTER 0x00000330U
#define LAPIC_LVT_PMC_REGISTER 0x00000340 #define LAPIC_LVT_PMC_REGISTER 0x00000340U
#define LAPIC_LVT_LINT0_REGISTER 0x00000350 #define LAPIC_LVT_LINT0_REGISTER 0x00000350U
#define LAPIC_LVT_LINT1_REGISTER 0x00000360 #define LAPIC_LVT_LINT1_REGISTER 0x00000360U
#define LAPIC_LVT_ERROR_REGISTER 0x00000370 #define LAPIC_LVT_ERROR_REGISTER 0x00000370U
#define LAPIC_INITIAL_COUNT_REGISTER 0x00000380 #define LAPIC_INITIAL_COUNT_REGISTER 0x00000380U
#define LAPIC_CURRENT_COUNT_REGISTER 0x00000390 #define LAPIC_CURRENT_COUNT_REGISTER 0x00000390U
#define LAPIC_DIVIDE_CONFIGURATION_REGISTER 0x000003E0 #define LAPIC_DIVIDE_CONFIGURATION_REGISTER 0x000003E0U
/* LAPIC CPUID bit and bitmask definitions */ /* LAPIC CPUID bit and bitmask definitions */
#define CPUID_OUT_RDX_APIC_PRESENT ((uint64_t) 1 << 9) #define CPUID_OUT_RDX_APIC_PRESENT ((uint64_t) 1UL << 9)
#define CPUID_OUT_RCX_X2APIC_PRESENT ((uint64_t) 1 << 21) #define CPUID_OUT_RCX_X2APIC_PRESENT ((uint64_t) 1UL << 21)
/* LAPIC MSR bit and bitmask definitions */ /* LAPIC MSR bit and bitmask definitions */
#define MSR_01B_XAPIC_GLOBAL_ENABLE ((uint64_t) 1 << 11) #define MSR_01B_XAPIC_GLOBAL_ENABLE ((uint64_t) 1UL << 11)
/* LAPIC register bit and bitmask definitions */ /* LAPIC register bit and bitmask definitions */
#define LAPIC_SVR_VECTOR 0x000000FF #define LAPIC_SVR_VECTOR 0x000000FFU
#define LAPIC_SVR_APIC_ENABLE_MASK 0x00000100 #define LAPIC_SVR_APIC_ENABLE_MASK 0x00000100U
#define LAPIC_LVT_MASK 0x00010000 #define LAPIC_LVT_MASK 0x00010000U
#define LAPIC_DELIVERY_MODE_EXTINT_MASK 0x00000700 #define LAPIC_DELIVERY_MODE_EXTINT_MASK 0x00000700U
/* LAPIC Timer bit and bitmask definitions */ /* LAPIC Timer bit and bitmask definitions */
#define LAPIC_TMR_ONESHOT ((uint32_t) 0x0 << 17) #define LAPIC_TMR_ONESHOT ((uint32_t) 0x0U << 17)
#define LAPIC_TMR_PERIODIC ((uint32_t) 0x1 << 17) #define LAPIC_TMR_PERIODIC ((uint32_t) 0x1U << 17)
#define LAPIC_TMR_TSC_DEADLINE ((uint32_t) 0x2 << 17) #define LAPIC_TMR_TSC_DEADLINE ((uint32_t) 0x2U << 17)
enum intr_cpu_startup_shorthand { enum intr_cpu_startup_shorthand {
INTR_CPU_STARTUP_USE_DEST, INTR_CPU_STARTUP_USE_DEST,