HV: CAT: capability enumaration

Enumarate capability of Cache Allocation Technology(CAT) on X86 platform,
when HV init the primary cpu. If CAT is supported, store its info
to global struct cat_hw_info.

Tracked-On: #2462
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

hypervisor/include/arch/x86/cat.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CAT_H
+#define CAT_H
+
+/* The intel Resource Director Tech(RDT) based Cache Allocation Tech support */
+struct cat_hw_info {
+	bool support;		/* If L2/L3 CAT supported */
+	bool enabled;		/* If any VM setup CLOS */
+	uint32_t bitmask;	/* Used by other entities */
+	uint16_t cbm_len;	/* Length of Cache mask in bits */
+	uint16_t clos_max;	/* Maximum CLOS supported, the number of cache masks */
+
+	uint32_t res_id;
+};
+
+extern struct cat_hw_info cat_cap_info;
+
+#define CAT_RESID_L3   1U
+#define CAT_RESID_L2   2U
+
+int32_t init_cat_cap_info(void);
+
+#endif	/* CAT_H */

hypervisor/include/arch/x86/cpufeatures.h

@@ -73,6 +73,7 @@
 #define X86_FEATURE_SMEP	((FEAT_7_0_EBX << 5U) +  7U)
 #define X86_FEATURE_ERMS	((FEAT_7_0_EBX << 5U) +  9U)
 #define X86_FEATURE_INVPCID	((FEAT_7_0_EBX << 5U) + 10U)
+#define X86_FEATURE_CAT        ((FEAT_7_0_EBX << 5U) + 15U)
 #define X86_FEATURE_SMAP	((FEAT_7_0_EBX << 5U) + 20U)
 
 /* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/

hypervisor/include/arch/x86/cpuid.h

@@ -100,6 +100,7 @@
 #define CPUID_TLB               2U
 #define CPUID_SERIALNUM         3U
 #define CPUID_EXTEND_FEATURE    7U
+#define CPUID_RSD_ALLOCATION   0x10U
 #define CPUID_MAX_EXTENDED_FUNCTION  0x80000000U
 #define CPUID_EXTEND_FUNCTION_1      0x80000001U
 #define CPUID_EXTEND_FUNCTION_2      0x80000002U