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hv: pci_priv.h code cleanup
- move most of the content of pci_priv.h to include/dm/pci.h. This allows other code outside dm/vpci to be able to share these macros. - code cleanup: fix alignments etc. Tracked-On: #1568 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Reviewed-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Zide Chen
Xie, Nanlin
parent
a43ff9ce98
commit
4741fcfff2
@ -101,6 +101,7 @@ INCLUDE_PATH += include/debug
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INCLUDE_PATH += include/public
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ifeq ($(CONFIG_PARTITION_MODE),y)
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INCLUDE_PATH += include/dm/vpci
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INCLUDE_PATH += include/dm
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endif
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INCLUDE_PATH += bsp/include
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INCLUDE_PATH += bsp/include/$(CONFIG_PLATFORM)
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@ -30,35 +30,7 @@
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#ifndef PCI_PRIV_H_
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#define PCI_PRIV_H_
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#include <hv_debug.h>
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#include "vpci.h"
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#define PCIM_BAR_MEM_BASE 0xFFFFFFF0U
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#define PCI_BUSMAX 0xFFU
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#define PCI_SLOTMAX 0x1FU
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#define PCI_FUNCMAX 0x7U
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#define PCIR_VENDOR 0x00U
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#define PCIR_DEVICE 0x02U
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#define PCIR_COMMAND 0x04U
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#define PCIR_REVID 0x08U
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#define PCIR_SUBCLASS 0x0AU
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#define PCIR_CLASS 0x0BU
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#define PCIR_HDRTYPE 0x0EU
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#define PCIM_HDRTYPE_NORMAL 0x00U
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#define PCIM_MFDEV 0x80U
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#define PCIC_BRIDGE 0x06U
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#define PCIS_BRIDGE_HOST 0x00U
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#define PCI_CONFIG_ADDR 0xCF8U
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#define PCI_CONFIG_DATA 0xCFCU
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#define PCI_CFG_ENABLE 0x80000000U
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void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in,
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union pci_bdf vbdf, uint32_t offset, uint32_t bytes, uint32_t *val);
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#include <pci.h>
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static inline uint8_t
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pci_vdev_read_cfg_u8(struct pci_vdev *vdev, uint32_t offset)
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@ -132,19 +104,7 @@ static inline void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset,
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}
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}
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static inline uint32_t pci_bar_offset(uint32_t idx)
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{
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return 0x10U + (idx << 2U);
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}
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static inline int pci_bar_access(uint32_t offset)
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{
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if ((offset >= pci_bar_offset(0U))
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&& (offset < pci_bar_offset(PCI_BAR_COUNT))) {
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return 1;
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} else {
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return 0;
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}
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}
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void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in,
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union pci_bdf vbdf, uint32_t offset, uint32_t bytes, uint32_t *val);
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#endif /* PCI_PRIV_H_ */
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72
hypervisor/include/dm/pci.h
Normal file
72
hypervisor/include/dm/pci.h
Normal file
@ -0,0 +1,72 @@
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/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef PCI_H_
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#define PCI_H_
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#define PCIM_BAR_MEM_BASE 0xFFFFFFF0U
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#define PCI_BUSMAX 0xFFU
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#define PCI_SLOTMAX 0x1FU
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#define PCI_FUNCMAX 0x7U
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#define PCIR_VENDOR 0x00U
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#define PCIR_DEVICE 0x02U
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#define PCIR_COMMAND 0x04U
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#define PCIR_REVID 0x08U
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#define PCIR_SUBCLASS 0x0AU
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#define PCIR_CLASS 0x0BU
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#define PCIR_HDRTYPE 0x0EU
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#define PCIM_HDRTYPE_NORMAL 0x00U
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#define PCIM_MFDEV 0x80U
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#define PCIC_BRIDGE 0x06U
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#define PCIS_BRIDGE_HOST 0x00U
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#define PCI_CONFIG_ADDR 0xCF8U
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#define PCI_CONFIG_DATA 0xCFCU
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#define PCI_CFG_ENABLE 0x80000000U
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static inline uint32_t pci_bar_offset(uint32_t idx)
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{
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return 0x10U + (idx << 2U);
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}
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static inline int pci_bar_access(uint32_t offset)
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{
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if ((offset >= pci_bar_offset(0U))
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&& (offset < pci_bar_offset(PCI_BAR_COUNT))) {
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return 1;
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} else {
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return 0;
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}
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}
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#endif /* PCI_H_ */
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