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https://github.com/projectacrn/acrn-hypervisor.git
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HV: correct ept page array usage
Currently ept_pages_info[] is initialized with first element only that force VM of id 0 using SOS EPT pages. This is incorrect for logical partition and hybrid scenario. Considering SOS_RAM_SIZE and UOS_RAM_SIZE are configured separately, we should use different ept pages accordingly. So, the PRE_VM_NUM/SOS_VM_NUM and MAX_POST_VM_NUM macros are introduced to resolve this issue. The macros would be generated by acrn-config tool when user configure ACRN for their specific scenario. One more thing, that when UOS_RAM_SIZE is less then 2GB, the EPT address range should be (4G + PLATFORM_HI_MMIO_SIZE). Tracked-On: #4458 Signed-off-by: Victor Sun <victor.sun@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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e9a99845f6
commit
4c0965d89e
@ -277,10 +277,10 @@ void init_paging(void)
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mmu_modify_or_del((uint64_t *)ppt_mmu_pml4_addr, round_pde_down(hv_hva),
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round_pde_up((uint64_t)&ld_text_end) - round_pde_down(hv_hva), 0UL,
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PAGE_NX, &ppt_mem_ops, MR_MODIFY);
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#if (SOS_VM_NUM == 1)
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mmu_modify_or_del((uint64_t *)ppt_mmu_pml4_addr, (uint64_t)get_reserve_sworld_memory_base(),
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TRUSTY_RAM_SIZE * (CONFIG_MAX_VM_NUM - 1U), PAGE_USER, 0UL, &ppt_mem_ops, MR_MODIFY);
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TRUSTY_RAM_SIZE * MAX_POST_VM_NUM, PAGE_USER, 0UL, &ppt_mem_ops, MR_MODIFY);
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#endif
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/* Enable paging */
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enable_paging();
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@ -10,7 +10,6 @@
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#include <mmu.h>
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#include <trusty.h>
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#include <vtd.h>
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#include <vm_configurations.h>
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#include <security.h>
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#include <vm.h>
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@ -78,37 +77,33 @@ const struct memory_ops ppt_mem_ops = {
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.recover_exe_right = nop_recover_exe_right,
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};
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static struct page sos_vm_pml4_pages[PML4_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
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static struct page sos_vm_pdpt_pages[PDPT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
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static struct page sos_vm_pd_pages[PD_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
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static struct page sos_vm_pt_pages[PT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
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static struct page sos_vm_pml4_pages[SOS_VM_NUM][PML4_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
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static struct page sos_vm_pdpt_pages[SOS_VM_NUM][PDPT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
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static struct page sos_vm_pd_pages[SOS_VM_NUM][PD_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
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static struct page sos_vm_pt_pages[SOS_VM_NUM][PT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))];
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/* uos_nworld_pml4_pages[i] is ...... of UOS i (whose vm_id = i +1) */
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static struct page uos_nworld_pml4_pages[CONFIG_MAX_VM_NUM - 1U][PML4_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page uos_nworld_pdpt_pages[CONFIG_MAX_VM_NUM - 1U][PDPT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page uos_nworld_pd_pages[CONFIG_MAX_VM_NUM - 1U][PD_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page uos_nworld_pt_pages[CONFIG_MAX_VM_NUM - 1U][PT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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/* pre_uos_nworld_pml4_pages */
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static struct page pre_uos_nworld_pml4_pages[PRE_VM_NUM][PML4_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page pre_uos_nworld_pdpt_pages[PRE_VM_NUM][PDPT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page pre_uos_nworld_pd_pages[PRE_VM_NUM][PD_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page pre_uos_nworld_pt_pages[PRE_VM_NUM][PT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page uos_sworld_pgtable_pages[CONFIG_MAX_VM_NUM - 1U][TRUSTY_PGTABLE_PAGE_NUM(TRUSTY_RAM_SIZE)];
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/* post_uos_nworld_pml4_pages */
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static struct page post_uos_nworld_pml4_pages[MAX_POST_VM_NUM][PML4_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page post_uos_nworld_pdpt_pages[MAX_POST_VM_NUM][PDPT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page post_uos_nworld_pd_pages[MAX_POST_VM_NUM][PD_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page post_uos_nworld_pt_pages[MAX_POST_VM_NUM][PT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))];
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static struct page post_uos_sworld_pgtable_pages[MAX_POST_VM_NUM][TRUSTY_PGTABLE_PAGE_NUM(TRUSTY_RAM_SIZE)];
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/* pre-assumption: TRUSTY_RAM_SIZE is 2M aligned */
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static struct page uos_sworld_memory[CONFIG_MAX_VM_NUM - 1U][TRUSTY_RAM_SIZE >> PAGE_SHIFT] __aligned(MEM_2M);
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static struct page post_uos_sworld_memory[MAX_POST_VM_NUM][TRUSTY_RAM_SIZE >> PAGE_SHIFT] __aligned(MEM_2M);
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/* ept: extended page table*/
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static union pgtable_pages_info ept_pages_info[CONFIG_MAX_VM_NUM] = {
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{
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.ept = {
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.top_address_space = EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE),
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.nworld_pml4_base = sos_vm_pml4_pages,
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.nworld_pdpt_base = sos_vm_pdpt_pages,
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.nworld_pd_base = sos_vm_pd_pages,
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.nworld_pt_base = sos_vm_pt_pages,
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},
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},
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};
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static union pgtable_pages_info ept_pages_info[CONFIG_MAX_VM_NUM];
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void *get_reserve_sworld_memory_base(void)
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{
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return uos_sworld_memory;
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return post_uos_sworld_memory;
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}
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static inline uint64_t ept_get_default_access_right(void)
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@ -188,15 +183,31 @@ static inline void ept_recover_exe_right(uint64_t *entry)
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void init_ept_mem_ops(struct memory_ops *mem_ops, uint16_t vm_id)
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{
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if (vm_id != 0U) {
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ept_pages_info[vm_id].ept.top_address_space = EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE);
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ept_pages_info[vm_id].ept.nworld_pml4_base = uos_nworld_pml4_pages[vm_id - 1U];
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ept_pages_info[vm_id].ept.nworld_pdpt_base = uos_nworld_pdpt_pages[vm_id - 1U];
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ept_pages_info[vm_id].ept.nworld_pd_base = uos_nworld_pd_pages[vm_id - 1U];
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ept_pages_info[vm_id].ept.nworld_pt_base = uos_nworld_pt_pages[vm_id - 1U];
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ept_pages_info[vm_id].ept.sworld_pgtable_base = uos_sworld_pgtable_pages[vm_id - 1U];
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ept_pages_info[vm_id].ept.sworld_memory_base = uos_sworld_memory[vm_id - 1U];
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struct acrn_vm *vm = get_vm_from_vmid(vm_id);
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if (is_sos_vm(vm)) {
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ept_pages_info[vm_id].ept.top_address_space = EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE);
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ept_pages_info[vm_id].ept.nworld_pml4_base = sos_vm_pml4_pages[0U];
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ept_pages_info[vm_id].ept.nworld_pdpt_base = sos_vm_pdpt_pages[0U];
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ept_pages_info[vm_id].ept.nworld_pd_base = sos_vm_pd_pages[0U];
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ept_pages_info[vm_id].ept.nworld_pt_base = sos_vm_pt_pages[0U];
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} else if (is_prelaunched_vm(vm)) {
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ept_pages_info[vm_id].ept.top_address_space = EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE);
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ept_pages_info[vm_id].ept.nworld_pml4_base = pre_uos_nworld_pml4_pages[vm_id];
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ept_pages_info[vm_id].ept.nworld_pdpt_base = pre_uos_nworld_pdpt_pages[vm_id];
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ept_pages_info[vm_id].ept.nworld_pd_base = pre_uos_nworld_pd_pages[vm_id];
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ept_pages_info[vm_id].ept.nworld_pt_base = pre_uos_nworld_pt_pages[vm_id];
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} else {
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uint16_t sos_vm_id = (get_sos_vm())->vm_id;
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uint16_t page_idx = vmid_2_rel_vmid(sos_vm_id, vm_id) - 1U;
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ept_pages_info[vm_id].ept.top_address_space = EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE);
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ept_pages_info[vm_id].ept.nworld_pml4_base = post_uos_nworld_pml4_pages[page_idx];
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ept_pages_info[vm_id].ept.nworld_pdpt_base = post_uos_nworld_pdpt_pages[page_idx];
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ept_pages_info[vm_id].ept.nworld_pd_base = post_uos_nworld_pd_pages[page_idx];
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ept_pages_info[vm_id].ept.nworld_pt_base = post_uos_nworld_pt_pages[page_idx];
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ept_pages_info[vm_id].ept.sworld_pgtable_base = post_uos_sworld_pgtable_pages[page_idx];
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ept_pages_info[vm_id].ept.sworld_memory_base = post_uos_sworld_memory[page_idx];
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mem_ops->get_sworld_memory_base = ept_get_sworld_memory_base;
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}
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mem_ops->info = &ept_pages_info[vm_id];
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@ -214,7 +225,7 @@ void init_ept_mem_ops(struct memory_ops *mem_ops, uint16_t vm_id)
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mem_ops->tweak_exe_right = ept_tweak_exe_right;
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mem_ops->recover_exe_right = ept_recover_exe_right;
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/* For RTVM, build 4KB page mapping in EPT */
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if (is_rt_vm(get_vm_from_vmid(vm_id))) {
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if (is_rt_vm(vm)) {
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mem_ops->large_page_enabled = false;
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}
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} else {
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@ -20,7 +20,7 @@
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#include <timer.h>
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#include <logmsg.h>
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#include <board.h>
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#include <vm_configurations.h>
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#include <vm_config.h>
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#include <pci.h>
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#define DBG_IOMMU 0
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@ -40,6 +40,7 @@
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#define MEM_1M (MEM_1K * 1024U)
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#define MEM_2M (MEM_1M * 2U)
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#define MEM_1G (MEM_1M * 1024U)
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#define MEM_2G (1024UL * 1024UL * 1024UL * 2UL)
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#ifndef ASSEMBLER
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@ -29,7 +29,9 @@
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* - Guest OS won't re-program device MMIO bars to the address not covered by
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* this EPT_ADDRESS_SPACE.
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*/
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#define EPT_ADDRESS_SPACE(size) (((size) != 0UL) ? ((size) + PLATFORM_LO_MMIO_SIZE + PLATFORM_HI_MMIO_SIZE) : 0UL)
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#define EPT_ADDRESS_SPACE(size) ((size > MEM_2G) ? \
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((size) + PLATFORM_LO_MMIO_SIZE + PLATFORM_HI_MMIO_SIZE) \
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: (MEM_2G + PLATFORM_LO_MMIO_SIZE + PLATFORM_HI_MMIO_SIZE))
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#define TRUSTY_PML4_PAGE_NUM(size) (1UL)
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#define TRUSTY_PDPT_PAGE_NUM(size) (1UL)
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@ -14,6 +14,8 @@
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#include <vm_configurations.h>
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#include <sgx.h>
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#define CONFIG_MAX_VM_NUM (PRE_VM_NUM + SOS_VM_NUM + MAX_POST_VM_NUM)
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#define AFFINITY_CPU(n) (1U << (n))
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#define MAX_VCPUS_PER_VM MAX_PCPU_NUM
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#define MAX_VUART_NUM_PER_VM 2U
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@ -11,7 +11,6 @@
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#include <vcpu.h>
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#include <vm_config.h>
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#include <vm_configurations.h>
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#define MAX_MSR_LIST_NUM 15U
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#define MAX_PROFILING_MSR_STORE_NUM 1
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@ -13,7 +13,13 @@
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#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
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GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
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#define CONFIG_MAX_VM_NUM (3U + CONFIG_MAX_KATA_VM_NUM)
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/* SOS_VM_NUM can only be 0U or 1U;
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* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
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* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
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*/
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#define PRE_VM_NUM 1U
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#define SOS_VM_NUM 1U
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#define MAX_POST_VM_NUM 1U
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#define VM0_CONFIG_VCPU_AFFINITY {AFFINITY_CPU(3U)}
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#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
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@ -9,7 +9,13 @@
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#include <misc_cfg.h>
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#define CONFIG_MAX_VM_NUM (3U + CONFIG_MAX_KATA_VM_NUM)
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/* SOS_VM_NUM can only be 0U or 1U;
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* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
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* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
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*/
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#define PRE_VM_NUM 0U
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#define SOS_VM_NUM 1U
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#define MAX_POST_VM_NUM 2U
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/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
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#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
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@ -13,7 +13,13 @@
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/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
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#define DM_OWNED_GUEST_FLAG_MASK 0UL
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#define CONFIG_MAX_VM_NUM 2U
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/* SOS_VM_NUM can only be 0U or 1U;
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* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
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* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
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*/
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#define PRE_VM_NUM 2U
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#define SOS_VM_NUM 0U
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#define MAX_POST_VM_NUM 0U
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/* The VM CONFIGs like:
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* VMX_CONFIG_VCPU_AFFINITY
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@ -9,7 +9,13 @@
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#include <misc_cfg.h>
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#define CONFIG_MAX_VM_NUM (2U + CONFIG_MAX_KATA_VM_NUM)
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/* SOS_VM_NUM can only be 0U or 1U;
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* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
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* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
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*/
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#define PRE_VM_NUM 0U
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#define SOS_VM_NUM 1U
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#define MAX_POST_VM_NUM 2U /* including 1 KATA VM */
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/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
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#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
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@ -9,7 +9,13 @@
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#include <misc_cfg.h>
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#define CONFIG_MAX_VM_NUM (4U + CONFIG_MAX_KATA_VM_NUM)
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/* SOS_VM_NUM can only be 0U or 1U;
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* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
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* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
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*/
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#define PRE_VM_NUM 0U
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#define SOS_VM_NUM 1U
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#define MAX_POST_VM_NUM 3U
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/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
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#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
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