github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-03 12:49:45 +00:00
Code Issues Projects Releases Wiki Activity

config_tools: update files under generic_code directory

Browse Source 
update files under generic_code directory with the latest code.

Tracked-On: #6663
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
This commit is contained in:
Kunhui-Li 2021-11-16 17:50:25 +08:00 committed by wenlingz
parent 960238cdcb
commit 4ee4835d47
39 changed files with 800 additions and 800 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

BIN
misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/dsdt.aml Normal file
View File

Binary file not shown.

25
misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/dsdt.asl
View File

@ -1,25 +0,0 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190703 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Original Table Header:
* Signature "DSDT"
* Length 0x00000051 (81)
* Revision 0x03
* Checksum 0xF0
* OEM ID "ACRN "
* OEM Table ID "ACRNDSDT"
* OEM Revision 0x00000001 (1)
* Compiler ID "INTL"
* Compiler Version 0x20190703 (538511107)
*/
DefinitionBlock ("", "DSDT", 3, "ACRN ", "ACRNDSDT", 0x00000001)
{
Name (_S5, Package ()
{
0x05,
Zero,
})
}

2
misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/facp.asl
View File

@ -19,7 +19,7 @@
[0004] Asl Compiler Revision : 20190703
[0004] FACS Address : 00000000
[0004] DSDT Address : 7FF00240
[0004] DSDT Address : 7FE00240
[0001] Model : 00
[0001] PM Profile : 00 [Unspecified]
[0002] SCI Interrupt : 0000

2
misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/rsdp.asl
View File

@ -11,6 +11,6 @@
[0001] Revision : 02
[0004] RSDT Address : 0000000000000000
[0004] Length : 00000024
[0008] XSDT Address : 000000007FF00080
[0008] XSDT Address : 000000007FE00080
[0001] Extended Checksum : DC
[0003] Reserved : 000000

6
misc/config_tools/data/generic_board/generic_code/hybrid/ACPI_VM0/xsdt.asl
View File

@ -18,6 +18,6 @@
[0004] Asl Compiler ID : "INTL"
[0004] Asl Compiler Revision : 20190703
[0008] ACPI Table Address 0 : 000000007FF00100
[0008] ACPI Table Address 1 : 000000007FF00440
[0008] ACPI Table Address 2 : 000000007FF00480
[0008] ACPI Table Address 0 : 000000007FE00100
[0008] ACPI Table Address 1 : 000000007FE00BC0
[0008] ACPI Table Address 2 : 000000007FE00C00

3
misc/config_tools/data/generic_board/generic_code/hybrid/generic_board.config
View File

@ -1,8 +1,7 @@
# Board defconfig generated by acrn-config tool
CONFIG_BOARD="generic_board"
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x3800000
CONFIG_HV_RAM_START=0x00400000
CONFIG_PLATFORM_RAM_SIZE=0x400000000
CONFIG_LOW_RAM_SIZE=0x00010000
CONFIG_STACK_SIZE=0x2000

3
misc/config_tools/data/generic_board/generic_code/hybrid/ivshmem_cfg.h
View File

@ -1,8 +1,9 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IVSHMEM_CFG_H
#define IVSHMEM_CFG_H

84
misc/config_tools/data/generic_board/generic_code/hybrid/misc_cfg.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,69 +7,27 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define SOS_ROOTFS "root=/dev/nvme0n1p3 "
#define SOS_CONSOLE "console=ttyS0 "
#define SOS_COM1_BASE 0x3F8U
#define SOS_COM1_IRQ 4U
#define SOS_COM2_BASE 0x2F8U
#define SOS_COM2_IRQ 3U
#define SOS_BOOTARGS_DIFF "rw " \
"rootwait " \
"console=tty0 " \
"consoleblank=0 " \
"no_timer_check " \
"quiet " \
"loglevel=3 " \
"i915.nuclear_pageflip=1 " \
"swiotlb=131072 " \
"maxcpus=3"
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U))
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U))
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U))
#define SERVICE_VM_ROOTFS "root=/dev/nvme0n1p3 "
#define SERVICE_VM_OS_CONSOLE "console=ttyS0 "
#define SERVICE_VM_BOOTARGS_DIFF \
"rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3 i915.nuclear_pageflip=1 " \
"swiotlb=131072 maxcpus=3 hugepagesz=1G hugepages=8 "
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U))
#define SERVICE_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U))
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U))
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#define CLOS_MASK_0 0xfffffU
#define CLOS_MASK_1 0xfffffU
#define CLOS_MASK_2 0xfffffU
#define CLOS_MASK_3 0xfffffU
#define CLOS_MASK_4 0xfffffU
#define CLOS_MASK_5 0xfffffU
#define CLOS_MASK_6 0xfffffU
#define CLOS_MASK_7 0xfffffU
#define VM0_VCPU_CLOS {0U}
#define VM1_VCPU_CLOS {0U, 0U, 0U}
#define VM2_VCPU_CLOS {0U}
#define VM3_VCPU_CLOS {0U}
#define HV_SUPPORTED_MAX_CLOS 0U
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#define CLOS_MASK_0 0xfffffU
#define CLOS_MASK_1 0xfffffU
#define CLOS_MASK_2 0xfffffU
#define CLOS_MASK_3 0xfffffU
#define CLOS_MASK_4 0xfffffU
#define CLOS_MASK_5 0xfffffU
#define CLOS_MASK_6 0xfffffU
#define CLOS_MASK_7 0xfffffU
#endif
#define VM0_PT_INTX_NUM 0U
#endif /* MISC_CFG_H */

10
misc/config_tools/data/generic_board/generic_code/hybrid/pci_dev.c
View File

@ -1,14 +1,14 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm/vm_config.h>
#include <pci_devices.h>
#include <vpci.h>
#include <vbar_base.h>
#include <asm/mmu.h>
#include <asm/page.h>
struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
#include <vmcs9900.h>
#include <ivshmem_cfg.h>
#define INVALID_PCI_BASE 0U
struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM] = {};

6
misc/config_tools/data/generic_board/generic_code/hybrid/pt_intx.c
View File

@ -1,10 +1,8 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm/vm_config.h>
struct pt_intx_config vm0_pt_intx[1U];
struct pt_intx_config vm0_pt_intx[1U] = {};

46
misc/config_tools/data/generic_board/generic_code/hybrid/vbar_base.h
View File

@ -7,46 +7,42 @@
#ifndef VBAR_BASE_H_
#define VBAR_BASE_H_
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x0UL, \
.vbar_base[2] = HI_MMIO_START + 0x10000000UL
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR \
.vbar_base[0] = HI_MMIO_START + 0x0UL, .vbar_base[2] = HI_MMIO_START + 0x10000000UL
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20000000UL
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20000000UL
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20010000UL
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20010000UL
#define USB_CONTROLLER_1_VBAR .vbar_base[0] = HI_MMIO_START + 0x20040000UL, \
.vbar_base[2] = HI_MMIO_START + 0x20080000UL
#define USB_CONTROLLER_1_VBAR .vbar_base[0] = HI_MMIO_START + 0x20040000UL, .vbar_base[2] = HI_MMIO_START + 0x20080000UL
#define USB_CONTROLLER_2_VBAR .vbar_base[0] = HI_MMIO_START + 0x200c0000UL, \
.vbar_base[2] = HI_MMIO_START + 0x20100000UL
#define USB_CONTROLLER_2_VBAR .vbar_base[0] = HI_MMIO_START + 0x200c0000UL, .vbar_base[2] = HI_MMIO_START + 0x20100000UL
#define USB_CONTROLLER_3_VBAR .vbar_base[0] = HI_MMIO_START + 0x20110000UL
#define USB_CONTROLLER_3_VBAR .vbar_base[0] = HI_MMIO_START + 0x20110000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20120000UL, \
.vbar_base[2] = HI_MMIO_START + 0x20124000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20120000UL, .vbar_base[2] = HI_MMIO_START + 0x20124000UL
#define NETWORK_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20128000UL
#define NETWORK_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20128000UL
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012c000UL
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012c000UL
#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012d000UL
#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012d000UL
#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = HI_MMIO_START + 0x20301000UL
#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = HI_MMIO_START + 0x20301000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012e000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012e000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20130000UL, \
.vbar_base[1] = HI_MMIO_START + 0x20132000UL, \
.vbar_base[5] = HI_MMIO_START + 0x20132800UL
#define SATA_CONTROLLER_0_VBAR \
.vbar_base[0] = HI_MMIO_START + 0x20130000UL, .vbar_base[1] = HI_MMIO_START + 0x20132000UL, \
.vbar_base[5] = HI_MMIO_START + 0x20132800UL
#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20134000UL, \
.vbar_base[4] = HI_MMIO_START + 0x20200000UL
#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20134000UL, .vbar_base[4] = HI_MMIO_START + 0x20200000UL
#define SMBUS_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20300000UL
#define SMBUS_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20300000UL
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20304000UL
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20304000UL
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20400000UL, \
.vbar_base[3] = HI_MMIO_START + 0x20500000UL
#define ETHERNET_CONTROLLER_0_VBAR \
.vbar_base[0] = HI_MMIO_START + 0x20400000UL, .vbar_base[3] = HI_MMIO_START + 0x20500000UL
#endif /* VBAR_BASE_H_ */

297
misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.c
View File

@ -1,136 +1,213 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm/vm_config.h>
#include <vuart.h>
#include <asm/pci_dev.h>
extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
#include <asm/pgtable.h>
#include <schedule.h>
extern struct pt_intx_config vm0_pt_intx[1U];
extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
{ /* VM0 */
CONFIG_SAFETY_VM(1),
.name = "ACRN PRE-LAUNCHED VM0",
{
/* Static configured VM0 */
CONFIG_SAFETY_VM,
.name = "SAFETY_VM0",
.vm_prio = PRIO_LOW,
.guest_flags = GUEST_FLAG_STATIC_VM,
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
.guest_flags = 0UL,
#ifdef CONFIG_RDT_ENABLED
.clos = VM0_VCPU_CLOS,
#endif
.memory = {
.start_hpa = VM0_CONFIG_MEM_START_HPA,
.size = VM0_CONFIG_MEM_SIZE,
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
},
.os_config = {
.name = "Zephyr",
.kernel_type = KERNEL_ZEPHYR,
.kernel_mod_tag = "Zephyr_RawImage",
.kernel_load_addr = 0x8000,
.kernel_entry_addr = 0x8000,
},
.acpi_config = {
.acpi_mod_tag = "ACPI_VM0",
},
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM2_BASE,
.irq = COM2_IRQ,
.t_vuart.vm_id = 1U,
.t_vuart.vuart_id = 1U,
},
.memory =
{
.start_hpa = VM0_CONFIG_MEM_START_HPA,
.size = VM0_CONFIG_MEM_SIZE,
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
},
.os_config =
{
.name = "Zephyr",
.kernel_type = KERNEL_ELF,
.kernel_mod_tag = "Zephyr_ElfImage",
.ramdisk_mod_tag = "",
},
.acpi_config =
{
.acpi_mod_tag = "ACPI_VM0",
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x2F8U,
.irq = 3U,
.t_vuart.vm_id = 1U,
.t_vuart.vuart_id = 1U,
},
#ifdef VM0_PASSTHROUGH_TPM
.pt_tpm2 = true,
.mmiodevs[0] = {
.user_vm_pa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
.service_vm_pa = VM0_TPM_BUFFER_BASE_ADDR,
.size = VM0_TPM_BUFFER_SIZE,
},
.mmiodevs[0] =
{
.name = "tpm2",
.res[0] =
{
.user_vm_pa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
.host_pa = VM0_TPM_BUFFER_BASE_ADDR,
.size = VM0_TPM_BUFFER_SIZE,
.mem_type = EPT_UNCACHED,
},
.res[1] =
{
.user_vm_pa = VM0_TPM_EVENTLOG_BASE_ADDR,
.host_pa = VM0_TPM_EVENTLOG_BASE_ADDR_HPA,
.size = VM0_TPM_EVENTLOG_SIZE,
.mem_type = EPT_WB,
},
},
#endif
#ifdef P2SB_BAR_ADDR
.pt_p2sb_bar = true,
.mmiodevs[0] = {
.user_vm_pa = P2SB_BAR_ADDR_GPA,
.service_vm_pa = P2SB_BAR_ADDR,
.size = P2SB_BAR_SIZE,
},
.mmiodevs[0] =
{
.res[0] =
{
.user_vm_pa = P2SB_BAR_ADDR_GPA,
.host_pa = P2SB_BAR_ADDR,
.size = P2SB_BAR_SIZE,
},
},
#endif
.pt_intx_num = VM0_PT_INTX_NUM,
.pt_intx = &vm0_pt_intx[0U],
.pt_intx_num = 0,
.pt_intx = vm0_pt_intx,
},
{ /* VM1 */
CONFIG_SOS_VM,
.name = "ACRN SOS VM",
/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
.guest_flags = 0UL,
#ifdef CONFIG_RDT_ENABLED
.clos = VM1_VCPU_CLOS,
#endif
.cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY,
.memory = {
.start_hpa = 0UL,
},
.os_config = {
.name = "ACRN Service OS",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = SOS_VM_BOOTARGS,
},
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = SOS_COM1_BASE,
.irq = SOS_COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = SOS_COM2_BASE,
.irq = SOS_COM2_IRQ,
.t_vuart.vm_id = 0U,
.t_vuart.vuart_id = 1U,
},
{
/* Static configured VM1 */
CONFIG_SERVICE_VM,
.name = "ACRN_Service_VM",
/* Allow Service VM to reboot the system since it is the highest priority VM. */
.vm_prio = PRIO_LOW,
.guest_flags = GUEST_FLAG_STATIC_VM,
.cpu_affinity = SERVICE_VM_CONFIG_CPU_AFFINITY,
.memory =
{
.start_hpa = 0UL,
},
.os_config =
{
.name = "ACRN Service OS",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.ramdisk_mod_tag = "",
.bootargs = SERVICE_VM_OS_BOOTARGS,
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x2F8U,
.irq = 3U,
.t_vuart.vm_id = 0U,
.t_vuart.vuart_id = 1U,
},
.pci_dev_num = 0U,
.pci_devs = sos_pci_devs,
},
{ /* VM2 */
CONFIG_POST_STD_VM(1),
#ifdef CONFIG_RDT_ENABLED
.clos = VM2_VCPU_CLOS,
#endif
{
/* Static configured VM2 */
CONFIG_POST_STD_VM,
.name = "POST_STD_VM1",
.vm_prio = PRIO_LOW,
.guest_flags = GUEST_FLAG_STATIC_VM,
.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
},
},
{ /* VM3 */
CONFIG_POST_STD_VM(2),
#ifdef CONFIG_RDT_ENABLED
.clos = VM3_VCPU_CLOS,
#endif
{
/* Static configured VM3 */
CONFIG_POST_STD_VM,
.name = "POST_STD_VM2",
.vm_prio = PRIO_LOW,
.guest_flags = GUEST_FLAG_STATIC_VM,
.cpu_affinity = VM3_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
},
},
{
/* Dynamic configured VM4 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM5 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM6 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM7 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM8 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM9 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM10 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM11 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM12 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM13 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM14 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM15 */
CONFIG_POST_STD_VM,
}
};

42
misc/config_tools/data/generic_board/generic_code/hybrid/vm_configurations.h
View File

@ -1,36 +1,28 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VM_CONFIGURATIONS_H
#define VM_CONFIGURATIONS_H
#include <misc_cfg.h>
#include <pci_devices.h>
/* SOS_VM_NUM can only be 0U or 1U;
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
*/
#define PRE_VM_NUM 1U
#define SOS_VM_NUM 1U
#define MAX_POST_VM_NUM 2U
#define CONFIG_MAX_KATA_VM_NUM 0U
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
/* SOS_VM == VM1 */
#define SOS_VM_BOOTARGS SOS_ROOTFS \
SOS_CONSOLE \
SOS_IDLE \
SOS_BOOTARGS_DIFF
/* SERVICE_VM_NUM can only be 0 or 1; When SERVICE_VM_NUM is 1, MAX_POST_VM_NUM must be 0 too. */
#define PRE_VM_NUM 1U
#define SERVICE_VM_NUM 1U
#define MAX_POST_VM_NUM 14U
#define CONFIG_MAX_VM_NUM 16U
/* Bitmask of guest flags that can be programmed by device model. Other bits are set by hypervisor only. */
#define DM_OWNED_GUEST_FLAG_MASK \
(GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT | \
GUEST_FLAG_IO_COMPLETION_POLLING | GUEST_FLAG_SECURITY_VM)
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
/* SERVICE_VM == VM1 */
#define SERVICE_VM_OS_BOOTARGS SERVICE_VM_ROOTFS SERVICE_VM_OS_CONSOLE SERVICE_VM_IDLE SERVICE_VM_BOOTARGS_DIFF
#endif /* VM_CONFIGURATIONS_H */

BIN
misc/config_tools/data/generic_board/generic_code/partitioned/ACPI_VM0/dsdt.aml Normal file
View File

Binary file not shown.

25
misc/config_tools/data/generic_board/generic_code/partitioned/ACPI_VM0/dsdt.asl
View File

@ -1,25 +0,0 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190703 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Original Table Header:
* Signature "DSDT"
* Length 0x00000051 (81)
* Revision 0x03
* Checksum 0xF0
* OEM ID "ACRN "
* OEM Table ID "ACRNDSDT"
* OEM Revision 0x00000001 (1)
* Compiler ID "INTL"
* Compiler Version 0x20190703 (538511107)
*/
DefinitionBlock ("", "DSDT", 3, "ACRN ", "ACRNDSDT", 0x00000001)
{
Name (_S5, Package ()
{
0x05,
Zero,
})
}

2
misc/config_tools/data/generic_board/generic_code/partitioned/ACPI_VM0/facp.asl
View File

@ -19,7 +19,7 @@
[0004] Asl Compiler Revision : 20190703
[0004] FACS Address : 00000000
[0004] DSDT Address : 7FF00240
[0004] DSDT Address : 7FE00240
[0001] Model : 00
[0001] PM Profile : 00 [Unspecified]
[0002] SCI Interrupt : 0000

2
misc/config_tools/data/generic_board/generic_code/partitioned/ACPI_VM0/rsdp.asl
View File

@ -11,6 +11,6 @@
[0001] Revision : 02
[0004] RSDT Address : 0000000000000000
[0004] Length : 00000024
[0008] XSDT Address : 000000007FF00080
[0008] XSDT Address : 000000007FE00080
[0001] Extended Checksum : DC
[0003] Reserved : 000000

6
misc/config_tools/data/generic_board/generic_code/partitioned/ACPI_VM0/xsdt.asl
View File

@ -18,6 +18,6 @@
[0004] Asl Compiler ID : "INTL"
[0004] Asl Compiler Revision : 20190703
[0008] ACPI Table Address 0 : 000000007FF00100
[0008] ACPI Table Address 1 : 000000007FF00440
[0008] ACPI Table Address 2 : 000000007FF00480
[0008] ACPI Table Address 0 : 000000007FE00100
[0008] ACPI Table Address 1 : 000000007FE00BC0
[0008] ACPI Table Address 2 : 000000007FE00C00

BIN
misc/config_tools/data/generic_board/generic_code/partitioned/ACPI_VM1/dsdt.aml Normal file
View File

Binary file not shown.

25
misc/config_tools/data/generic_board/generic_code/partitioned/ACPI_VM1/dsdt.asl
View File

@ -1,25 +0,0 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20190703 (64-bit version)
* Copyright (c) 2000 - 2019 Intel Corporation
*
* Original Table Header:
* Signature "DSDT"
* Length 0x00000051 (81)
* Revision 0x03
* Checksum 0xF0
* OEM ID "ACRN "
* OEM Table ID "ACRNDSDT"
* OEM Revision 0x00000001 (1)
* Compiler ID "INTL"
* Compiler Version 0x20190703 (538511107)
*/
DefinitionBlock ("", "DSDT", 3, "ACRN ", "ACRNDSDT", 0x00000001)
{
Name (_S5, Package ()
{
0x05,
Zero,
})
}

2
misc/config_tools/data/generic_board/generic_code/partitioned/ACPI_VM1/facp.asl
View File

@ -19,7 +19,7 @@
[0004] Asl Compiler Revision : 20190703
[0004] FACS Address : 00000000
[0004] DSDT Address : 7FF00240
[0004] DSDT Address : 7FE00240
[0001] Model : 00
[0001] PM Profile : 00 [Unspecified]
[0002] SCI Interrupt : 0000

2
misc/config_tools/data/generic_board/generic_code/partitioned/ACPI_VM1/rsdp.asl
View File

@ -11,6 +11,6 @@
[0001] Revision : 02
[0004] RSDT Address : 0000000000000000
[0004] Length : 00000024
[0008] XSDT Address : 000000007FF00080
[0008] XSDT Address : 000000007FE00080
[0001] Extended Checksum : DC
[0003] Reserved : 000000

6
misc/config_tools/data/generic_board/generic_code/partitioned/ACPI_VM1/xsdt.asl
View File

@ -18,6 +18,6 @@
[0004] Asl Compiler ID : "INTL"
[0004] Asl Compiler Revision : 20190703
[0008] ACPI Table Address 0 : 000000007FF00100
[0008] ACPI Table Address 1 : 000000007FF00440
[0008] ACPI Table Address 2 : 000000007FF00480
[0008] ACPI Table Address 0 : 000000007FE00100
[0008] ACPI Table Address 1 : 000000007FE00BC0
[0008] ACPI Table Address 2 : 000000007FE00C00

3
misc/config_tools/data/generic_board/generic_code/partitioned/generic_board.config
View File

@ -1,8 +1,7 @@
# Board defconfig generated by acrn-config tool
CONFIG_BOARD="generic_board"
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x1800000
CONFIG_HV_RAM_START=0x00400000
CONFIG_PLATFORM_RAM_SIZE=0x400000000
CONFIG_LOW_RAM_SIZE=0x00010000
CONFIG_STACK_SIZE=0x2000

3
misc/config_tools/data/generic_board/generic_code/partitioned/ivshmem_cfg.h
View File

@ -1,8 +1,9 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IVSHMEM_CFG_H
#define IVSHMEM_CFG_H

71
misc/config_tools/data/generic_board/generic_code/partitioned/misc_cfg.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,56 +7,29 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
#define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#define CLOS_MASK_0 0xfffffU
#define CLOS_MASK_1 0xfffffU
#define CLOS_MASK_2 0xfffffU
#define CLOS_MASK_3 0xfffffU
#define CLOS_MASK_4 0xfffffU
#define CLOS_MASK_5 0xfffffU
#define CLOS_MASK_6 0xfffffU
#define CLOS_MASK_7 0xfffffU
#define VM0_VCPU_CLOS {0U, 0U}
#define VM1_VCPU_CLOS {0U, 0U}
#define HV_SUPPORTED_MAX_CLOS 0U
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#define CLOS_MASK_0 0xfffffU
#define CLOS_MASK_1 0xfffffU
#define CLOS_MASK_2 0xfffffU
#define CLOS_MASK_3 0xfffffU
#define CLOS_MASK_4 0xfffffU
#define CLOS_MASK_5 0xfffffU
#define CLOS_MASK_6 0xfffffU
#define CLOS_MASK_7 0xfffffU
#endif
#define VM0_CONFIG_PCI_DEV_NUM 3U
#define VM1_CONFIG_PCI_DEV_NUM 2U
#define VM0_CONFIG_PCI_DEV_NUM 3U
#define VM1_CONFIG_PCI_DEV_NUM 2U
#define VM0_BOOT_ARGS "rw rootwait root=/dev/sda3 console=ttyS0 \
noxsave nohpet no_timer_check ignore_loglevel \
log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi"
#define VM1_BOOT_ARGS "rw rootwait root=/dev/sda2 console=ttyS0 \
noxsave nohpet no_timer_check ignore_loglevel \
log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi"
#define VM0_PT_INTX_NUM 0U
#define VM0_BOOT_ARGS \
"rw rootwait root=/dev/sda3 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel log_buf_len=16M " \
"consoleblank=0 tsc=reliable reboot=acpi "
#define VM1_BOOT_ARGS \
"rw rootwait root=/dev/sda2 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel log_buf_len=16M " \
"consoleblank=0 tsc=reliable reboot=acpi "
#endif /* MISC_CFG_H */

75
misc/config_tools/data/generic_board/generic_code/partitioned/pci_dev.c
View File

@ -1,54 +1,81 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm/vm_config.h>
#include <pci_devices.h>
#include <vpci.h>
#include <vbar_base.h>
#include <asm/mmu.h>
#include <asm/page.h>
/*
* TODO: remove PTDEV macro and add DEV_PRIVINFO macro to initialize pbdf for
* passthrough device configuration and shm_name for ivshmem device configuration.
*/
#define PTDEV(PCI_DEV) PCI_DEV, PCI_DEV##_VBAR
/*
* TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops
* to simplify the code.
*/
#include <vmcs9900.h>
#include <ivshmem_cfg.h>
#define INVALID_PCI_BASE 0U
struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
{
.emu_type = PCI_DEV_TYPE_HVEMUL,
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
.vdev_ops = &vhostbridge_ops,
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
},
{
.emu_type = PCI_DEV_TYPE_PTDEV,
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
PTDEV(SATA_CONTROLLER_0),
.vbdf.bits =
{
.b = 0x00U,
.d = 0x01U,
.f = 0x00U,
},
.pbdf.bits =
{
.b = 0x00U,
.d = 0x17U,
.f = 0x00U,
},
.vbar_base[0] = 0x80104000UL,
.vbar_base[5] = 0x80106000UL,
.vbar_base[1] = 0x80107000UL,
.vbar_base[4] = 0x3060UL,
.vbar_base[3] = 0x3080UL,
.vbar_base[2] = 0x3090UL,
},
{
.emu_type = PCI_DEV_TYPE_PTDEV,
.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
PTDEV(ETHERNET_CONTROLLER_0),
.vbdf.bits =
{
.b = 0x00U,
.d = 0x02U,
.f = 0x00U,
},
.pbdf.bits =
{
.b = 0x58U,
.d = 0x00U,
.f = 0x00U,
},
.vbar_base[0] = 0x80000000UL,
.vbar_base[3] = 0x80100000UL,
},
};
struct acrn_vm_pci_dev_config vm1_pci_devs[VM1_CONFIG_PCI_DEV_NUM] = {
{
.emu_type = PCI_DEV_TYPE_HVEMUL,
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
.vdev_ops = &vhostbridge_ops,
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
},
{
.emu_type = PCI_DEV_TYPE_PTDEV,
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x00U},
PTDEV(USB_CONTROLLER_3),
.vbdf.bits =
{
.b = 0x00U,
.d = 0x01U,
.f = 0x00U,
},
.pbdf.bits =
{
.b = 0x00U,
.d = 0x14U,
.f = 0x00U,
},
.vbar_base[0] = 0x80000000UL,
},
};

6
misc/config_tools/data/generic_board/generic_code/partitioned/pt_intx.c
View File

@ -1,10 +1,10 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm/vm_config.h>
struct pt_intx_config vm0_pt_intx[1U] = {};
struct pt_intx_config vm0_pt_intx[1U];
struct pt_intx_config vm1_pt_intx[1U] = {};

46
misc/config_tools/data/generic_board/generic_code/partitioned/vbar_base.h
View File

@ -7,46 +7,42 @@
#ifndef VBAR_BASE_H_
#define VBAR_BASE_H_
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x0UL, \
.vbar_base[2] = HI_MMIO_START + 0x10000000UL
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR \
.vbar_base[0] = HI_MMIO_START + 0x0UL, .vbar_base[2] = HI_MMIO_START + 0x10000000UL
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20000000UL
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20000000UL
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20010000UL
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20010000UL
#define USB_CONTROLLER_1_VBAR .vbar_base[0] = HI_MMIO_START + 0x20040000UL, \
.vbar_base[2] = HI_MMIO_START + 0x20080000UL
#define USB_CONTROLLER_1_VBAR .vbar_base[0] = HI_MMIO_START + 0x20040000UL, .vbar_base[2] = HI_MMIO_START + 0x20080000UL
#define USB_CONTROLLER_2_VBAR .vbar_base[0] = HI_MMIO_START + 0x200c0000UL, \
.vbar_base[2] = HI_MMIO_START + 0x20100000UL
#define USB_CONTROLLER_2_VBAR .vbar_base[0] = HI_MMIO_START + 0x200c0000UL, .vbar_base[2] = HI_MMIO_START + 0x20100000UL
#define USB_CONTROLLER_3_VBAR .vbar_base[0] = HI_MMIO_START + 0x20110000UL
#define USB_CONTROLLER_3_VBAR .vbar_base[0] = HI_MMIO_START + 0x20110000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20120000UL, \
.vbar_base[2] = HI_MMIO_START + 0x20124000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20120000UL, .vbar_base[2] = HI_MMIO_START + 0x20124000UL
#define NETWORK_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20128000UL
#define NETWORK_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20128000UL
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012c000UL
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012c000UL
#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012d000UL
#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012d000UL
#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = HI_MMIO_START + 0x20301000UL
#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = HI_MMIO_START + 0x20301000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012e000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012e000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20130000UL, \
.vbar_base[1] = HI_MMIO_START + 0x20132000UL, \
.vbar_base[5] = HI_MMIO_START + 0x20132800UL
#define SATA_CONTROLLER_0_VBAR \
.vbar_base[0] = HI_MMIO_START + 0x20130000UL, .vbar_base[1] = HI_MMIO_START + 0x20132000UL, \
.vbar_base[5] = HI_MMIO_START + 0x20132800UL
#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20134000UL, \
.vbar_base[4] = HI_MMIO_START + 0x20200000UL
#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20134000UL, .vbar_base[4] = HI_MMIO_START + 0x20200000UL
#define SMBUS_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20300000UL
#define SMBUS_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20300000UL
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20304000UL
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20304000UL
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20400000UL, \
.vbar_base[3] = HI_MMIO_START + 0x20500000UL
#define ETHERNET_CONTROLLER_0_VBAR \
.vbar_base[0] = HI_MMIO_START + 0x20400000UL, .vbar_base[3] = HI_MMIO_START + 0x20500000UL
#endif /* VBAR_BASE_H_ */

256
misc/config_tools/data/generic_board/generic_code/partitioned/vm_configurations.c
View File

@ -1,110 +1,198 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm/vm_config.h>
#include <vuart.h>
#include <asm/pci_dev.h>
#include <asm/pgtable.h>
#include <schedule.h>
extern struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM];
extern struct acrn_vm_pci_dev_config vm1_pci_devs[VM1_CONFIG_PCI_DEV_NUM];
extern struct pt_intx_config vm0_pt_intx[1U];
extern struct acrn_vm_pci_dev_config vm1_pci_devs[VM1_CONFIG_PCI_DEV_NUM];
extern struct pt_intx_config vm1_pt_intx[1U];
struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
{ /* VM0 */
CONFIG_PRE_STD_VM(1),
.name = "ACRN PRE-LAUNCHED VM0",
{
/* Static configured VM0 */
CONFIG_PRE_STD_VM,
.name = "PRE_STD_VM0",
.vm_prio = PRIO_LOW,
.guest_flags = GUEST_FLAG_STATIC_VM,
.cpu_affinity = VM0_CONFIG_CPU_AFFINITY,
.guest_flags = 0UL,
#ifdef CONFIG_RDT_ENABLED
.clos = VM0_VCPU_CLOS,
#endif
.memory = {
.start_hpa = VM0_CONFIG_MEM_START_HPA,
.size = VM0_CONFIG_MEM_SIZE,
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
},
.os_config = {
.name = "YOCTO",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = VM0_BOOT_ARGS,
},
.acpi_config = {
.acpi_mod_tag = "ACPI_VM0",
},
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM2_BASE,
.irq = COM2_IRQ,
.t_vuart.vm_id = 1U,
.t_vuart.vuart_id = 1U,
},
.memory =
{
.start_hpa = VM0_CONFIG_MEM_START_HPA,
.size = VM0_CONFIG_MEM_SIZE,
.start_hpa2 = VM0_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM0_CONFIG_MEM_SIZE_HPA2,
},
.os_config =
{
.name = "YOCTO",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.ramdisk_mod_tag = "",
.bootargs = VM0_BOOT_ARGS,
},
.acpi_config =
{
.acpi_mod_tag = "ACPI_VM0",
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x2F8U,
.irq = 3U,
.t_vuart.vm_id = 1U,
.t_vuart.vuart_id = 1U,
},
.pci_dev_num = VM0_CONFIG_PCI_DEV_NUM,
.pci_devs = vm0_pci_devs,
#ifdef VM0_PASSTHROUGH_TPM
.pt_tpm2 = true,
.mmiodevs[0] = {
.user_vm_pa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
.service_vm_pa = VM0_TPM_BUFFER_BASE_ADDR,
.size = VM0_TPM_BUFFER_SIZE,
},
.mmiodevs[0] =
{
.name = "tpm2",
.res[0] =
{
.user_vm_pa = VM0_TPM_BUFFER_BASE_ADDR_GPA,
.host_pa = VM0_TPM_BUFFER_BASE_ADDR,
.size = VM0_TPM_BUFFER_SIZE,
.mem_type = EPT_UNCACHED,
},
.res[1] =
{
.user_vm_pa = VM0_TPM_EVENTLOG_BASE_ADDR,
.host_pa = VM0_TPM_EVENTLOG_BASE_ADDR_HPA,
.size = VM0_TPM_EVENTLOG_SIZE,
.mem_type = EPT_WB,
},
},
#endif
#ifdef P2SB_BAR_ADDR
.pt_p2sb_bar = true,
.mmiodevs[0] = {
.user_vm_pa = P2SB_BAR_ADDR_GPA,
.service_vm_pa = P2SB_BAR_ADDR,
.size = P2SB_BAR_SIZE,
},
.mmiodevs[0] =
{
.res[0] =
{
.user_vm_pa = P2SB_BAR_ADDR_GPA,
.host_pa = P2SB_BAR_ADDR,
.size = P2SB_BAR_SIZE,
},
},
#endif
.pt_intx_num = VM0_PT_INTX_NUM,
.pt_intx = &vm0_pt_intx[0U],
.pt_intx_num = 0,
.pt_intx = vm0_pt_intx,
},
{ /* VM1 */
CONFIG_PRE_STD_VM(2),
.name = "ACRN PRE-LAUNCHED VM1",
{
/* Static configured VM1 */
CONFIG_PRE_STD_VM,
.name = "PRE_STD_VM1",
.vm_prio = PRIO_LOW,
.guest_flags = GUEST_FLAG_STATIC_VM,
.cpu_affinity = VM1_CONFIG_CPU_AFFINITY,
.guest_flags = 0UL,
#ifdef CONFIG_RDT_ENABLED
.clos = VM1_VCPU_CLOS,
#endif
.memory = {
.start_hpa = VM1_CONFIG_MEM_START_HPA,
.size = VM1_CONFIG_MEM_SIZE,
.start_hpa2 = VM1_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM1_CONFIG_MEM_SIZE_HPA2,
},
.os_config = {
.name = "YOCTO",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = VM1_BOOT_ARGS,
},
.acpi_config = {
.acpi_mod_tag = "ACPI_VM1",
},
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM2_BASE,
.irq = COM2_IRQ,
.t_vuart.vm_id = 0U,
.t_vuart.vuart_id = 1U,
},
.memory =
{
.start_hpa = VM1_CONFIG_MEM_START_HPA,
.size = VM1_CONFIG_MEM_SIZE,
.start_hpa2 = VM1_CONFIG_MEM_START_HPA2,
.size_hpa2 = VM1_CONFIG_MEM_SIZE_HPA2,
},
.os_config =
{
.name = "YOCTO",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.ramdisk_mod_tag = "",
.bootargs = VM1_BOOT_ARGS,
},
.acpi_config =
{
.acpi_mod_tag = "ACPI_VM1",
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x2F8U,
.irq = 3U,
.t_vuart.vm_id = 0U,
.t_vuart.vuart_id = 1U,
},
.pci_dev_num = VM1_CONFIG_PCI_DEV_NUM,
.pci_devs = vm1_pci_devs,
.pt_intx_num = 0,
.pt_intx = vm1_pt_intx,
},
{
/* Dynamic configured VM2 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM3 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM4 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM5 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM6 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM7 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM8 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM9 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM10 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM11 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM12 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM13 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM14 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM15 */
CONFIG_POST_STD_VM,
}
};

38
misc/config_tools/data/generic_board/generic_code/partitioned/vm_configurations.h
View File

@ -1,33 +1,27 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VM_CONFIGURATIONS_H
#define VM_CONFIGURATIONS_H
#include <misc_cfg.h>
#include <pci_devices.h>
/* SOS_VM_NUM can only be 0U or 1U;
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
*/
#define PRE_VM_NUM 2U
#define SOS_VM_NUM 0U
#define MAX_POST_VM_NUM 0U
#define CONFIG_MAX_KATA_VM_NUM 0U
#define DM_OWNED_GUEST_FLAG_MASK 0UL
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
#define VM1_CONFIG_MEM_START_HPA 0x120000000UL
#define VM1_CONFIG_MEM_SIZE 0x20000000UL
#define VM1_CONFIG_MEM_START_HPA2 0x0UL
#define VM1_CONFIG_MEM_SIZE_HPA2 0x0UL
/* SERVICE_VM_NUM can only be 0 or 1; When SERVICE_VM_NUM is 1, MAX_POST_VM_NUM must be 0 too. */
#define PRE_VM_NUM 2U
#define SERVICE_VM_NUM 0U
#define MAX_POST_VM_NUM 14U
#define CONFIG_MAX_VM_NUM 16U
#define DM_OWNED_GUEST_FLAG_MASK 0UL
#define VM0_CONFIG_MEM_START_HPA 0x100000000UL
#define VM0_CONFIG_MEM_SIZE 0x20000000UL
#define VM0_CONFIG_MEM_START_HPA2 0x0UL
#define VM0_CONFIG_MEM_SIZE_HPA2 0x0UL
#define VM1_CONFIG_MEM_START_HPA 0x120000000UL
#define VM1_CONFIG_MEM_SIZE 0x20000000UL
#define VM1_CONFIG_MEM_START_HPA2 0x0UL
#define VM1_CONFIG_MEM_SIZE_HPA2 0x0UL
#endif /* VM_CONFIGURATIONS_H */

3
misc/config_tools/data/generic_board/generic_code/shared/generic_board.config
View File

@ -1,8 +1,7 @@
# Board defconfig generated by acrn-config tool
CONFIG_BOARD="generic_board"
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x8800000
CONFIG_HV_RAM_START=0x00400000
CONFIG_PLATFORM_RAM_SIZE=0x400000000
CONFIG_LOW_RAM_SIZE=0x00010000
CONFIG_STACK_SIZE=0x2000

3
misc/config_tools/data/generic_board/generic_code/shared/ivshmem_cfg.h
View File

@ -1,8 +1,9 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IVSHMEM_CFG_H
#define IVSHMEM_CFG_H

95
misc/config_tools/data/generic_board/generic_code/shared/misc_cfg.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,77 +7,30 @@
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define SOS_ROOTFS "root=/dev/nvme0n1p3 "
#define SOS_CONSOLE "console=ttyS0 "
#define SOS_COM1_BASE 0x3F8U
#define SOS_COM1_IRQ 4U
#define SOS_COM2_BASE 0x2F8U
#define SOS_COM2_IRQ 3U
#define SOS_BOOTARGS_DIFF "rw " \
"rootwait " \
"console=tty0 " \
"consoleblank=0 " \
"no_timer_check " \
"quiet " \
"loglevel=3 " \
"i915.nuclear_pageflip=1 " \
"swiotlb=131072 " \
"maxcpus=4"
#define SOS_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM4_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM5_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM6_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM7_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define SERVICE_VM_ROOTFS "root=/dev/nvme0n1p3 "
#define SERVICE_VM_OS_CONSOLE "console=ttyS0 "
#define SERVICE_VM_BOOTARGS_DIFF \
"rw rootwait console=tty0 consoleblank=0 no_timer_check quiet loglevel=3 i915.nuclear_pageflip=1 " \
"swiotlb=131072 maxcpus=4 hugepagesz=1G hugepages=8 "
#define SERVICE_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U) | AFFINITY_CPU(3U))
#define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM4_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM5_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#define VM6_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
#ifdef CONFIG_RDT_ENABLED
/*
* The maximum CLOS that is allowed by ACRN hypervisor,
* its value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
* among all supported RDT resources in the platform. In other words, it is
* min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
* CLOS allocations between all the RDT resources.
*/
#define HV_SUPPORTED_MAX_CLOS 0U
/*
* Max number of Cache Mask entries corresponding to each CLOS.
* This can vary if CDP is enabled vs disabled, as each CLOS entry
* will have corresponding cache mask values for Data and Code when
* CDP is enabled.
*/
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
/* Max number of MBA delay entries corresponding to each CLOS. */
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#define CLOS_MASK_0 0xfffffU
#define CLOS_MASK_1 0xfffffU
#define CLOS_MASK_2 0xfffffU
#define CLOS_MASK_3 0xfffffU
#define CLOS_MASK_4 0xfffffU
#define CLOS_MASK_5 0xfffffU
#define CLOS_MASK_6 0xfffffU
#define CLOS_MASK_7 0xfffffU
#define VM0_VCPU_CLOS {0U}
#define VM1_VCPU_CLOS {0U, 0U}
#define VM2_VCPU_CLOS {0U, 0U}
#define VM3_VCPU_CLOS {0U, 0U}
#define VM4_VCPU_CLOS {0U, 0U}
#define VM5_VCPU_CLOS {0U, 0U}
#define VM6_VCPU_CLOS {0U, 0U}
#define VM7_VCPU_CLOS {0U, 0U}
#define HV_SUPPORTED_MAX_CLOS 0U
#define MAX_MBA_CLOS_NUM_ENTRIES 0U
#define MAX_CACHE_CLOS_NUM_ENTRIES 0U
#define CLOS_MASK_0 0xfffffU
#define CLOS_MASK_1 0xfffffU
#define CLOS_MASK_2 0xfffffU
#define CLOS_MASK_3 0xfffffU
#define CLOS_MASK_4 0xfffffU
#define CLOS_MASK_5 0xfffffU
#define CLOS_MASK_6 0xfffffU
#define CLOS_MASK_7 0xfffffU
#endif
#define VM0_PT_INTX_NUM 0U
#endif /* MISC_CFG_H */

10
misc/config_tools/data/generic_board/generic_code/shared/pci_dev.c
View File

@ -1,14 +1,14 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm/vm_config.h>
#include <pci_devices.h>
#include <vpci.h>
#include <vbar_base.h>
#include <asm/mmu.h>
#include <asm/page.h>
struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
#include <vmcs9900.h>
#include <ivshmem_cfg.h>
#define INVALID_PCI_BASE 0U
struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM] = {};

5
misc/config_tools/data/generic_board/generic_code/shared/pt_intx.c
View File

@ -1,10 +1,7 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm/vm_config.h>
struct pt_intx_config vm0_pt_intx[1U];

46
misc/config_tools/data/generic_board/generic_code/shared/vbar_base.h
View File

@ -7,46 +7,42 @@
#ifndef VBAR_BASE_H_
#define VBAR_BASE_H_
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x0UL, \
.vbar_base[2] = HI_MMIO_START + 0x10000000UL
#define VGA_COMPATIBLE_CONTROLLER_0_VBAR \
.vbar_base[0] = HI_MMIO_START + 0x0UL, .vbar_base[2] = HI_MMIO_START + 0x10000000UL
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20000000UL
#define SYSTEM_PERIPHERAL_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20000000UL
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20010000UL
#define USB_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20010000UL
#define USB_CONTROLLER_1_VBAR .vbar_base[0] = HI_MMIO_START + 0x20040000UL, \
.vbar_base[2] = HI_MMIO_START + 0x20080000UL
#define USB_CONTROLLER_1_VBAR .vbar_base[0] = HI_MMIO_START + 0x20040000UL, .vbar_base[2] = HI_MMIO_START + 0x20080000UL
#define USB_CONTROLLER_2_VBAR .vbar_base[0] = HI_MMIO_START + 0x200c0000UL, \
.vbar_base[2] = HI_MMIO_START + 0x20100000UL
#define USB_CONTROLLER_2_VBAR .vbar_base[0] = HI_MMIO_START + 0x200c0000UL, .vbar_base[2] = HI_MMIO_START + 0x20100000UL
#define USB_CONTROLLER_3_VBAR .vbar_base[0] = HI_MMIO_START + 0x20110000UL
#define USB_CONTROLLER_3_VBAR .vbar_base[0] = HI_MMIO_START + 0x20110000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20120000UL, \
.vbar_base[2] = HI_MMIO_START + 0x20124000UL
#define RAM_MEMORY_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20120000UL, .vbar_base[2] = HI_MMIO_START + 0x20124000UL
#define NETWORK_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20128000UL
#define NETWORK_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20128000UL
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012c000UL
#define SERIAL_BUS_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012c000UL
#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012d000UL
#define SERIAL_BUS_CONTROLLER_1_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012d000UL
#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = HI_MMIO_START + 0x20301000UL
#define SERIAL_BUS_CONTROLLER_2_VBAR .vbar_base[0] = HI_MMIO_START + 0x20301000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012e000UL
#define COMMUNICATION_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x2012e000UL
#define SATA_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20130000UL, \
.vbar_base[1] = HI_MMIO_START + 0x20132000UL, \
.vbar_base[5] = HI_MMIO_START + 0x20132800UL
#define SATA_CONTROLLER_0_VBAR \
.vbar_base[0] = HI_MMIO_START + 0x20130000UL, .vbar_base[1] = HI_MMIO_START + 0x20132000UL, \
.vbar_base[5] = HI_MMIO_START + 0x20132800UL
#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20134000UL, \
.vbar_base[4] = HI_MMIO_START + 0x20200000UL
#define AUDIO_DEVICE_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20134000UL, .vbar_base[4] = HI_MMIO_START + 0x20200000UL
#define SMBUS_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20300000UL
#define SMBUS_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20300000UL
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20304000UL
#define NON_VOLATILE_MEMORY_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20304000UL
#define ETHERNET_CONTROLLER_0_VBAR .vbar_base[0] = HI_MMIO_START + 0x20400000UL, \
.vbar_base[3] = HI_MMIO_START + 0x20500000UL
#define ETHERNET_CONTROLLER_0_VBAR \
.vbar_base[0] = HI_MMIO_START + 0x20400000UL, .vbar_base[3] = HI_MMIO_START + 0x20500000UL
#endif /* VBAR_BASE_H_ */

311
misc/config_tools/data/generic_board/generic_code/shared/vm_configurations.c
View File

@ -1,164 +1,201 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm/vm_config.h>
#include <vuart.h>
#include <asm/pci_dev.h>
#include <asm/pgtable.h>
#include <schedule.h>
extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
extern struct pt_intx_config vm0_pt_intx[1U];
struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
{ /* VM0 */
CONFIG_SOS_VM,
.name = "ACRN SOS VM",
/* Allow SOS to reboot the host since there is supposed to be the highest severity guest */
.guest_flags = 0UL,
#ifdef CONFIG_RDT_ENABLED
.clos = VM0_VCPU_CLOS,
#endif
.cpu_affinity = SOS_VM_CONFIG_CPU_AFFINITY,
.memory = {
.start_hpa = 0UL,
},
.os_config = {
.name = "ACRN Service OS",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.bootargs = SOS_VM_BOOTARGS,
},
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = SOS_COM1_BASE,
.irq = SOS_COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = SOS_COM2_BASE,
.irq = SOS_COM2_IRQ,
.t_vuart.vm_id = 2U,
.t_vuart.vuart_id = 1U,
},
{
/* Static configured VM0 */
CONFIG_SERVICE_VM,
.name = "ACRN_Service_VM",
/* Allow Service VM to reboot the system since it is the highest priority VM. */
.vm_prio = PRIO_LOW,
.guest_flags = GUEST_FLAG_STATIC_VM,
.cpu_affinity = SERVICE_VM_CONFIG_CPU_AFFINITY,
.memory =
{
.start_hpa = 0UL,
},
.os_config =
{
.name = "ACRN Service OS",
.kernel_type = KERNEL_BZIMAGE,
.kernel_mod_tag = "Linux_bzImage",
.ramdisk_mod_tag = "",
.bootargs = SERVICE_VM_OS_BOOTARGS,
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x2F8U,
.irq = 3U,
.t_vuart.vm_id = 2U,
.t_vuart.vuart_id = 1U,
},
.pci_dev_num = 0U,
.pci_devs = sos_pci_devs,
},
{ /* VM1 */
CONFIG_POST_STD_VM(1),
#ifdef CONFIG_RDT_ENABLED
.clos = VM1_VCPU_CLOS,
#endif
{
/* Static configured VM1 */
CONFIG_POST_STD_VM,
.name = "POST_STD_VM1",
.vm_prio = PRIO_LOW,
.guest_flags = GUEST_FLAG_STATIC_VM,
.cpu_affinity = VM1_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
},
},
{ /* VM2 */
CONFIG_POST_RT_VM(1),
#ifdef CONFIG_RDT_ENABLED
.clos = VM2_VCPU_CLOS,
#endif
{
/* Static configured VM2 */
CONFIG_POST_RT_VM,
.name = "POST_RT_VM1",
.vm_prio = PRIO_LOW,
.guest_flags = (GUEST_FLAG_STATIC_VM | GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT),
.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM2_BASE,
.irq = COM2_IRQ,
.t_vuart.vm_id = 0U,
.t_vuart.vuart_id = 1U,
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x2F8U,
.irq = 3U,
.t_vuart.vm_id = 0U,
.t_vuart.vuart_id = 1U,
},
},
{ /* VM3 */
CONFIG_POST_STD_VM(2),
#ifdef CONFIG_RDT_ENABLED
.clos = VM3_VCPU_CLOS,
#endif
{
/* Static configured VM3 */
CONFIG_POST_STD_VM,
.name = "POST_STD_VM2",
.vm_prio = PRIO_LOW,
.guest_flags = GUEST_FLAG_STATIC_VM,
.cpu_affinity = VM3_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
},
},
{ /* VM4 */
CONFIG_POST_STD_VM(3),
#ifdef CONFIG_RDT_ENABLED
.clos = VM4_VCPU_CLOS,
#endif
{
/* Static configured VM4 */
CONFIG_POST_STD_VM,
.name = "POST_STD_VM3",
.vm_prio = PRIO_LOW,
.guest_flags = GUEST_FLAG_STATIC_VM,
.cpu_affinity = VM4_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
},
},
{ /* VM5 */
CONFIG_POST_STD_VM(4),
#ifdef CONFIG_RDT_ENABLED
.clos = VM5_VCPU_CLOS,
#endif
{
/* Static configured VM5 */
CONFIG_POST_STD_VM,
.name = "POST_STD_VM4",
.vm_prio = PRIO_LOW,
.guest_flags = GUEST_FLAG_STATIC_VM,
.cpu_affinity = VM5_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
},
},
{ /* VM6 */
CONFIG_POST_STD_VM(5),
#ifdef CONFIG_RDT_ENABLED
.clos = VM6_VCPU_CLOS,
#endif
{
/* Static configured VM6 */
CONFIG_POST_STD_VM,
.name = "POST_STD_VM5",
.vm_prio = PRIO_LOW,
.guest_flags = GUEST_FLAG_STATIC_VM,
.cpu_affinity = VM6_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = COM1_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
.vuart[0] =
{
.type = VUART_LEGACY_PIO,
.addr.port_base = 0x3F8U,
.irq = 4U,
},
.vuart[1] =
{
.type = VUART_LEGACY_PIO,
},
},
{ /* VM7 */
CONFIG_KATA_VM(1),
#ifdef CONFIG_RDT_ENABLED
.clos = VM7_VCPU_CLOS,
#endif
.cpu_affinity = VM7_CONFIG_CPU_AFFINITY,
.vuart[0] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
.irq = COM1_IRQ,
},
.vuart[1] = {
.type = VUART_LEGACY_PIO,
.addr.port_base = INVALID_COM_BASE,
},
{
/* Dynamic configured VM7 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM8 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM9 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM10 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM11 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM12 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM13 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM14 */
CONFIG_POST_STD_VM,
},
{
/* Dynamic configured VM15 */
CONFIG_POST_STD_VM,
}
};

33
misc/config_tools/data/generic_board/generic_code/shared/vm_configurations.h
View File

@ -1,31 +1,24 @@
/*
* Copyright (C) 2021 Intel Corporation. All rights reserved.
* Copyright (C) 2021 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef VM_CONFIGURATIONS_H
#define VM_CONFIGURATIONS_H
#include <misc_cfg.h>
#include <pci_devices.h>
/* SOS_VM_NUM can only be 0U or 1U;
* When SOS_VM_NUM is 0U, MAX_POST_VM_NUM must be 0U too;
* MAX_POST_VM_NUM must be bigger than CONFIG_MAX_KATA_VM_NUM;
*/
#define PRE_VM_NUM 0U
#define SOS_VM_NUM 1U
#define MAX_POST_VM_NUM 7U
#define CONFIG_MAX_KATA_VM_NUM 1U
/* Bits mask of guest flags that can be programmed by device model. Other bits are set by hypervisor only */
#define DM_OWNED_GUEST_FLAG_MASK (GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | \
GUEST_FLAG_RT | GUEST_FLAG_IO_COMPLETION_POLLING)
/* SOS_VM == VM0 */
#define SOS_VM_BOOTARGS SOS_ROOTFS \
SOS_CONSOLE \
SOS_IDLE \
SOS_BOOTARGS_DIFF
/* SERVICE_VM_NUM can only be 0 or 1; When SERVICE_VM_NUM is 1, MAX_POST_VM_NUM must be 0 too. */
#define PRE_VM_NUM 0U
#define SERVICE_VM_NUM 1U
#define MAX_POST_VM_NUM 15U
#define CONFIG_MAX_VM_NUM 16U
/* Bitmask of guest flags that can be programmed by device model. Other bits are set by hypervisor only. */
#define DM_OWNED_GUEST_FLAG_MASK \
(GUEST_FLAG_SECURE_WORLD_ENABLED | GUEST_FLAG_LAPIC_PASSTHROUGH | GUEST_FLAG_RT | \
GUEST_FLAG_IO_COMPLETION_POLLING | GUEST_FLAG_SECURITY_VM)
/* SERVICE_VM == VM0 */
#define SERVICE_VM_OS_BOOTARGS SERVICE_VM_ROOTFS SERVICE_VM_OS_CONSOLE SERVICE_VM_IDLE SERVICE_VM_BOOTARGS_DIFF
#endif /* VM_CONFIGURATIONS_H */