mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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hv: pirq: change the order of functions within irq.c
This commit changes the order of functions in arch/x86/irq.c, and internal function names to make it looks cleaner, with no change within any function. Signed-off-by: Yan, Like <like.yan@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Yan, Like
lijinxia
parent
a8cd6925fc
commit
538173838d
@ -334,7 +334,7 @@ ioapic_nr_pins(void *ioapic_base)
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return nr_pins;
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}
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void setup_ioapic_irq(void)
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void setup_ioapic_irqs(void)
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{
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uint8_t ioapic_id;
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uint32_t gsi = 0U;
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@ -15,39 +15,12 @@ static uint32_t vector_to_irq[NR_MAX_VECTOR + 1];
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spurious_handler_t spurious_handler;
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static inline void handle_irq(struct irq_desc *desc);
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#define NR_STATIC_MAPPINGS (2U)
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static uint32_t irq_static_mappings[NR_STATIC_MAPPINGS][2] = {
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{TIMER_IRQ, VECTOR_TIMER},
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{NOTIFY_IRQ, VECTOR_NOTIFY_VCPU},
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};
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static void init_irq_desc(void)
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{
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uint32_t i;
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for (i = 0U; i < NR_IRQS; i++) {
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irq_desc_array[i].irq = i;
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irq_desc_array[i].vector = VECTOR_INVALID;
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spinlock_init(&irq_desc_array[i].lock);
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}
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for (i = 0U; i <= NR_MAX_VECTOR; i++) {
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vector_to_irq[i] = IRQ_INVALID;
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}
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/* init fixed mapping for specific irq and vector */
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for (i = 0U; i < NR_STATIC_MAPPINGS; i++) {
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uint32_t irq = irq_static_mappings[i][0];
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uint32_t vr = irq_static_mappings[i][1];
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irq_desc_array[irq].vector = vr;
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irq_desc_array[irq].used = IRQ_ASSIGNED;
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vector_to_irq[vr] = irq;
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}
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}
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/*
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* alloc an free irq if req_irq is IRQ_INVALID, or else set assigned
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* return: irq num on success, IRQ_INVALID on failure
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@ -184,12 +157,6 @@ void free_irq_vector(uint32_t irq)
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spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
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}
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static void disable_pic_irq(void)
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{
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pio_write8(0xffU, 0xA1U);
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pio_write8(0xffU, 0x21U);
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}
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/*
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* There are four cases as to irq/vector allocation:
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* case 1: req_irq = IRQ_INVALID
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@ -256,6 +223,48 @@ int32_t request_irq(uint32_t req_irq,
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return (int32_t)irq;
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}
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void free_irq(uint32_t irq)
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{
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uint64_t rflags;
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struct irq_desc *desc;
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if (irq >= NR_IRQS) {
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return;
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}
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desc = &irq_desc_array[irq];
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dev_dbg(ACRN_DBG_IRQ, "[%s] irq%d vr:0x%x",
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__func__, irq, irq_to_vector(irq));
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free_irq_vector(irq);
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free_irq_num(irq);
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spinlock_irqsave_obtain(&desc->lock, &rflags);
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desc->action = NULL;
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desc->priv_data = NULL;
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desc->flags = IRQF_NONE;
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spinlock_irqrestore_release(&desc->lock, rflags);
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}
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void set_irq_trigger_mode(uint32_t irq, bool is_level_trigger)
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{
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uint64_t rflags;
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struct irq_desc *desc;
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if (irq >= NR_IRQS) {
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return;
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}
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desc = &irq_desc_array[irq];
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spinlock_irqsave_obtain(&desc->lock, &rflags);
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if (is_level_trigger == true) {
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desc->flags |= IRQF_LEVEL;
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} else {
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desc->flags &= ~IRQF_LEVEL;
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}
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spinlock_irqrestore_release(&desc->lock, rflags);
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}
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uint32_t irq_to_vector(uint32_t irq)
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{
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if (irq < NR_IRQS) {
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@ -265,37 +274,6 @@ uint32_t irq_to_vector(uint32_t irq)
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}
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}
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void init_default_irqs(uint16_t cpu_id)
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{
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if (cpu_id != BOOT_CPU_ID) {
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return;
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}
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init_irq_desc();
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/* we use ioapic only, disable legacy PIC */
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disable_pic_irq();
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setup_ioapic_irq();
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init_softirq();
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}
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void dispatch_exception(struct intr_excp_ctx *ctx)
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{
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uint16_t pcpu_id = get_cpu_id();
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/* Obtain lock to ensure exception dump doesn't get corrupted */
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spinlock_obtain(&exception_spinlock);
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/* Dump exception context */
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dump_exception(ctx, pcpu_id);
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/* Release lock to let other CPUs handle exception */
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spinlock_release(&exception_spinlock);
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/* Halt the CPU */
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cpu_dead(pcpu_id);
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}
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static void handle_spurious_interrupt(uint32_t vector)
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{
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send_lapic_eoi();
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@ -309,6 +287,41 @@ static void handle_spurious_interrupt(uint32_t vector)
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}
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}
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static inline bool irq_need_mask(struct irq_desc *desc)
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{
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/* level triggered gsi should be masked */
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return (((desc->flags & IRQF_LEVEL) != 0U)
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&& irq_is_gsi(desc->irq));
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}
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static inline bool irq_need_unmask(struct irq_desc *desc)
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{
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/* level triggered gsi for non-ptdev should be unmasked */
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return (((desc->flags & IRQF_LEVEL) != 0U)
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&& ((desc->flags & IRQF_PT) == 0U)
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&& irq_is_gsi(desc->irq));
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}
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static inline void handle_irq(struct irq_desc *desc)
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{
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irq_action_t action = desc->action;
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if (irq_need_mask(desc)) {
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GSI_MASK_IRQ(desc->irq);
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}
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/* Send EOI to LAPIC/IOAPIC IRR */
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send_lapic_eoi();
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if (action != NULL) {
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action(desc->irq, desc->priv_data);
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}
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if (irq_need_unmask(desc)) {
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GSI_UNMASK_IRQ(desc->irq);
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}
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}
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/* do_IRQ() */
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void dispatch_interrupt(struct intr_excp_ctx *ctx)
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{
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@ -339,6 +352,23 @@ ERR:
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return;
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}
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void dispatch_exception(struct intr_excp_ctx *ctx)
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{
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uint16_t pcpu_id = get_cpu_id();
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/* Obtain lock to ensure exception dump doesn't get corrupted */
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spinlock_obtain(&exception_spinlock);
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/* Dump exception context */
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dump_exception(ctx, pcpu_id);
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/* Release lock to let other CPUs handle exception */
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spinlock_release(&exception_spinlock);
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/* Halt the CPU */
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cpu_dead(pcpu_id);
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}
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#ifdef CONFIG_PARTITION_MODE
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void partition_mode_dispatch_interrupt(struct intr_excp_ctx *ctx)
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{
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@ -361,83 +391,6 @@ void partition_mode_dispatch_interrupt(struct intr_excp_ctx *ctx)
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}
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#endif
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static inline bool irq_need_mask(struct irq_desc *desc)
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{
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/* level triggered gsi should be masked */
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return (((desc->flags & IRQF_LEVEL) != 0U)
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&& irq_is_gsi(desc->irq));
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}
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static inline bool irq_need_unmask(struct irq_desc *desc)
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{
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/* level triggered gsi for non-ptdev should be unmasked */
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return (((desc->flags & IRQF_LEVEL) != 0U)
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&& ((desc->flags & IRQF_PT) == 0U)
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&& irq_is_gsi(desc->irq));
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}
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static inline void handle_irq(struct irq_desc *desc)
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{
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irq_action_t action = desc->action;
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if (irq_need_mask(desc)) {
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GSI_MASK_IRQ(desc->irq);
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}
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/* Send EOI to LAPIC/IOAPIC IRR */
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send_lapic_eoi();
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if (action != NULL) {
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action(desc->irq, desc->priv_data);
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}
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if (irq_need_unmask(desc)) {
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GSI_UNMASK_IRQ(desc->irq);
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}
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}
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void set_irq_trigger_mode(uint32_t irq, bool is_level_trigger)
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{
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uint64_t rflags;
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struct irq_desc *desc;
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if (irq >= NR_IRQS) {
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return;
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}
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desc = &irq_desc_array[irq];
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spinlock_irqsave_obtain(&desc->lock, &rflags);
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if (is_level_trigger == true) {
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desc->flags |= IRQF_LEVEL;
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} else {
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desc->flags &= ~IRQF_LEVEL;
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}
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spinlock_irqrestore_release(&desc->lock, rflags);
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}
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void free_irq(uint32_t irq)
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{
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uint64_t rflags;
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struct irq_desc *desc;
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if (irq >= NR_IRQS) {
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return;
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}
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desc = &irq_desc_array[irq];
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dev_dbg(ACRN_DBG_IRQ, "[%s] irq%d vr:0x%x",
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__func__, irq, irq_to_vector(irq));
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free_irq_vector(irq);
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free_irq_num(irq);
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spinlock_irqsave_obtain(&desc->lock, &rflags);
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desc->action = NULL;
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desc->priv_data = NULL;
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desc->flags = IRQF_NONE;
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spinlock_irqrestore_release(&desc->lock, rflags);
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}
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#ifdef HV_DEBUG
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void get_cpu_interrupt_info(char *str_arg, int str_max)
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{
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@ -476,6 +429,51 @@ void get_cpu_interrupt_info(char *str_arg, int str_max)
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}
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#endif /* HV_DEBUG */
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static void init_irq_descs(void)
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{
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uint32_t i;
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for (i = 0U; i < NR_IRQS; i++) {
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irq_desc_array[i].irq = i;
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irq_desc_array[i].vector = VECTOR_INVALID;
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spinlock_init(&irq_desc_array[i].lock);
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}
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for (i = 0U; i <= NR_MAX_VECTOR; i++) {
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vector_to_irq[i] = IRQ_INVALID;
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}
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/* init fixed mapping for specific irq and vector */
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for (i = 0U; i < NR_STATIC_MAPPINGS; i++) {
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uint32_t irq = irq_static_mappings[i][0];
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uint32_t vr = irq_static_mappings[i][1];
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irq_desc_array[irq].vector = vr;
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irq_desc_array[irq].used = IRQ_ASSIGNED;
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vector_to_irq[vr] = irq;
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}
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}
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static void disable_pic_irqs(void)
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{
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pio_write8(0xffU, 0xA1U);
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pio_write8(0xffU, 0x21U);
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}
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void init_default_irqs(uint16_t cpu_id)
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{
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if (cpu_id != BOOT_CPU_ID) {
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return;
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}
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init_irq_descs();
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/* we use ioapic only, disable legacy PIC */
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disable_pic_irqs();
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setup_ioapic_irqs();
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init_softirq();
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}
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void interrupt_init(uint16_t pcpu_id)
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{
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struct host_idt_descriptor *idtd = &HOST_IDTR;
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@ -19,7 +19,7 @@
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#define GSI_MASK_IRQ(irq) irq_gsi_mask_unmask((irq), true)
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#define GSI_UNMASK_IRQ(irq) irq_gsi_mask_unmask((irq), false)
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void setup_ioapic_irq(void);
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void setup_ioapic_irqs(void);
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bool irq_is_gsi(uint32_t irq);
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uint32_t irq_gsi_num(void);
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