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acrn-config: set up whitelist for board containing hide pci device
Currently, config tool will maintain a whitelist for the board which need to hide some pci devices. For the board out of whitelist, we set MAX_HIDE_PDEVS_NUM to 0. Tracked-On: #3475 Signed-off-by: Wei Liu <weix.w.liu@intel.com> Acked-by: Victor Sun <victor.sun@intel.com>
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@ -10,7 +10,8 @@ import board_cfg_lib
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INCLUDE_HEADER = """
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INCLUDE_HEADER = """
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#include <board.h>
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#include <board.h>
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#include <vtd.h>
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#include <vtd.h>
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#include <msr.h>"""
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#include <msr.h>
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#include <pci.h>"""
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MSR_IA32_L2_MASK_BASE = 0x00000D10
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MSR_IA32_L2_MASK_BASE = 0x00000D10
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@ -155,6 +156,26 @@ def gen_px_cx(config):
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print("};", file=config)
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print("};", file=config)
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def gen_pci_hide(config):
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"""Generate hide pci information for this platform"""
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if board_cfg_lib.BOARD_NAME in list(board_cfg_lib.KNOWN_HIDDEN_PDEVS_BOARD_DB.keys()) and board_cfg_lib.KNOWN_HIDDEN_PDEVS_BOARD_DB[board_cfg_lib.BOARD_NAME] != 0:
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hidden_pdev_list = board_cfg_lib.KNOWN_HIDDEN_PDEVS_BOARD_DB[board_cfg_lib.BOARD_NAME]
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hidden_pdev_num = len(hidden_pdev_list)
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print("const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM] = {", file=config)
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for hidden_pdev_i in range(hidden_pdev_num):
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bus = hex(int(hidden_pdev_list[hidden_pdev_i].split(':')[0], 16))
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dev = hex(int(hidden_pdev_list[hidden_pdev_i].split(':')[1], 16))
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fun = hex(int(hidden_pdev_list[hidden_pdev_i].split(':')[2], 16))
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print("\t{", file=config)
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print("\t\t.bits.b = {}U,".format(bus), file=config)
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print("\t\t.bits.d = {}U,".format(dev), file=config)
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print("\t\t.bits.f = {}U,".format(fun), file=config)
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print("\t},", file=config)
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print("};", file=config)
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else:
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print("const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];", file=config)
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def generate_file(config):
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def generate_file(config):
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"""
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"""
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Start to generate board.c
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Start to generate board.c
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@ -178,4 +199,7 @@ def generate_file(config):
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# start to parse PX/CX info
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# start to parse PX/CX info
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gen_px_cx(config)
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gen_px_cx(config)
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# gen hide pci info for platform
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gen_pci_hide(config)
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return err_dic
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return err_dic
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@ -12,6 +12,7 @@ MISC_CFG_HEADER = """
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MISC_CFG_END = """#endif /* MISC_CFG_H */"""
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MISC_CFG_END = """#endif /* MISC_CFG_H */"""
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class Vuart:
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class Vuart:
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t_vm_id = {}
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t_vm_id = {}
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@ -157,6 +158,15 @@ def generate_file(config):
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print("", file=config)
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print("", file=config)
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if "SOS_VM" in vm_types:
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if "SOS_VM" in vm_types:
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sos_bootarg_diff(sos_cmdlines, config)
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sos_bootarg_diff(sos_cmdlines, config)
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# set macro for HIDDEN PTDEVS
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print("", file=config)
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if board_cfg_lib.BOARD_NAME in list(board_cfg_lib.KNOWN_HIDDEN_PDEVS_BOARD_DB):
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print("#define MAX_HIDDEN_PDEVS_NUM {}U".format(len(board_cfg_lib.KNOWN_HIDDEN_PDEVS_BOARD_DB[board_cfg_lib.BOARD_NAME])), file=config)
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else:
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print("#define MAX_HIDDEN_PDEVS_NUM 0U", file=config)
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print("", file=config)
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print("{}".format(MISC_CFG_END), file=config)
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print("{}".format(MISC_CFG_END), file=config)
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return err_dic
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return err_dic
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@ -33,6 +33,11 @@ ERR_LIST = {}
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HEADER_LICENSE = common.open_license() + "\n"
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HEADER_LICENSE = common.open_license() + "\n"
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# The data base contains hide pci device
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KNOWN_HIDDEN_PDEVS_BOARD_DB = {
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'apl-up2':['00:0d:0'],
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}
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def prepare(check_git):
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def prepare(check_git):
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""" check environment """
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""" check environment """
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