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Revert "Refine the BSP/AP boot flowchart to match BIOS boot flow"

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This reverts commit ff9d667b49.
This commit is contained in:
Zhao Yakui 2019-06-26 13:37:09 +08:00
parent 8c357a849f
commit 58dcb0af1b
2 changed files with 1 additions and 20 deletions
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11
hypervisor/arch/x86/cpu.c
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@ -232,12 +232,11 @@ void init_pcpu_post(uint16_t pcpu_id)
ptdev_init(); ptdev_init();
/* Start all secondary cores */ /* Start all secondary cores */
#if 0
startup_paddr = prepare_trampoline(); startup_paddr = prepare_trampoline();
if (!start_pcpus(AP_MASK)) { if (!start_pcpus(AP_MASK)) {
panic("Failed to start all secondary cores!"); panic("Failed to start all secondary cores!");
} }
#endif
ASSERT(get_pcpu_id() == BOOT_CPU_ID, ""); ASSERT(get_pcpu_id() == BOOT_CPU_ID, "");
} else { } else {
pr_dbg("Core %hu is up", pcpu_id); pr_dbg("Core %hu is up", pcpu_id);
@ -314,14 +313,6 @@ bool start_pcpus(uint64_t mask)
uint16_t pcpu_id = get_pcpu_id(); uint16_t pcpu_id = get_pcpu_id();
uint64_t expected_start_mask = mask; uint64_t expected_start_mask = mask;
if ((pcpu_active_bitmap & mask) == mask)
return 1;
#if 1
if (startup_paddr == 0)
startup_paddr = prepare_trampoline();
#endif
/* secondary cpu start up will wait for pcpu_sync -> 0UL */ /* secondary cpu start up will wait for pcpu_sync -> 0UL */
atomic_store64(&pcpu_sync, 1UL); atomic_store64(&pcpu_sync, 1UL);

10
hypervisor/arch/x86/guest/vlapic.c
View File

@ -1201,7 +1201,6 @@ vlapic_process_init_sipi(struct acrn_vcpu* target_vcpu, uint32_t mode,
target_vcpu->arch.nr_sipi = 1U; target_vcpu->arch.nr_sipi = 1U;
} }
} else if (mode == APIC_DELMODE_STARTUP) { } else if (mode == APIC_DELMODE_STARTUP) {
/* Ignore SIPIs in any state other than wait-for-SIPI */ /* Ignore SIPIs in any state other than wait-for-SIPI */
if ((target_vcpu->state == VCPU_INIT) && if ((target_vcpu->state == VCPU_INIT) &&
(target_vcpu->arch.nr_sipi != 0U)) { (target_vcpu->arch.nr_sipi != 0U)) {
@ -1260,11 +1259,6 @@ static void vlapic_icrlo_write_handler(struct acrn_vlapic *vlapic)
} else if (((shorthand == APIC_DEST_SELF) || (shorthand == APIC_DEST_ALLISELF)) } else if (((shorthand == APIC_DEST_SELF) || (shorthand == APIC_DEST_ALLISELF))
&& ((mode == APIC_DELMODE_NMI) || (mode == APIC_DELMODE_INIT) && ((mode == APIC_DELMODE_NMI) || (mode == APIC_DELMODE_INIT)
|| (mode == APIC_DELMODE_STARTUP))) { || (mode == APIC_DELMODE_STARTUP))) {
#if 1
/* Start all secondary cores */
start_pcpus(AP_MASK);
#endif
dev_dbg(ACRN_DBG_LAPIC, "Invalid ICR value"); dev_dbg(ACRN_DBG_LAPIC, "Invalid ICR value");
} else { } else {
@ -1274,10 +1268,6 @@ static void vlapic_icrlo_write_handler(struct acrn_vlapic *vlapic)
switch (shorthand) { switch (shorthand) {
case APIC_DEST_DESTFLD: case APIC_DEST_DESTFLD:
#if 1
/* Start all secondary cores */
start_pcpus(AP_MASK);
#endif
vlapic_calc_dest(vlapic->vm, &dmask, is_broadcast, dest, phys, false); vlapic_calc_dest(vlapic->vm, &dmask, is_broadcast, dest, phys, false);
break; break;
case APIC_DEST_SELF: case APIC_DEST_SELF: