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hv: msix: fix "Procedure has more than one exit point"
IEC 61508,ISO 26262 standards highly recommend single-exit rule. Reduce the count of the "return entries". Fix the violations which is comply with the cases list below: 1.Function has 2 return entries. 2.The first return entry is used to return the error code of checking variable whether is valid. V1->V2: remove the unrelated code. Fix the violations in "if else" format. Tracked-On: #861 Signed-off-by: Huihuang Shi <huihuang.shi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Huihuang Shi
lijinxia
parent
2f33d1bcf2
commit
5b6c611a1d
@ -32,11 +32,15 @@
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static inline bool msixcap_access(struct pci_vdev *vdev, uint32_t offset)
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{
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bool ret;
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if (vdev->msix.capoff == 0U) {
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return 0;
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ret = false;
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} else {
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ret = in_range(offset, vdev->msix.capoff, vdev->msix.caplen);
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}
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return in_range(offset, vdev->msix.capoff, vdev->msix.caplen);
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return ret;
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}
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static inline bool msixtable_access(struct pci_vdev *vdev, uint32_t offset)
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@ -56,25 +60,23 @@ static int vmsix_remap_entry(struct pci_vdev *vdev, uint32_t index, bool enable)
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info.vmsi_data = (enable) ? vdev->msix.tables[index].data : 0U;
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ret = ptdev_msix_remap(vdev->vpci->vm, vdev->vbdf.value, (uint16_t)index, &info);
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if (ret != 0) {
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return ret;
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if (ret == 0) {
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/* Write the table entry to the physical structure */
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hva = vdev->msix.mmio_hva + vdev->msix.table_offset;
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pentry = (struct msix_table_entry *)hva + index;
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/*
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* PCI 3.0 Spec allows writing to Message Address and Message Upper Address
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* fields with a single QWORD write, but some hardware can accept 32 bits
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* write only
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*/
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mmio_write32((uint32_t)(info.pmsi_addr), (const void *)&(pentry->addr));
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mmio_write32((uint32_t)(info.pmsi_addr >> 32U), (const void *)((char *)&(pentry->addr) + 4U));
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mmio_write32(info.pmsi_data, (const void *)&(pentry->data));
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mmio_write32(vdev->msix.tables[index].vector_control, (const void *)&(pentry->vector_control));
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}
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/* Write the table entry to the physical structure */
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hva = vdev->msix.mmio_hva + vdev->msix.table_offset;
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pentry = (struct msix_table_entry *)hva + index;
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/*
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* PCI 3.0 Spec allows writing to Message Address and Message Upper Address
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* fields with a single QWORD write, but some hardware can accept 32 bits
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* write only
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*/
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mmio_write32((uint32_t)(info.pmsi_addr), (const void *)&(pentry->addr));
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mmio_write32((uint32_t)(info.pmsi_addr >> 32U), (const void *)((char *)&(pentry->addr) + 4U));
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mmio_write32(info.pmsi_data, (const void *)&(pentry->data));
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mmio_write32(vdev->msix.tables[index].vector_control, (const void *)&(pentry->vector_control));
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return ret;
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}
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@ -126,19 +128,17 @@ static int vmsix_remap_one_entry(struct pci_vdev *vdev, uint32_t index, bool ena
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enable_disable_msix(vdev, false);
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ret = vmsix_remap_entry(vdev, index, enable);
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if (ret != 0) {
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return ret;
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}
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if (ret == 0) {
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/* If MSI Enable is being set, make sure INTxDIS bit is set */
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if (enable) {
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enable_disable_pci_intx(vdev->pdev.bdf, false);
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}
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/* If MSI Enable is being set, make sure INTxDIS bit is set */
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if (enable) {
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enable_disable_pci_intx(vdev->pdev.bdf, false);
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}
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/* Restore MSI-X Enable bit */
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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if ((msgctrl & PCIM_MSIXCTRL_MSIX_ENABLE) == PCIM_MSIXCTRL_MSIX_ENABLE) {
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pci_pdev_write_cfg(vdev->pdev.bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U, msgctrl);
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/* Restore MSI-X Enable bit */
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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if ((msgctrl & PCIM_MSIXCTRL_MSIX_ENABLE) == PCIM_MSIXCTRL_MSIX_ENABLE) {
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pci_pdev_write_cfg(vdev->pdev.bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U, msgctrl);
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}
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}
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return ret;
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@ -146,18 +146,23 @@ static int vmsix_remap_one_entry(struct pci_vdev *vdev, uint32_t index, bool ena
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static int vmsix_cfgread(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val)
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{
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int32_t ret;
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/* For PIO access, we emulate Capability Structures only */
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if (msixcap_access(vdev, offset)) {
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*val = pci_vdev_read_cfg(vdev, offset, bytes);
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return 0;
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ret = 0;
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} else {
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ret = -ENODEV;
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}
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return -ENODEV;
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return ret;
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}
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static int vmsix_cfgwrite(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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uint32_t msgctrl;
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int32_t ret;
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/* Writing MSI-X Capability Structure */
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if (msixcap_access(vdev, offset)) {
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@ -181,10 +186,12 @@ static int vmsix_cfgwrite(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes
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}
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}
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return 0;
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ret = 0;
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} else {
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ret = -ENODEV;
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}
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return -ENODEV;
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return ret;
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}
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static void vmsix_table_rw(struct pci_vdev *vdev, struct mmio_request *mmio, uint32_t offset)
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@ -300,41 +307,40 @@ static void decode_msix_table_bar(struct pci_vdev *vdev)
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uint32_t bar_lo, bar_hi, val32;
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bar_lo = pci_pdev_read_cfg(pbdf, pci_bar_offset(bir), 4U);
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if ((bar_lo & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) {
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if ((bar_lo & PCIM_BAR_SPACE) != PCIM_BAR_IO_SPACE) {
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/* Get the base address */
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base = (uint64_t)bar_lo & PCIM_BAR_MEM_BASE;
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if ((bar_lo & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64) {
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bar_hi = pci_pdev_read_cfg(pbdf, pci_bar_offset(bir + 1U), 4U);
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base |= ((uint64_t)bar_hi << 32U);
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}
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vdev->msix.mmio_hva = (uint64_t)hpa2hva(base);
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vdev->msix.mmio_gpa = vm0_hpa2gpa(base);
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/* Sizing the BAR */
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size = 0U;
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if (((bar_lo & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64) && (bir < (PCI_BAR_COUNT - 1U))) {
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir + 1U), 4U, ~0U);
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size = (uint64_t)pci_pdev_read_cfg(pbdf, pci_bar_offset(bir + 1U), 4U);
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size <<= 32U;
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}
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir), 4U, ~0U);
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val32 = pci_pdev_read_cfg(pbdf, pci_bar_offset(bir), 4U);
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size |= ((uint64_t)val32 & PCIM_BAR_MEM_BASE);
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vdev->msix.mmio_size = size & ~(size - 1U);
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/* Restore the BAR */
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir), 4U, bar_lo);
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if ((bar_lo & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64) {
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir + 1U), 4U, bar_hi);
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}
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} else {
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/* I/O bar, should never happen */
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pr_err("PCI device (%x) has MSI-X Table at IO BAR", vdev->vbdf.value);
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return;
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}
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/* Get the base address */
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base = (uint64_t)bar_lo & PCIM_BAR_MEM_BASE;
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if ((bar_lo & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64) {
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bar_hi = pci_pdev_read_cfg(pbdf, pci_bar_offset(bir + 1U), 4U);
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base |= ((uint64_t)bar_hi << 32U);
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}
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vdev->msix.mmio_hva = (uint64_t)hpa2hva(base);
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vdev->msix.mmio_gpa = vm0_hpa2gpa(base);
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/* Sizing the BAR */
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size = 0U;
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if (((bar_lo & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64) && (bir < (PCI_BAR_COUNT - 1U))) {
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir + 1U), 4U, ~0U);
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size = (uint64_t)pci_pdev_read_cfg(pbdf, pci_bar_offset(bir + 1U), 4U);
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size <<= 32U;
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}
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir), 4U, ~0U);
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val32 = pci_pdev_read_cfg(pbdf, pci_bar_offset(bir), 4U);
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size |= ((uint64_t)val32 & PCIM_BAR_MEM_BASE);
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vdev->msix.mmio_size = size & ~(size - 1U);
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/* Restore the BAR */
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir), 4U, bar_lo);
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if ((bar_lo & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64) {
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pci_pdev_write_cfg(pbdf, pci_bar_offset(bir + 1U), 4U, bar_hi);
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}
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}
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@ -344,6 +350,7 @@ static int vmsix_init(struct pci_vdev *vdev)
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uint32_t table_info, i;
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uint64_t addr_hi, addr_lo;
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struct msix *msix = &vdev->msix;
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int32_t ret;
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msgctrl = pci_pdev_read_cfg(vdev->pdev.bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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@ -354,49 +361,50 @@ static int vmsix_init(struct pci_vdev *vdev)
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msix->table_offset = table_info & ~PCIM_MSIX_BIR_MASK;
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msix->table_count = (msgctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1U;
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if (msix->table_bar >= (PCI_BAR_COUNT - 1U)) {
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if (msix->table_bar < (PCI_BAR_COUNT - 1U)) {
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/* Mask all table entries */
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for (i = 0U; i < msix->table_count; i++) {
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msix->tables[i].vector_control = PCIM_MSIX_VCTRL_MASK;
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msix->tables[i].addr = 0U;
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msix->tables[i].data = 0U;
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}
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decode_msix_table_bar(vdev);
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if (msix->mmio_gpa != 0U) {
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/*
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* PCI Spec: a BAR may also map other usable address space that is not associated
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* with MSI-X structures, but it must not share any naturally aligned 4 KB
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* address range with one where either MSI-X structure resides.
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* The MSI-X Table and MSI-X PBA are permitted to co-reside within a naturally
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* aligned 4 KB address range.
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*
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* If PBA or others reside in the same BAR with MSI-X Table, devicemodel could
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* emulate them and maps these memory range at the 4KB boundary. Here, we should
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* make sure only intercept the minimum number of 4K pages needed for MSI-X table.
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*/
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/* The higher boundary of the 4KB aligned address range for MSI-X table */
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addr_hi = msix->mmio_gpa + msix->table_offset + msix->table_count * MSIX_TABLE_ENTRY_SIZE;
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addr_hi = round_page_up(addr_hi);
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/* The lower boundary of the 4KB aligned address range for MSI-X table */
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addr_lo = round_page_down(msix->mmio_gpa + msix->table_offset);
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msix->intercepted_gpa = addr_lo;
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msix->intercepted_size = addr_hi - addr_lo;
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(void)register_mmio_emulation_handler(vdev->vpci->vm, vmsix_table_mmio_access_handler,
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msix->intercepted_gpa, msix->intercepted_gpa + msix->intercepted_size, vdev);
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}
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ret = 0;
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} else {
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pr_err("%s, MSI-X device (%x) invalid table BIR %d", __func__, vdev->pdev.bdf.value, msix->table_bar);
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vdev->msix.capoff = 0U;
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return -EIO;
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ret = -EIO;
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}
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/* Mask all table entries */
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for (i = 0U; i < msix->table_count; i++) {
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msix->tables[i].vector_control = PCIM_MSIX_VCTRL_MASK;
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msix->tables[i].addr = 0U;
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msix->tables[i].data = 0U;
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}
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decode_msix_table_bar(vdev);
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if (msix->mmio_gpa != 0U) {
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/*
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* PCI Spec: a BAR may also map other usable address space that is not associated
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* with MSI-X structures, but it must not share any naturally aligned 4 KB
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* address range with one where either MSI-X structure resides.
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* The MSI-X Table and MSI-X PBA are permitted to co-reside within a naturally
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* aligned 4 KB address range.
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*
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* If PBA or others reside in the same BAR with MSI-X Table, devicemodel could
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* emulate them and maps these memory range at the 4KB boundary. Here, we should
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* make sure only intercept the minimum number of 4K pages needed for MSI-X table.
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*/
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/* The higher boundary of the 4KB aligned address range for MSI-X table */
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addr_hi = msix->mmio_gpa + msix->table_offset + msix->table_count * MSIX_TABLE_ENTRY_SIZE;
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addr_hi = round_page_up(addr_hi);
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/* The lower boundary of the 4KB aligned address range for MSI-X table */
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addr_lo = round_page_down(msix->mmio_gpa + msix->table_offset);
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msix->intercepted_gpa = addr_lo;
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msix->intercepted_size = addr_hi - addr_lo;
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(void)register_mmio_emulation_handler(vdev->vpci->vm, vmsix_table_mmio_access_handler,
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msix->intercepted_gpa, msix->intercepted_gpa + msix->intercepted_size, vdev);
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}
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return 0;
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return ret;
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}
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static int vmsix_deinit(struct pci_vdev *vdev)
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