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hv: instr_emul: refine decode_prefixes to one exit point
Misra C requires Function must have only one return entry. Tracked-On: #861 Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -1698,76 +1698,80 @@ static bool segment_override(uint8_t x, enum cpu_reg_name *seg)
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return override;
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}
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static int32_t decode_prefixes(struct instr_emul_vie *vie,
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enum vm_cpu_mode cpu_mode, bool cs_d)
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static int32_t decode_prefixes(struct instr_emul_vie *vie, enum vm_cpu_mode cpu_mode, bool cs_d)
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{
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uint8_t x, i;
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int32_t ret = 0;
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for (i = 0U; i < VIE_PREFIX_SIZE; i++) {
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if (vie_peek(vie, &x) != 0) {
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return -1;
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}
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if (x == 0x66U) {
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vie->opsize_override = 1U;
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} else if (x == 0x67U) {
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vie->addrsize_override = 1U;
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} else if (x == 0xF3U) {
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vie->repz_present = 1U;
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} else if (x == 0xF2U) {
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vie->repnz_present = 1U;
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} else if (segment_override(x, &vie->segment_register)) {
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vie->seg_override = 1U;
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} else {
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ret = -1;
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break;
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}
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vie_advance(vie);
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}
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/*
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* From section 2.2.1, "REX Prefixes", Intel SDM Vol 2:
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* - Only one REX prefix is allowed per instruction.
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* - The REX prefix must immediately precede the opcode byte or the
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* escape opcode byte.
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* - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3)
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* the mandatory prefix must come before the REX prefix.
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*/
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if ((cpu_mode == CPU_MODE_64BIT) && (x >= 0x40U) && (x <= 0x4FU)) {
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vie->rex_present = 1U;
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vie->rex_w = (x & 0x8U) != 0U ? 1U : 0U;
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vie->rex_r = (x & 0x4U) != 0U ? 1U : 0U;
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vie->rex_x = (x & 0x2U) != 0U ? 1U : 0U;
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vie->rex_b = (x & 0x1U) != 0U ? 1U : 0U;
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vie_advance(vie);
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}
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/*
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* Section "Operand-Size And Address-Size Attributes", Intel SDM, Vol 1
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*/
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if (cpu_mode == CPU_MODE_64BIT) {
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/*
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* Default address size is 64-bits and default operand size
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* is 32-bits.
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*/
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vie->addrsize = (vie->addrsize_override != 0U)? 4U : 8U;
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if (vie->rex_w != 0U) {
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vie->opsize = 8U;
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} else if (vie->opsize_override != 0U) {
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vie->opsize = 2U;
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} else {
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vie->opsize = 4U;
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if (x == 0x66U) {
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vie->opsize_override = 1U;
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} else if (x == 0x67U) {
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vie->addrsize_override = 1U;
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} else if (x == 0xF3U) {
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vie->repz_present = 1U;
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} else if (x == 0xF2U) {
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vie->repnz_present = 1U;
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} else if (segment_override(x, &vie->segment_register)) {
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vie->seg_override = 1U;
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} else {
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break;
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}
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vie_advance(vie);
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}
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} else if (cs_d) {
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/* Default address and operand sizes are 32-bits */
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vie->addrsize = vie->addrsize_override != 0U ? 2U : 4U;
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vie->opsize = vie->opsize_override != 0U ? 2U : 4U;
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} else {
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/* Default address and operand sizes are 16-bits */
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vie->addrsize = vie->addrsize_override != 0U ? 4U : 2U;
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vie->opsize = vie->opsize_override != 0U ? 4U : 2U;
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}
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return 0;
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if (ret == 0) {
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/*
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* From section 2.2.1, "REX Prefixes", Intel SDM Vol 2:
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* - Only one REX prefix is allowed per instruction.
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* - The REX prefix must immediately precede the opcode byte or the
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* escape opcode byte.
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* - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3)
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* the mandatory prefix must come before the REX prefix.
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*/
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if ((cpu_mode == CPU_MODE_64BIT) && (x >= 0x40U) && (x <= 0x4FU)) {
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vie->rex_present = 1U;
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vie->rex_w = (x & 0x8U) != 0U ? 1U : 0U;
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vie->rex_r = (x & 0x4U) != 0U ? 1U : 0U;
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vie->rex_x = (x & 0x2U) != 0U ? 1U : 0U;
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vie->rex_b = (x & 0x1U) != 0U ? 1U : 0U;
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vie_advance(vie);
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}
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/*
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* Section "Operand-Size And Address-Size Attributes", Intel SDM, Vol 1
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*/
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if (cpu_mode == CPU_MODE_64BIT) {
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/*
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* Default address size is 64-bits and default operand size
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* is 32-bits.
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*/
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vie->addrsize = (vie->addrsize_override != 0U)? 4U : 8U;
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if (vie->rex_w != 0U) {
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vie->opsize = 8U;
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} else if (vie->opsize_override != 0U) {
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vie->opsize = 2U;
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} else {
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vie->opsize = 4U;
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}
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} else if (cs_d) {
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/* Default address and operand sizes are 32-bits */
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vie->addrsize = vie->addrsize_override != 0U ? 2U : 4U;
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vie->opsize = vie->opsize_override != 0U ? 2U : 4U;
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} else {
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/* Default address and operand sizes are 16-bits */
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vie->addrsize = vie->addrsize_override != 0U ? 4U : 2U;
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vie->opsize = vie->opsize_override != 0U ? 4U : 2U;
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}
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}
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return ret;
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}
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static int32_t decode_two_byte_opcode(struct instr_emul_vie *vie)
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