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https://github.com/projectacrn/acrn-hypervisor.git
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hv: vpci: remove 64 bits PCI BAR map logic constraint
After reshuffle pci_bar structrue we could write ~0U not BAR size mask to BAR configuration space directly when do BAR sizing. In this case, we could know whether the value in BAR configuration space is a valid base address. As a result, we could do BAR re-programming whenever we want. Tracked-On: #3475 Signed-off-by: Li Fei1 <fei1.li@intel.com>
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@ -32,19 +32,6 @@
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#include <logmsg.h>
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#include "vpci_priv.h"
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/**
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* @pre vdev != NULL
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*/
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void vdev_pt_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val)
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{
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/* bar access must be 4 bytes and offset must also be 4 bytes aligned */
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if ((bytes == 4U) && ((offset & 0x3U) == 0U)) {
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*val = pci_vdev_read_cfg(vdev, offset, bytes);
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} else {
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*val = ~0U;
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}
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}
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/**
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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@ -191,7 +178,6 @@ static void vdev_pt_deny_io_vbar(struct pci_vdev *vdev, uint32_t idx)
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*/
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void vdev_pt_write_vbar(struct pci_vdev *vdev, uint32_t idx, uint32_t val)
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{
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bool update_bar = false;
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uint32_t update_idx = idx;
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uint32_t offset = pci_bar_offset(idx);
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struct pci_bar *vbar = &vdev->bar[idx];
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@ -203,30 +189,25 @@ void vdev_pt_write_vbar(struct pci_vdev *vdev, uint32_t idx, uint32_t val)
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pci_vdev_write_bar(vdev, idx, val);
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vdev_pt_allow_io_vbar(vdev, update_idx);
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} else {
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pci_vdev_write_cfg_u32(vdev, offset, vbar->mask);
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pci_vdev_write_cfg_u32(vdev, offset, val);
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}
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break;
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case PCIBAR_MEM64HI:
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update_idx = idx - 1U;
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/* falls through */
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case PCIBAR_MEM32:
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update_bar = true;
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/* falls through */
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case PCIBAR_MEM64:
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vdev_pt_unmap_mem_vbar(vdev, update_idx);
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if (val != ~0U) {
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pci_vdev_write_bar(vdev, idx, val);
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if (update_bar) {
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vdev_pt_map_mem_vbar(vdev, update_idx);
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}
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} else {
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pci_vdev_write_cfg_u32(vdev, offset, vbar->mask);
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}
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case PCIBAR_NONE:
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/* Nothing to do */
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break;
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default:
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/* Nothing to do */
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if (vbar->type == PCIBAR_MEM64HI) {
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update_idx = idx - 1U;
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}
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vdev_pt_unmap_mem_vbar(vdev, update_idx);
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if (val != ~0U) {
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pci_vdev_write_bar(vdev, idx, val);
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vdev_pt_map_mem_vbar(vdev, update_idx);
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} else {
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pci_vdev_write_cfg_u32(vdev, offset, val);
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}
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break;
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}
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}
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@ -299,6 +280,7 @@ void init_vdev_pt(struct pci_vdev *vdev)
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if (is_prelaunched_vm(vdev->vpci->vm)) {
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lo = (uint32_t)vdev->pci_dev_config->vbar_base[idx];
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}
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pci_vdev_write_bar(vdev, idx, lo);
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if (type == PCIBAR_MEM64) {
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idx++;
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@ -318,14 +300,12 @@ void init_vdev_pt(struct pci_vdev *vdev)
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if (is_prelaunched_vm(vdev->vpci->vm)) {
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hi = (uint32_t)(vdev->pci_dev_config->vbar_base[idx - 1U] >> 32U);
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}
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vdev_pt_write_vbar(vdev, idx - 1U, lo);
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vdev_pt_write_vbar(vdev, idx, hi);
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pci_vdev_write_bar(vdev, idx, hi);
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} else {
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vbar->size = vbar->size & ~(vbar->size - 1UL);
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if (type == PCIBAR_MEM32) {
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vbar->size = round_page_up(vbar->size);
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}
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vdev_pt_write_vbar(vdev, idx, lo);
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}
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}
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}
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@ -92,6 +92,19 @@ struct pci_vdev *pci_find_vdev(struct acrn_vpci *vpci, union pci_bdf vbdf)
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return vdev;
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}
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uint32_t pci_vdev_read_bar(const struct pci_vdev *vdev, uint32_t idx)
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{
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uint32_t bar, offset;
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offset = pci_bar_offset(idx);
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bar = pci_vdev_read_cfg_u32(vdev, offset);
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/* Sizing BAR */
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if (bar == ~0U) {
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bar = vdev->bar[idx].mask;
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}
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return bar;
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}
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void pci_vdev_write_bar(struct pci_vdev *vdev, uint32_t idx, uint32_t val)
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{
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struct pci_bar *vbar;
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@ -349,7 +349,12 @@ static int32_t vpci_read_pt_dev_cfg(const struct pci_vdev *vdev, uint32_t offset
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uint32_t bytes, uint32_t *val)
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{
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if (vbar_access(vdev, offset)) {
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vdev_pt_read_cfg(vdev, offset, bytes, val);
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/* bar access must be 4 bytes and offset must also be 4 bytes aligned */
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if ((bytes == 4U) && ((offset & 0x3U) == 0U)) {
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*val = pci_vdev_read_bar(vdev, pci_bar_index(offset));
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} else {
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*val = ~0U;
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}
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} else if (msicap_access(vdev, offset)) {
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vmsi_read_cfg(vdev, offset, bytes, val);
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} else if (msixcap_access(vdev, offset)) {
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@ -126,7 +126,6 @@ static inline bool msicap_access(const struct pci_vdev *vdev, uint32_t offset)
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}
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void init_vdev_pt(struct pci_vdev *vdev);
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void vdev_pt_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
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void vdev_pt_write_vbar(struct pci_vdev *vdev, uint32_t idx, uint32_t val);
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void init_vmsi(struct pci_vdev *vdev);
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@ -145,6 +144,7 @@ void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes,
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struct pci_vdev *pci_find_vdev(struct acrn_vpci *vpci, union pci_bdf vbdf);
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uint32_t pci_vdev_read_bar(const struct pci_vdev *vdev, uint32_t idx);
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void pci_vdev_write_bar(struct pci_vdev *vdev, uint32_t idx, uint32_t val);
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uint64_t pci_vdev_get_bar_base(const struct pci_vdev *vdev, uint32_t idx);
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#endif /* VPCI_PRIV_H_ */
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