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hv: check the availability of guest CR4 features
Check hardware support for all features in CR4, and hide bits from guest by vcpuid if they're not supported for guests OS. Tracked-On: #5586 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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442fc30117
commit
643bbcfe34
@ -115,6 +115,8 @@ static void init_vcpuid_entry(uint32_t leaf, uint32_t subleaf,
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switch (leaf) {
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case 0x07U:
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if (subleaf == 0U) {
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uint64_t cr4_reserved_mask = get_cr4_reserved_bits();
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cpuid_subleaf(leaf, subleaf, &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
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entry->ebx &= ~(CPUID_EBX_PQM | CPUID_EBX_PQE);
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@ -132,6 +134,34 @@ static void init_vcpuid_entry(uint32_t leaf, uint32_t subleaf,
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/* mask CET shadow stack and indirect branch tracking */
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entry->ecx &= ~CPUID_ECX_CET_SS;
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entry->edx &= ~CPUID_EDX_CET_IBT;
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if ((cr4_reserved_mask & CR4_FSGSBASE) != 0UL) {
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entry->ebx &= ~CPUID_EBX_FSGSBASE;
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}
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if ((cr4_reserved_mask & CR4_SMEP) != 0UL) {
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entry->ebx &= ~CPUID_EBX_SMEP;
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}
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if ((cr4_reserved_mask & CR4_SMAP) != 0UL) {
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entry->ebx &= ~CPUID_EBX_SMAP;
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}
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if ((cr4_reserved_mask & CR4_UMIP) != 0UL) {
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entry->ecx &= ~CPUID_ECX_UMIP;
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}
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if ((cr4_reserved_mask & CR4_PKE) != 0UL) {
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entry->ecx &= ~CPUID_ECX_PKE;
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}
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if ((cr4_reserved_mask & CR4_LA57) != 0UL) {
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entry->ecx &= ~CPUID_ECX_LA57;
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}
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if ((cr4_reserved_mask & CR4_PKS) != 0UL) {
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entry->ecx &= ~CPUID_ECX_PKS;
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}
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} else {
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entry->eax = 0U;
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entry->ebx = 0U;
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@ -403,6 +433,7 @@ static void guest_cpuid_01h(struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx
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{
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uint32_t apicid = vlapic_get_apicid(vcpu_vlapic(vcpu));
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uint64_t guest_ia32_misc_enable = vcpu_get_guest_msr(vcpu, MSR_IA32_MISC_ENABLE);
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uint64_t cr4_reserved_mask = get_cr4_reserved_bits();
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cpuid_subleaf(0x1U, 0x0U, eax, ebx, ecx, edx);
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/* Patching initial APIC ID */
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@ -431,7 +462,8 @@ static void guest_cpuid_01h(struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx
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/* set Hypervisor Present Bit */
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*ecx |= CPUID_ECX_HV;
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if ((get_cr4_reserved_bits() & CR4_PCIDE) != 0UL) {
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if ((cr4_reserved_mask & CR4_PCIDE) != 0UL) {
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*ecx &= ~CPUID_ECX_PCID;
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}
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@ -450,6 +482,30 @@ static void guest_cpuid_01h(struct acrn_vcpu *vcpu, uint32_t *eax, uint32_t *ebx
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}
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}
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if ((cr4_reserved_mask & CR4_VME) != 0UL) {
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*edx &= ~CPUID_EDX_VME;
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}
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if ((cr4_reserved_mask & CR4_DE) != 0UL) {
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*edx &= ~CPUID_EDX_DE;
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}
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if ((cr4_reserved_mask & CR4_PSE) != 0UL) {
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*edx &= ~CPUID_EDX_PSE;
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}
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if ((cr4_reserved_mask & CR4_PAE) != 0UL) {
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*edx &= ~CPUID_EDX_PAE;
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}
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if ((cr4_reserved_mask & CR4_PGE) != 0UL) {
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*edx &= ~CPUID_EDX_PGE;
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}
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if ((cr4_reserved_mask & CR4_OSFXSR) != 0UL) {
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*edx &= ~CPUID_EDX_FXSR;
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}
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/* mask Debug Store feature */
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*edx &= ~CPUID_EDX_DTES;
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*edx &= ~CPUID_EDX_MCE;
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@ -51,10 +51,10 @@
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#define CR4_PASSTHRU_BITS (CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | \
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CR4_PGE | CR4_PCE | CR4_OSFXSR | CR4_PCIDE | \
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CR4_OSXSAVE | CR4_FSGSBASE | CR4_OSXMMEXCPT | \
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CR4_UMIP)
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CR4_UMIP | CR4_LA57)
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static uint64_t cr4_passthru_mask = CR4_PASSTHRU_BITS; /* bound to flexible bits */
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#define CR4_TRAP_AND_PASSTHRU_BITS (CR4_PSE | CR4_PAE | CR4_SMEP | CR4_SMAP | CR4_PKE)
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#define CR4_TRAP_AND_PASSTHRU_BITS (CR4_PSE | CR4_PAE | CR4_SMEP | CR4_SMAP | CR4_PKE | CR4_PKS)
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static uint64_t cr4_trap_and_passthru_mask = CR4_TRAP_AND_PASSTHRU_BITS; /* bound to flexible bits */
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#define CR4_TRAP_AND_EMULATE_BITS 0UL /* software emulated bits even if host is fixed */
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@ -75,6 +75,7 @@
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#define CR4_OSXMMEXCPT (1UL<<10U)
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/* OS support for unmasked SIMD floating point exceptions */
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#define CR4_UMIP (1UL<<11U) /* User-Mode Inst prevention */
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#define CR4_LA57 (1UL<<12U) /* 57-bit linear address */
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#define CR4_VMXE (1UL<<13U) /* VMX enable */
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#define CR4_SMXE (1UL<<14U) /* SMX enable */
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#define CR4_FSGSBASE (1UL<<16U) /* RD(FS|GS|FS)BASE inst */
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@ -85,6 +86,7 @@
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#define CR4_SMAP (1UL<<21U)
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#define CR4_PKE (1UL<<22U) /* Protect-key-enable */
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#define CR4_CET (1UL<<23U) /* Control-flow Enforcement Technology enable */
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#define CR4_PKS (1UL<<24U) /* Enable protection keys for supervisor-mode pages */
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/* XCR0_SSE */
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#define XCR0_SSE (1UL<<1U)
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@ -72,16 +72,30 @@
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#define CPUID_EDX_TM1 (1U<<29U)
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#define CPUID_EDX_IA64 (1U<<30U)
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#define CPUID_EDX_PBE (1U<<31U)
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/* CPUID.07H:EBX.FSGSBASE*/
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#define CPUID_EBX_FSGSBASE (1U<<0U)
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/* CPUID.07H:EBX.TSC_ADJUST*/
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#define CPUID_EBX_TSC_ADJ (1U<<1U)
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/* CPUID.07H:EBX.SGX */
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#define CPUID_EBX_SGX (1U<<2U)
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/* CPUID.07H:EBX.SMEP*/
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#define CPUID_EBX_SMEP (1U<<7U)
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/* CPUID.07H:EBX.MPX */
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#define CPUID_EBX_MPX (1U<<14U)
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/* CPUID.07H:EBX.SMAP*/
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#define CPUID_EBX_SMAP (1U<<20U)
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/* CPUID.07H:ECX.UMIP */
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#define CPUID_ECX_UMIP (1U<<2U)
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/* CPUID.07H:ECX.PKE */
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#define CPUID_ECX_PKE (1U<<3U)
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/* CPUID.07H:ECX.CET_SS */
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#define CPUID_ECX_CET_SS (1U<<7U)
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/* CPUID.07H:ECX.LA57 */
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#define CPUID_ECX_LA57 (1U<<16U)
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/* CPUID.07H:ECX.SGX_LC*/
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#define CPUID_ECX_SGX_LC (1U<<30U)
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/* CPUID.07H:ECX.PKS*/
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#define CPUID_ECX_PKS (1U<<31U)
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/* CPUID.07H:EDX.CET_IBT */
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#define CPUID_EDX_CET_IBT (1U<<20U)
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/* CPUID.07H:EDX.IBRS_IBPB*/
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