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https://github.com/projectacrn/acrn-hypervisor.git
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hv: remove ACRN_REQUEST_TMR_UPDATE and unnecessary codes
Because ACRN_REQUEST_TMR_UPDATE is not needed anymore, this commit remove the MACRO definition and its related logic, including following functions: - apicv_batch_set_tmr() - vlapic_apicv_batch_set_tmr() - vlapic_set_tmr_one_vec() - vioapic_update_tmr() Tracked-On: #2343 Signed-off-by: Yan, Like <like.yan@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Yan, Like
wenlingz
parent
fc61536b07
commit
6641bc7949
@ -83,9 +83,6 @@ apicv_set_intr_ready(struct acrn_vlapic *vlapic, uint32_t vector);
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static int32_t
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apicv_pending_intr(const struct acrn_vlapic *vlapic);
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static void
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apicv_batch_set_tmr(const struct acrn_vlapic *vlapic);
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/*
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* Post an interrupt to the vcpu running on 'hostcpu'. This will use a
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* hardware assist if available (e.g. Posted Interrupt) or fall back to
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@ -1866,45 +1863,6 @@ vlapic_enabled(const struct acrn_vlapic *vlapic)
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return ret;
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}
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/*
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* APICv batch set tmr will try to set multi vec at the same time
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* to avoid unnecessary VMCS read/update.
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*/
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void
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vlapic_apicv_batch_set_tmr(struct acrn_vlapic *vlapic)
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{
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if (is_apicv_intr_delivery_supported()) {
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apicv_batch_set_tmr(vlapic);
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}
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}
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void
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vlapic_set_tmr_one_vec(struct acrn_vlapic *vlapic, uint32_t delmode,
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uint32_t vector, bool level)
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{
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ASSERT(vector <= NR_MAX_VECTOR,
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"invalid vector %u", vector);
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/*
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* A level trigger is valid only for fixed and lowprio delivery modes.
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*/
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if ((delmode != APIC_DELMODE_FIXED) && (delmode != APIC_DELMODE_LOWPRIO)) {
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dev_dbg(ACRN_DBG_LAPIC,
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"Ignoring level trigger-mode for delivery-mode %u",
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delmode);
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} else {
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/* NOTE
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* We don't check whether the vcpu is in the dest here. That means
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* all vcpus of vm will do tmr update.
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*
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* If there is new caller to this function, need to refine this
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* part of work.
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*/
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dev_dbg(ACRN_DBG_LAPIC, "vector %u set to level-triggered", vector);
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vlapic_set_tmr(vlapic, vector, level);
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}
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}
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/*
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* @pre vcpu != NULL
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* @pre vector <= 255U
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@ -2312,31 +2270,6 @@ apicv_pending_intr(const struct acrn_vlapic *vlapic)
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return ret;
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}
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/* Update the VMX_EOI_EXIT according to related tmr */
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#define EOI_STEP_LEN (64U)
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#define TMR_STEP_LEN (32U)
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static void
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apicv_batch_set_tmr(const struct acrn_vlapic *vlapic)
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{
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const struct lapic_regs *lapic = &(vlapic->apic_page);
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uint64_t val;
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const struct lapic_reg *ptr;
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uint32_t s, e;
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ptr = &lapic->tmr[0];
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s = 0U;
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e = 256U;
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while (s < e) {
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val = ptr[(s / TMR_STEP_LEN) + 1].v;
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val <<= TMR_STEP_LEN;
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val |= ptr[s / TMR_STEP_LEN].v;
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exec_vmwrite64(vmx_eoi_exit(s), val);
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s += EOI_STEP_LEN;
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}
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}
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/**
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*APIC-v: Get the HPA to APIC-access page
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* **/
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@ -405,10 +405,6 @@ int32_t acrn_handle_pending_request(struct acrn_vcpu *vcpu)
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flush_vpid_single(arch->vpid);
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}
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if (bitmap_test_and_clear_lock(ACRN_REQUEST_TMR_UPDATE, pending_req_bits)) {
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vioapic_update_tmr(vcpu);
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}
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if (bitmap_test_and_clear_lock(ACRN_REQUEST_EOI_EXIT_UPDATE, pending_req_bits)) {
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vcpu_set_vmcs_eoi_exit(vcpu);
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}
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@ -231,44 +231,6 @@ vioapic_update_eoi_exit(const struct acrn_vioapic *vioapic)
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}
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}
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/*
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* Reset the vlapic's trigger-mode register to reflect the ioapic pin
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* configuration.
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*/
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void
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vioapic_update_tmr(struct acrn_vcpu *vcpu)
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{
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struct acrn_vioapic *vioapic;
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struct acrn_vlapic *vlapic;
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union ioapic_rte rte;
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uint32_t vector, delmode;
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bool level;
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uint32_t pin, pincount;
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vlapic = vcpu_vlapic(vcpu);
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vioapic = vm_ioapic(vcpu->vm);
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spinlock_obtain(&(vioapic->mtx));
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pincount = vioapic_pincount(vcpu->vm);
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for (pin = 0U; pin < pincount; pin++) {
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rte = vioapic->rtbl[pin];
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level = ((rte.full & IOAPIC_RTE_TRGRLVL) != 0UL);
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/*
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* For a level-triggered 'pin' let the vlapic figure out if
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* an assertion on this 'pin' would result in an interrupt
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* being delivered to it. If yes, then it will modify the
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* TMR bit associated with this vector to level-triggered.
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*/
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delmode = (uint32_t)(rte.full & IOAPIC_RTE_DELMOD);
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vector = rte.u.lo_32 & IOAPIC_RTE_LOW_INTVEC;
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vlapic_set_tmr_one_vec(vlapic, delmode, vector, level);
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}
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vlapic_apicv_batch_set_tmr(vlapic);
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spinlock_release(&(vioapic->mtx));
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}
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static uint32_t
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vioapic_indirect_read(const struct acrn_vioapic *vioapic, uint32_t addr)
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{
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@ -31,17 +31,16 @@
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/*
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* VCPU related APIs
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*/
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#define ACRN_REQUEST_EXCP 0U
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#define ACRN_REQUEST_EVENT 1U
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#define ACRN_REQUEST_EXTINT 2U
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#define ACRN_REQUEST_NMI 3U
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#define ACRN_REQUEST_TMR_UPDATE 4U
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#define ACRN_REQUEST_EPT_FLUSH 5U
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#define ACRN_REQUEST_TRP_FAULT 6U
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#define ACRN_REQUEST_VPID_FLUSH 7U /* flush vpid tlb */
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#define ACRN_REQUEST_EOI_EXIT_UPDATE 8U
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#define ACRN_REQUEST_EXCP 0U
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#define ACRN_REQUEST_EVENT 1U
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#define ACRN_REQUEST_EXTINT 2U
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#define ACRN_REQUEST_NMI 3U
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#define ACRN_REQUEST_EOI_EXIT_UPDATE 4U
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#define ACRN_REQUEST_EPT_FLUSH 5U
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#define ACRN_REQUEST_TRP_FAULT 6U
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#define ACRN_REQUEST_VPID_FLUSH 7U /* flush vpid tlb */
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#define E820_MAX_ENTRIES 32U
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#define E820_MAX_ENTRIES 32U
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#define save_segment(seg, SEG_NAME) \
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{ \
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@ -99,7 +99,6 @@ void vioapic_set_irqline_lock(const struct acrn_vm *vm, uint32_t irqline, uint32
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* @return None
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*/
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void vioapic_set_irqline_nolock(const struct acrn_vm *vm, uint32_t irqline, uint32_t operation);
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void vioapic_update_tmr(struct acrn_vcpu *vcpu);
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uint32_t vioapic_pincount(const struct acrn_vm *vm);
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void vioapic_process_eoi(struct acrn_vm *vm, uint32_t vector);
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@ -227,15 +227,6 @@ int32_t vlapic_intr_msi(struct acrn_vm *vm, uint64_t addr, uint64_t msg);
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void vlapic_deliver_intr(struct acrn_vm *vm, bool level, uint32_t dest,
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bool phys, uint32_t delmode, uint32_t vec, bool rh);
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/*
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* Set the trigger-mode bit associated with 'vector' to level-triggered if
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* the (dest,phys,delmode) tuple resolves to an interrupt being delivered to
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* this 'vlapic'.
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*/
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void vlapic_set_tmr_one_vec(struct acrn_vlapic *vlapic, uint32_t delmode,
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uint32_t vector, bool level);
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void vlapic_apicv_batch_set_tmr(struct acrn_vlapic *vlapic);
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uint32_t vlapic_get_apicid(const struct acrn_vlapic *vlapic);
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int32_t vlapic_create(struct acrn_vcpu *vcpu);
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/*
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